LOLA 1553 Chip Overview

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					LOLA 1553 Chip Overview

        Rod Barto
 NASA Office of Logic Design
         5/7/2006
                    One Chip 1553 Solution
                                                                         User
                                                        DMA
     1553                                             Interface          RAM
  Transformer              SAM, WC


                                                       Discrete
                   Sital                            digital outputs
                                      Backend
                   1553
                           data       interface
                   Core
                                                      Discrete        User system
                                                    digital inputs
     1553
  Transformer              controls
                                                       Event
                                                      counters




                Actel RTAX2000S FPGA



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                    Chip Function Overview
• Internal Interfaces
     –   Discrete digital outputs
     –   Discrete digital inputs
     –   DMA interface
     –   Event counters
• External device interface
• Internal status and monitoring
     –   Command buffer
     –   Internal event counters
     –   Error conditions
     –   Status register
• Reset conditions

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               Discrete Digital Outputs
•   16 bit output
•   All set to 0 (low) on reset
•   Bits cannot be individually set
•   Bits can be read back at pins
•   Bit transitions are synchronous to clock




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                 Discrete Inputs
•   16 bit input
•   All read simultaneously
•   Synchronized to 20 MHz clock
•   Sampled every clock cycle




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               DMA and External Devices




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                    DMA Operation
• Addressing
     – 24 bit auto-incrementing register that can be
       read and written
     – Address word is read back at pin outputs
     – Address drivers are always enabled
• Data input and output busses are separate



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               External Device Operation
• External devices are those that are added
  by the user outside the 1553 chip
• Operation is the same as for DMA, except
  that addressing is by sub-address and
  word number
• Read and write timing is same as DMA
• Use same data busses as DMA

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               External Event Counters
• 16-bit rising edge triggered ripple counters
• Saturate at 2^16-1 events
• 4 counters provided
• All 4 counters read out by single 1553
  read
• All 4 counters reset by single 1553 write


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               Internal event counters
• Same as external event counters, but do
  not saturate
• 4 counters provided, currently count
     – New_command (occurs at start of every
       command received),
     – Meok (message ended OK)




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               Command buffer
• Stores last 32 commands
• Reads out most recent command first
• Resets only on core reset




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                    Status Register
• 16 bit register holding error flags
     – Upper 8 bits = 0
• Setting a bit in the register sets the
  terminal flag
• Setting the terminal flag causes an
  interface reset
• Register resets to 0000h when read

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                            Status Register Bits
Bit             name                                     meaning
 0    Write_sm_error            Illegal state in RCV mode state machine

 1    Read_sm_error             Illegal state in XMIT mode state maching

 2    Read_fifo_empty_error     Core attempted to read empty XMIT mode FIFO

 3    Rcv_fifo_full_error       Core attempted to write full RCV mode FIFO

 4    Echo_error_a              Transmission error on channel A

 5    Echo_error_b              Transmission error on channel B

 6    Message_overrun_error     In blast mode, operation not completed by time meok
                                is received
 7    Message_overtime_error    In meok mode, operation took longer than 100 usec



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                       Sub-address Summary
    SA                    Function                     Read words      Write words
     2         Status Register                                 1           0
     3         Discrete Outputs                                1           1
     4         Discrete Inputs                                 1           0
     5         External Event Counters                         4           1
     6         DMA Address Register                            2           2
     7         DMA Data Transfer                            Up to 32    Up to 32
     8         Internal Event Counters                         4           1
     9         Command Buffer                               Up to 32       0

  10-29        External Devices, User Defined
    30         1553 Readback


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                                  Usage Statistics
Compile report:
===============
Family : Axcelerator
Device : AX500
Package : 208 PQFP

Post-Combiner device utilization:
  SEQUENTIAL (R-cells)         Used: 2232   Total: 2688   (83.04%)
  COMB (C-cells)               Used: 2633   Total: 5376   (48.98%)
  LOGIC (R+C cells)            Used: 4865   Total: 8064   (60.33%)
  RAM/FIFO                     Used: 2      Total: 16     * test version only
  IO w/Clocks                  Used: 51     Total: 115
  CLOCK (Routed)               Used: 4      Total: 4
  HCLOCK (Hardwired)            Used: 1     Total: 4
  PLL                          Used: 0      Total: 8




    * Stats for test version of chip. Actual usage will be less.



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