VIEWS: 1 PAGES: 7 CATEGORY: Computers POSTED ON: 8/23/2010
The invention relates to microprocessor communications and, more particularly, to communications about a bridge chip set.BACKGROUND OF THE INVENTIONComputer systems generally provide a bus that enables communication between computer system components such as a central processing unit (CPU) and a memory. Such a bus may be referred to a system bus, a memory bus, or a host bus. Computersystems generally also include one or more secondary or peripheral buses. Such peripheral buses typically enable communication to various devices, such as input/output devices, of the computer system. The peripheral buses are typically standardized andenable the connection of various types of devices or agents to the computer system.Typical peripheral standardized buses include the Peripheral Component Interconnect (PCI) bus or bridge that links devices or agents such as video devices, disk drives, and other adapter cards. A second bus often used in connection with a PCIbus in modern computer systems is the Accelerated Graphics Port (AGP). AGP is an interface specification generally designed for the throughput demands of 3-D graphics.Communication protocol between a processor and peripheral devices or agents about a peripheral bus generally allows the transfer of chunks of data of 8 bytes or less. Such chunks represent a quad word. In addition to quad words, communicationprotocols also allow the transfer of data as four quad words or 32 bytes. Such a transfer is referred to as a cache line or burst. A cache line or burst transfer is typically faster than a transfer of four individual quad words of the same data,because the transfer of a burst allows compacting of the data.When a processor reads memory, the processor requests a section of address space in memory. That address space may typically be represented by a quad word. Typically, what the processor receives in response to its request is a cache line orburst that includes the requested quad word. The burst order refers
"Reordering Of Burst Data Transfers Across A Host Bridge - Patent 6505259"