INTRODUCING THE ITANIUM
The press and the technical com- form the basis of the IA-64 instruction set and
munity have generated much excitement and the related Itanium processor products.
speculation about the IA-64 instruction set These articles were written well in advance
John Crawford and the Itanium processor. Intel and Hewlett- of the product introduction for the Itanium
Packard have rolled out (one instruction at a processor. Consequently, the articles focus on
Intel time) the instruction set. Intel is rolling out describing what will be provided as these con-
(one transistor at a time) the Itanium proces- cepts and products come to market rather
sor and other platform components. This spe- than how well the products and concepts
cial issue provides the broad technical work. Our intention is to provide grounding
community with a comprehensive introduc- in the products and concepts to IEEE Micro
tion to the concepts and mechanisms that readers.
0272-1732/00/$10.00 2000 IEEE 9
GUEST EDITOR’S INTRODUCTION
History type compiler based on the University of Illi-
My involvement with the IA-64 instruction nois Impact compiler system2 was targeted at
set architecture started in December 1993 the evolving instruction set spec.
when HP and Intel met to discuss the oppor- The joint instruction set development pre-
tunity to collaborate on high-end micro- ceded a massive effort at Intel to prepare all of
processors. I was chartered to lead a group of the products needed to successfully launch a
Intel architects, software experts, and chip new computer architecture. Intel started ﬁrst
designers to evaluate the technical merits of one, then several, processor designs to imple-
concepts HP might bring to such a partner- ment the IA-64 instruction set. Compiler and
ship, and to present our technical capabilities operating system software development
to a corresponding group of HP experts for projects replaced prototype software develop-
their evaluation. ment, and application software development
During the first half of 1994, these two began. As this is published, Intel is preparing
teams met and exchanged information on our to bring to market its biggest product line
64-bit directions and capabilities. To provide since the launch of the 386 processor in 1985.
protection of our mutual intellectual proper- Certainly, the next several years will continue
ty, the teams agreed to establish a neutral site to be interesting for all of us involved in Intel’s
at an HP training ofﬁce in Santa Clara, rough- Itanium processor products.
ly midway between the Intel site in Santa
Clara, the HP site in Cupertino, and HP Labs EPIC and ILP
in Palo Alto. A conference room was dedicat- The IA-64 instruction set is based on a set
ed to the task, with two large ﬁling cabinets, of concepts that we describe as EPIC, for
one assigned to each company. All of our notes, Explicitly Parallel Instruction Computing.
along with any printed material received from Our belief is that EPIC is the next advance
the other company, were stored in these cabi- beyond RISC that’s needed to keep on the per-
nets and locked when we left the room. All we formance treadmill deﬁned by Moore’s law of
could leave with was what was in our heads. If doubling performance every 18 months, or an
HP and Intel decided not to form a joint activ- annual growth rate of 1.6 times. Improve-
ity, the agreement was to destroy the contents ments in the underlying silicon technology
of the cabinets. There were no corresponding yield about a 1.2-times annual improvement
restrictions placed on our use of the residual rate via faster silicon devices. The rest must be
information content in our brains. made up with improvements in circuit design
Corresponding teams met to determine the and in parallel execution, by overlapping the
business merits of such a partnership, and the execution of more instructions through deep-
merits of cooperation in other technical areas. er pipelining (to enable a higher clock rate)
The investigations went well, and on 6 June and/or executing more instructions in paral-
1994, HP and Intel announced formation of lel. This second kind of parallelism is known
a joint research activity to develop a 64-bit as instruction-level parallelism, or ILP, and is
instruction set architecture that would measured as the number of instructions exe-
become the basis for a line of Intel micro- cuted each clock cycle (IPC).
processors. At that time I was asked to lead an Our belief is that the EPIC techniques will
HP-Intel team to jointly deﬁne the instruc- enable us to stay on the curve of increasing
tion set architecture. levels of ILP.
This architecture team was formed from
both Intel and HP with computer architects, Hardware-compiler interface
compiler and operating system software EPIC is based on the premise that the com-
experts, and chip designers. Over the next year piler has much better visibility into program
or two the joint team produced a series of execution than does the hardware. Certainly
speciﬁcations that reﬂected the best concepts, the compiler can look at a much larger win-
judgment, and data from both companies and dow, and it has more time for analysis (sec-
external researchers. (Schlansker and Rau onds versus nanoseconds). What it’s missing
recount the HP history.1) Functional and per- is knowledge of individual dynamic events
formance simulators were built, and a proto- such as individual branch taken/not taken,
10 IEEE MICRO
and cache hit/miss, although there may be sta- structure of this large system with a remote
tistical aggregate information on these events and local latency ratio of 1.5, and RAS fea-
if proﬁle data is available. tures to support enterprise applications.
There are three main tenets of an EPIC “High Availability and Reliability in the Ita-
architecture. It provides nium Processor” describes a set of capabilities
for detecting, containing, reporting, and
• mechanisms to enable the compiler to recovering from hardware failures in processor
arrange the computation efﬁciently based and external buses. These features are impor-
on its global knowledge, tant in the enterprise-computing application
• sufﬁcient resources such as registers and area that is a key target of the initial Itanium
functional units to perform multiple processor systems.
operations in parallel, and to store the
“inventory” of intermediate results, and
instruction formats that let the compiler
communicate to the hardware the key
W e’ve scheduled more articles for
upcoming issues of IEEE Micro.
information it has gleaned from the pro- References
gram as it’s compiled. 1. M.S. Schlansker and B.R Rau, “EPIC:
Explicitly Parallel Instruction Computing,”
Each of these three key EPIC characteris- Computer, Feb. 2000, pp. 37-45.
tics are embodied in the IA-64 instruction set 2. W.W. Hwu et al, “Compiler Technology for
and are described in the ﬁrst article, “Intro- Future Microprocessors,” IEEE Proc., Vol.
ducing the IA-64 Architecture.” This article 83, No. 12, Dec. 1995, pp. 1625-1640.
describes the key concepts and mechanisms
provided in the instruction set at a high level, John Crawford is an Intel Fellow who has
along with the main motivations behind the worked at Intel for 23 years, 5 as a software
inclusion of these mechanisms. The focus of developer and 18 as a computer architect.
this article is on the instruction set as seen by Prior to managing the joint Intel-HP team
all programs (both applications and the oper- that deﬁned the IA-64 instruction set, he was
ating system). Virtual memory support in IA- the chief architect of the 386 and 486 micro-
64 includes better support for sharing (up to processors and comanaged the Pentium
and including support for a single address processor development. Crawford earned a BS
space) that we expect to happen with the large degree from Brown and an MS degree from
increase in addressing that comes with a 64- the University of North Carolina, both in
bit architecture. computer science. He received the ACM-
“The Itanium Processor Microarchitecture” IEEE Eckert-Mauchly award in 1995 and the
describes the internal structure of the first IEEE Ernst Weber Engineering Leadership
processor to implement the IA-64 instruction Recognition in 1996.
set. It emphasizes how the processor supports
EPIC constructs such as predication, control
and data speculation, and multiway branches. Direct comments about this special issue to
The compiler is a key component of per- John H. Crawford, Intel Corp., SC12-304,
formance in an Itanium processor-based sys- 2200 Mission College Blvd., Santa Clara, CA
tem. “The Intel IA-64 Compiler Code 95052-8119; email@example.com.
Generator” describes the structure and con-
siderations for the code generation phase of a
compiler that targets the IA-64 instruction set
from the point of view of how the generated
code makes use of EPIC constructs.
“The AzusA 16-Way Itanium Server”
describes thea server system developed by
NEC for enterprise-level computing applica-
tions. The article discusses the system archi-
tecture and the partitioning and clustering
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