VIEWS: 2 PAGES: 13 CATEGORY: Computers POSTED ON: 8/13/2010
1. Field of the InventionThis invention relates to the field of computer systems and, more particularly, to prefetching mechanisms for reducing effective memory latency within computer systems.2. Description of the Related ArtSuperscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. On the other hand, superpipelined microprocessor designs divideinstruction execution into a large number of subtasks which can be performed quickly, and assign pipeline stages to each subtask. By overlapping the execution of many instructions within the pipeline, superpipelined microprocessors attempt to achievehigh performance.Superscalar microprocessors demand low memory latency due to the number of instructions attempting concurrent execution and due to the increasing clock frequency (i.e. shortening clock cycle) employed by the superscalar microprocessors. Many ofthe instructions include memory operations to fetch (read) and update (write) memory operands. The memory operands must be fetched from or conveyed to memory, and each instruction must originally be fetched from memory as well. Similarly,superpipelined microprocessors demand low memory latency because of the high clock frequency employed by these microprocessors and the attempt to begin execution of a new instruction each clock cycle. It is noted that a given microprocessor design mayemploy both superscalar and superpipelined techniques in an attempt to achieve the highest possible performance characteristics.Microprocessors are often configured into computer systems which have a relatively large, relatively slow main memory. Typically, multiple dynamic random access memory (DRAM) modules comprise the main memory system. The large main memoryprovides storage for a large number of instructions and/or a large amount of data for use by the microprocessor, providing faster access to the instructio
"Chipset Configured To Perform Data-directed Prefetching - Patent 6247107"