/Sasha / 09-Sep-99
APEmille assembler instructions.
TARZAN Arithmetic operations
TADD reg3 reg1 reg2 TSUB reg3 reg1 reg2 TMUL reg3 reg1 reg2 TDIV reg31 reg32 reg1 reg2 TMULA reg3 reg1 reg2 [reg3] [reg3] [reg3] <= [reg1]+[reg2] <= [reg1]-[reg2] <= [reg1]x[reg2] (31 LSB's) 37 5 3(1) 3 5
[reg31] <= [reg1]/[reg2] , [reg32] <= rest [reg3(31)] <= sign ( [reg1(31,22:0)]x[reg2(31:0)] ) [reg3(30:23)] <= [reg1(30:23)] [reg3(22:0)] <= SHR31 ( [reg1(31,22:0)]x[reg2(31:0)] ) [reg3] <= [reg0]+[reg1]+[reg2] [reg3] <= [reg0]+[reg1]-[reg2] [reg4] <= disp [reg4] <= disp+[reg0] [reg4] <= disp+[reg0]+[reg1]
TADD3 TSUB3 TAGU1 TAGU2 TAGU3
reg3 reg0 reg1 reg2 reg3 reg0 reg1 reg2 reg4 disp reg4 disp.reg0 reg4 disp.reg0.reg1
3 3 2 3 3
TARZAN logic and bitwise operations
TAND TOR TXOR TNAND TNOR TXNOR TASH TLSH TROT reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 reg3 reg1 reg2 [reg3] [reg3] [reg3] [reg3] [reg3] [reg3] [reg3] [reg3] [reg3] <= [reg1]AND[reg2] <= [reg1]OR[reg2] <= [reg1]XOR[reg2] <= [reg1]NAND[reg2] <= [reg1]NOR[reg2] <= [reg1]XNOR[reg2] <= ASH [reg2][reg1] (Restriction: <= LSH [reg2][reg1] (Restriction: <= LSH [reg2][reg1] 3 3 3 3 3 3 3 -32<[reg2] <32 ) 3 -32<[reg2] <32) 3
Flow control (Tarzan) instructions
TEQ reg1 reg2 TNE reg1 reg2 TGT reg1 reg2 TLT reg1 reg2 TGE reg1 reg2 TLE reg1 reg2 TINCCOMP reg0 reg1 reg2 if( [reg1]=[reg2] ) then Flag <=’1’ if( [reg1]!=[reg2] ) then Flag <=’1’ if( [reg1]>[reg2] ) then Flag <=’1’ if( [reg1]<[reg2] ) then Flag <=’1’ if( [reg1]>=[reg2] ) then Flag <=’1’ if( [reg1]=<[reg2] ) then Flag <=’1’ if( ([reg0]+[reg1] )>[reg2] ) then Flag <=’1’ [reg0] <= zero_disp + [reg0] +[reg1] 4 4 4 4 4 4 4
(1)
length of a microcommand in number of PM words.
1
TANY TNONE TCNB TGETPC reg4 JUMP
*
if( Gif=’1’ ) then Flag <=’1’ if( Gif=’0’ ) then Flag <=’1’ if( CNB=’1’ ) then Flag <=’1’ [reg4] [PC] <= PC <= *label+[reg0] (+[reg1])
1 1 1 2 1 1
label.reg0.(reg1)
*
JUMPIF
label.reg0.(reg1)
*
If( Flag =’1’) then [PC] <= *label+[reg0] (+[reg1]) else [PC] <= [PC]+1 If(Flag =’0’) then [PC] <= *label+[reg0] (+[reg1]) else [PC] <= [PC]+1 [reg4] <= [PC] <= *label + [reg0] (+[reg1])
JUMPIFNOT
*
label.reg0.(reg1)
1
GOSUB
label.reg0.(reg1)
reg4 [PC]
10
LABEL BREAK HALT
*
label
Symbolic reference to an address of a following instruction Soft Exception
halt_code(4-bits)
2
JANE single precision arithmetics (floating point 32 bist).
JSNORM_αβ reg3 reg0 reg1 reg2 [reg3] <= α ( [reg0]x[reg1] + β[reg2] ) Where α, β = P(+),M(-) [reg3] <= ABS( [reg0]x[reg1] + β[reg2] ) Where β = P(+),M(-) [reg3] <= α ( [reg0] + β[reg1] + γ[reg2] ) Where α, β, γ = P(+),M(-) [reg3] <= ABS ( [reg0] + β[reg1] + γ[reg2] ) Where β, γ = P(+),M(-) [reg3] <= α ( [reg0]x[reg1] + β[reg2] ) [reg3+1] <= α ( [reg0+1]x[reg1+1] + β[reg2+1] ) where α, β = P(+),M(-) ; reg0,1,2,3 are even [reg3] <= ABS( [reg0]x[reg1] + β[reg2] ) [reg3+1] <= α ( [reg0+1]x[reg1+1] + β[reg2+1] ) where β = P(+),M(-) ; reg0,1,2,3 are even zn(2) 10 if(3)
JSNORM_Aβ reg3 reg0 reg1 reg2 JSADD3_αβγ JSADD3_Aβγ JVNORM_αβ reg3 reg0 reg1 reg2 reg3 reg0 reg1 reg2 reg3 reg0 reg1 reg2
z?
10
if
zn
10
if
z?
10
if
zn
12
if
JVNORM_Aβ reg3 reg0 reg1 reg2
zn
12
if
JANE complex single precision arithmetics(floating point 32 bist).
JCNORM_ αβ reg3 reg0 reg1 reg2 12 if [reg3]C <= α ( [reg0]C x [reg1]C + β[reg2]C ) where JCNORM_ Aβ reg3 reg0 reg1 reg2 α, β = P(+),M(-); reg0,1,2,3 are even; [reg]C=[reg] +i[reg+1] - complex z 12 if z
[reg3]C <= ( ABS (REAL ([reg0]C x [reg1]C + β[reg2]C ) + i * ABS (IMAGE ([reg0]C x [reg1]C + β[reg2]C ) ) where α, β = P(+),M(-); reg0,1,2,3 are even; [reg]C=[reg] +i[reg+1] - complex
JANE double precision arithmetics(floating point 64 bits).
JDNORM_ αβ reg3 reg0 reg1 reg2 12 if [reg3]D <= α ( [reg0]D x[reg1]D + β[reg2]D ) Where JDNORM_A αβ reg3 reg0 reg1 reg2 α, β = P(+),M(-) ;reg0,1,2,3 are even; [reg]D = [reg+1] &[reg] z? 12 if zn
[reg3] D <= ABS ( [reg0]D x[reg1]D + β[reg2]D ) Where α, β = P(+),M(-) ;reg0,1,2,3 are even; [reg]D = [reg+1] &[reg]
JANE integer arithmetics (interger 32 bits).
JIADD JISUB JIMULT reg3 reg0 reg1 reg3 reg0 reg1 reg3 reg0 reg1 reg3 reg0 reg3 reg0 [reg3] <= [reg0] + [reg1] [reg3] <= [reg0] - [reg1] [reg3] <= [reg0] x [reg1] [reg3] <= INTEGER ( log 2 [reg0] ) [reg3] <= number of 1’s in [reg0] zn zn zn zn 4 4 if if
10 if 4 4 if if
JILEADONE JIBITCOUNT
JANE logic and bitwise operations
JIAND reg3 reg0 reg1 [reg3] <= [reg0] AND [reg1] [reg3] <= [reg0] NAND [reg1] zn 4 zn if
JINAND reg3 reg0 reg1 4 if
(2) (3)
condition outputs of the FILU affected by the command. writing the result to the destination may be conditioned.
3
JIOR reg3 reg0 reg1 4 if JIXOR reg3 reg0 reg1 JILSH reg3 reg0 reg1 JIASH reg3 reg0 reg1 JIROT reg3 reg0 reg1
[reg3] <= [reg0] OR [reg1]
zn
[reg3] <= [reg0] XOR [reg1] [reg3] <= LSH [reg1] [reg0] [reg3] <= ASH [reg1] [reg0] [reg3] <= ROT [reg1] [reg0]
zn zn zn zn
4 4 4 4
if if if if
JANE LUT operations (fetching a value or a seed of the requested value).
JSLUTONE reg4 [reg4] <= single precision ONE [reg4i]S <= single precision LSB [reg4i] <= seed ( 1/[ reg4o] ) [reg4i] <= seed ( 1/ [reg4o]1/2 ) [reg4i] <= [reg4o] [reg4i] <= - [reg4o] [reg4i] <= seed (e [ reg4o] ) [reg4i] <= 1 _seed (log e [reg4o] ) [reg4i] <= 2nd_seed (log e [reg4o] ) [reg4]D <= double precision ONE [reg4i]D <= double precision LSB [reg4o] [reg4]D <= seed ( 1/[reg4] D ) reg4 [reg4]D <= seed ( 1/ [reg4] D [reg4i] D <= [reg4o] D [reg4i] D <= - [reg4o] D [reg4i] D <= seed (e
[ reg4o] D) 1/2 st
1 [reg4o] 3 3 3 3 3 3 3 1 1 3 )
if
JSLUTLSB reg4i reg4o 1 if JSLUTINV reg4i reg4o JSLUTINVSQRT reg4i reg4o JSLUTMOVE reg4i reg4o JSLUTCHS reg4i reg4o JSLUTEXP reg4i reg4o JSLUTLOGM reg4i reg4o JSLUTLOGE JDLUTONE reg4i reg4o reg4
if if if if if if if if if if
JDLUTLSB reg4i reg4o JDLUTINV reg4
JDLUTINVSQRT 3 if
JDLUTMOVE reg4i reg4o JDLUTCHS reg4i reg4o JDLUTEXP reg4i reg4o JDLUTLOGM reg4i reg4o JDLUTLOGE reg4i reg4o JVLUTONE reg4
3 3 3 3 3 1
if if if if if if
[reg4i]D <= 1st_seed (log e [reg4o]D) [reg4i] D <= 2nd_seed (log e [reg4o]D) [reg4] <= single precision ONE [reg4+1] <= single precision ONE [reg4i] <= single precision LSB [reg4o]
JVLUTLSB reg4i reg4o 1 if
[reg4i +1] <= single precision LSB [reg4o +1] JVLUTINV reg4i reg4o 3 if [reg4i] <= seed ( 1/[ reg4o] )
[reg4i +1] <= seed ( 1/[ reg4o +1] ) JVLUTINVSQRT reg4i reg4o JVLUTMOVE reg4i reg4o 3 if [reg4i] <= seed ( 1/ [reg4o] 1/2 ) [reg4i +1] <= seed ( 1/ [reg4o +1] 1/2 ) [reg4i] <= [reg4o] 3 if
[reg4i +1] <= [reg4o+1]
4
JVLUTCHS reg4i reg4o JVLUTEXP reg4i reg4o JVLUTLOGM reg4i reg4o JVLUTLOGE reg4i reg4o
[reg4i] <= - [reg4o] [reg4i +1] <= - [reg4o+1] [reg4i] <= seed (e [ reg4o] ) [reg4i +1] <= seed (e [ reg4o+1] ) [reg4i] <= 1st_seed (log e [reg4o]) [reg4i +1] <= 1st_seed (log e [reg4o +1]) [reg4i] <= 2nd_seed (log e [reg4o]) [reg4i +1] <= 2nd_seed (log e [reg4o +1])
3 3
if if
3
if
3
if
JANE type conversion instructions
JSTOD reg3 reg0 JDTOS reg3 reg0 JSTOI reg3 reg2 JDTOI reg3 reg2 JITOS reg3 reg2 JITOD reg3 reg2 [reg3]D <= convert ( [reg0]S ) [reg3]S <= convert ( [reg0]D ) [reg3]i <= convert ( [reg2]S ) [reg3]i <= convert ( [reg2]D ) [reg3]S <= convert ( [reg2]i ) [reg3]D <= convert ( [reg2]i ) zn zn zn zn zn zn 12 12 10 10 10 10 if if if if if if
JANE local boolean conditions and IF stack
JSPUSHEQ JSPUSHNE JSPUSHGT JSPUSHLT JSPUSHGE JSPUSHLE reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1 PushStack ; TopStack <= ( [reg0]S = [reg1]S ); PushStack ; TopStack <= ( [reg0]S != [reg1]S); PushStack ; TopStack <= ( [reg0]S > [reg1]S); PushStack ; TopStack <= ( [reg0]S < [reg1]S ); PushStack ; TopStack <= ( [reg0]S >= [reg1]S); PushStack ; TopStack <= ( [reg0]S =< [reg1]S); PushStack ; TopStack <= ( [reg0]C = [reg1]C ); Reg0,1 are even. PushStack ; TopStack <= ( [reg0]C != [reg1]C ); Reg0,1 are even. PushStack ; TopStack <= ( [reg0]D = [reg1]D ); Reg0,1 are even PushStack ; TopStack <= ( [reg0]D != [reg1]D ); Reg0,1 are even PushStack ; TopStack <= ( [reg0]D > [reg1]D ); Reg0,1 are even PushStack ; TopStack <= ( [reg0]D < [reg1]D ); Reg0,1 are even PushStack ; TopStack <= ( [reg0]D >= [reg1]D ); Reg0,1 are even PushStack ; TopStack <= ( [reg0]D =< [reg1]D ); Reg0,1 are even PushStack ; TopStack <= ( [reg0] i = PushStack ; TopStack <= ( [reg0] i != PushStack ; TopStack <= ( [reg0] i > PushStack ; TopStack <= ( [reg0] i < [reg1] i ); [reg1] i ); [reg1] i ); [reg1] i ); 11 11 11 11 11 11
JCPUSHEQ JCPUSHNE
reg0 reg1 reg0 reg1
13 13
JDPUSHEQ JDPUSHNE JDPUSHGT JDPUSHLT JDPUSHGE JDPUSHLE
reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1
13 13 13 13 13 13
JIPUSHEQ JIPUSHNE JIPUSHGT JIPUSHLT
reg0 reg1 reg0 reg1 reg0 reg1 reg0 reg1
5 5 5 5
5
JIPUSHGE JIPUSHLE
reg0 reg1 reg0 reg1
PushStack ; TopStack <= ( [reg0] i >= PushStack ; TopStack <= ( [reg0] i =< PushStack ; TopStack <= TopStack PopStack
[reg1] i ); [reg1] i );
5 5 1 1 1 1 1 1 1 1
JSTKREPUSH JPOP JSTKAND JSTKOR JSTKXOR JSTKRESET JSTKANDBIS JSTKSWAP
TopStack <= TopStack AND uTopStack; PopStack Where uTopStack - a stack element under the TopStack. TopStack <= TopStack OR uTopStack; PopStack TopStack <= TopStack XOR uTopStack; PopStack; ClearStack TopStack <= TopStack AND uTopStack If StackEmpty elsif StackUno else TopStack <= ‘0’ , tempTop <= ‘0’, PushStack; TopStack<=tempTop , tempTop <=TopStack ; TopStack<=uTopStack, uTopStack<=TopStack .
JSTKNOT
TopStack <= NOT TopStack
1
6
Data transfer instructions
MEMTOT1 treg4 disp [treg4] [treg4] [treg4] <= TzDM[disp] <= TzDM[disp+[treg0]] <= TzDM[disp+[treg0] +[treg1]] 7 7 7 2 2 2 if if if if if if
MEMTOT2 treg4 disp.treg0 MEMTOT3 treg4 disp.treg0.treg1 TTOMEM1 disp treg4 TTOMEM2 disp.treg0 treg4 TTOMEM3 disp.treg0.treg1 treg4
TzDM[disp] <= [treg4] TzDM[disp+[treg0]] <= [treg4] TzDM[disp+[treg0] +[treg1]] <= [treg4] [jreg4 + i ] <= JnDM[disp + LOF + i], i=0,…(N-1)
MEMTOJ1 if
jreg4: N
disp
12+N/2
Where (disp + LOF) and jreg4 must be both even or odd. MEMTOJ2 if jreg4: N disp.treg0 [jreg4 + i ] <= JnDM[disp + [treg0] + LOF + i], i=0,…(N-1) 12+N/2
Where (disp+[treg0]+LOF) and jreg4 must be both even or odd. MEMTOJ4 jreg4: N if disp.treg0.treg1 [jreg4 + i ] <= JnDM[disp + [treg0] + [treg1] + LOF + i], i=0,…(N-1) 12+N/2
Where (disp+[treg0] ]+[treg1]+LOF) and jreg4 must be both even or odd. JTOMEM1 disp jreg4: N JnDM[disp + LOF + i] <= [jreg4 + i ], i=0,…(N-1) Where (disp + LOF) and jreg4 must be both even or odd. JnDM[disp + [treg0] + LOF + i] <= [jreg4 + i ], i=0,…(N-1) 8+N/2 if
JTOMEM2 disp.treg0 8+N/2 if
jreg4: N
Where (disp+[treg0]+LOF) and jreg4 must be both even or odd. JTOMEM3 disp.treg0.treg1 jreg4: N JnDM[disp + [treg0] + [treg1] + LOF + i] <= [jreg4 + i ], i=0,…(N-1) Where (disp+[treg0]+[treg1]+LOF) and jreg4 must be both even or odd. [jreg4] <= disp + [treg0] + [treg1] 8+N/2 if
TTOJ JTOT
jreg4 treg4 14
disp.treg0.treg1 jreg4 if
5
if
translated to consecutive JTOC jreg4 and CTOT treg4
JTOC jreg4
ch_xreg(i) <= [jreg4] Where i= 0..7 corresponds to the Jane numbers. ch_xreg(i) <= 1st B[jreg4], 1st B[jreg4], 1st B[jreg4], 1st B[jreg4] Where i= 0..7 corresponds to the Jane numbers. ch_yreg(i) <= 2nd B[jreg4], 2nd B[jreg4], 2nd B[jreg4], 2nd B[jreg4] Where i= 0..7 corresponds to the Jane numbers. ch_zreg(i) <= 3d B[jreg4], 3d B[jreg4], 3d B[jreg4], 3d B[jreg4] Where i= 0..7 corresponds to the Jane numbers. [treg4] <= ch_xreg(0)
6
if
JTOC0 jreg4
6
if
JTOC1 jreg4
6
if
JTOC2 jreg4
6
if
CTOT treg4 7 if JLOFRESET JLOFSET jreg4
LOF <= 0x00000000 LOF <= [jreg4]
1 1
if if
7
Memory initialisation.
TCONST tadr const TzDM[tadr] <= const Restrictions: tadr =< 0x1FFFF. JnDM[jadr] <= const Restrictions: jadr =< 0x3FFF. JnDM[jadr] <= flp_const Restrictions: jadr < 0x3FFF jadr - even. JnDM[jadr] <= flp_const1 JnDM[jadr+1] <= flp_const2 Restrictions: jadr < 0x3FFF jadr - even.
JCONST
jadr const
JCONSTD jadr {flp_const}
JCONSTV jadr const1 const2
8