Keypad Scanner System by frt17672

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									Keypad Scanner System                                       Thursday FEB 14th 2008




Keypad Scanner System

                                                    Project Report 1




                                                          Nagarjuna Surapaneni




The Ohio State University || Project Report 1   ECE 667 Digital Logic Lab || Page 1
Keypad Scanner System                                             Thursday FEB 14th 2008


                                                                Report Format

Section 1:            Abstract………………………………………………………………………………..03

Section 2:            Introduction……………………………………………………………………………03

Section 3             Keypad Scanner Simulator…………………………………………………………….04

     Section 3.1:     Discussion……………………………………………………………………………..05

     Section 3.2:     Implementation and Testing…………………………………………………………...06

Section 3.5           Keypad Simulator……………………………………………………………………...09

     Section 3.5.1:   Discussion……………………………………………………………………………...09

    Section 3.5.2:    Implementation and Testing…………………………………………………………...10

Section 3.6           Clock Divider………………………………………………………………………….13

   Section 3.5.1:     Discussion……………………………………………………………………………..13

   Section 3.5.2:     Implementation and Testing…………………………………………………………...13

Section 4:            Integration……………………………………………………………………………..16

Section 5:            Hardware settings……………………………………………………………………...17

Section 6:            Conclusion …………………………………………………………………………….19

Section 7:            Appendix……………………………………………………………………………....20




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Keypad Scanner System                                                                      Thursday FEB 14th 2008




                                                                                Section 1:Abstract
This Project aims at development of the Keypad Scanner System components. Keypad scanner has 6 components..

     1)   Column Scanner
     2)   Row Encoder
     3)   Output Data Latch
     4)   Keypad Scanner System Controller
     5)   Keypad Simulator
     6)   Clock Divider

In this Report we aim at design and development of 4-6 components (among the six components stated above) and
integrate them to obtain Keypad Scanner System with desired functionalities.




                                                                        Section 2:Introduction
1.   Column Scanner upon activation of the Enable terminal will sequentially ground one of the four outputs C[3..0]
     and corresponding count value would be placed in two output lines COL[1..0].

2.   Row Encoder has soon as it detects logic 0 at inputs (ROW[3..0]) ZDET output would be asserted and encoded
     value of the row would be placed in the ROW[1..0].

3.   Output Data Latch upon assertion of the load signal encoded values of the ROW and COL have to be latched.

First three components 1) Column Scanner 2) Row Encoder 3) Output Data Latch and their design and
implementation are presented in the earlier report.

4.   Keypad Scanner System Controller is designed to co-ordinate the signals in among the various components and
     outside world.

5.   Keypad Simulator simulates the keypad board used. This helps to remove the logical errors that might have
     caused in the during the design process.

6.   Clock Divider brings down the system clock to the desired frequency of interest.

In this report, we shall see the design and implementation of components 4) Keypad Scanner System Controller 5)
Keypad Simulator 6) Clock Divider and integration of these six components was presented. In later part of the
document keypad simulator is removed and replaced with hardware module of keypad scanner and tested.

To proceed further into design it would be better to have idea about combinational logical circuit design and state
machine design.


Digital Logic Design may be divided into two classes: Combinational Logic and Sequential Logic. If Output
depends only on the current inputs its combinational logic design. If the Output depends on the current inputs and
past output then its sequential logic.



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Keypad Scanner System                                                                      Thursday FEB 14th 2008




This report deals with the Design of three modules used in the Keypad Scanner System. While designing These
modules, we need to have an idea about the current inputs and Past Output (previous state) . In this case D flip flops
and basic gates (logical and or not) are used to build the desired hardware. Past outputs might not be needed for all
the modules, these modules can be designed using logic gates.

Finite State Machine or State Machine is model in which circuit moves around fixed sates based on the variation in
the input and output. Information about the past state is stored and based on the current input, system decides on
which state to stay

Now let us look at the Sub Modules 4-6(The Keypad Scanner, Keypad simulator and Clock Divider).



                         Section 3:KeyPad Scanner System Controller
Keypad Simulator is designed to co-ordinate the signals in the systems, as well as the outside world when valid key
is detected. It has 2 inputs. 1) RE_ZDET and 2) Clock and three outputs 1) CS_ENA 2) LATCH_LD 3) VALID

RE_ZDET is output of the row detector which gets activated when any of the rows of the keypad is pressed. When
System is powered in CS_ENA is high and should turn to low immediately.

It should wait for a period of 10ms and then check value of ZDET. If ZDET remains high then Valid and Latch
needs to enabled

If after 10ms ZDET turns out to be low then false key press is detected and VALID and LATCH signals are made
low and CS_ENA signals should be made high.




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Keypad Scanner System                                                                    Thursday FEB 14th 2008


                                                                          Section 3.1:Discussion




                            Fig 3.1 Flow Chart of the logical sequence flow

Shows the flow chart of the logical sequence explained in statements above.

When RE_ZDET is high CS_ENA=0 immediately and timer is started for 10msec.

If Re_ZDET remains high after 10ms then VALID, LATCH_LD are made high and CS_ENA ia remained at
zero. If RE_ZDET remains low after 10ms CS_ENA should be made high.

This is shown in the state diagram.

CIRCUIT DESIGN:

RE_ZDET is connected to the enable of the mod 10 counter, If it remains high for 10 pulses then it is detected by c3
not(c2) c1 not(c0). This output is latched with DFF to hold the high pulse till RE_ZDET falls low this is achived by
connecting RE_ZDET to CLR of DFF.

So Design Equations for Valid and Latch

DFFin=ZDET AND ((c3) AND (NOT (c2)) AND (c1) AND (NOT (c0))) OR Q;

CLK=RE_ZDET;

VALID=LATCH_LD= (Q)

And

CS_ENA is inversion of RE_ZDET

So CS_ENA= NOT (RE_ZDET)


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Keypad Scanner System                                                                       Thursday FEB 14th 2008



                                              Section 3.2:Implementation and Testing
 The above derived equations are realized in Altrea software and hardware circuit is built and its simulated to verify
 its functionality.
 .




                                Fig 3.2.1 Hardware Implementation in Altera software



This Circuit is simualated for functional verfication.




                                             Fig 3.2.2 Functional behavior
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Keypad Scanner System                                                            Thursday FEB 14th 2008


In the first shaded region we can observe the RE_ZDET becoming high then CS_ENA becomes low immediately
and since RE_ZDET is not 10 pulses long VALID or LATCH_LD is not enabled. In the second shaded region
RE_ZDET is high for long time and we can observe the LATCH_LD and VALID rising high and when RE_ZDET
falls then VALID and LATCH_LD are made low and CS_ENA is made high.

AHDL code:

SUBDESIGN P1

(

RE_ZDET,CLOCK:INPUT;

CS_ENA,LATCH_LD,VALID:OUTPUT;

)

VARIABLE

C[3..0]:DFF;

SS:MACHINE OF BITS (A[1..0])

WITH STATES(ONE,CNT,TWO,THREE);

BEGIN

SS.CLK=CLOCK;

CASE SS IS

    WHEN ONE => CS_ENA=B"1";

         LATCH_LD=B"0";

                  VALID=B"0";

          IF (RE_ZDET==1) THEN

                  CS_ENA=B"1";

                  else

          SS=CNT;

                                  CS_ENA=B"0";

                                 C[].D=B"0000";

         ENDIF;

    WHEN CNT =>

         LATCH_LD=B"0";

                  VALID=B"0";

          CS_ENA=B"0";

          C[].CLK=CLOCK;

          C[].D=C[].Q + 1;

                                          IF C[].Q==9 THEN


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Keypad Scanner System                                                          Thursday FEB 14th 2008

        SS=TWO;

        C[].D=B"0000";

       END IF;

 WHEN TWO =>

      IF (RE_ZDET == 0) THEN

                               SS=ONE;

                               ELSE

                               SS=THREE;

                               END IF;

       WHEN THREE =>

              CS_ENA=B"0";

              LATCH_LD=B"1";

              VALID=B"1";

       IF (RE_ZDET ==0) THEN

                               VALID=B"0";

                               SS=ONE;

                               END IF;

       END CASE;

       END;




                                 Fig 3.2.3Simlated Functional Behavior

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Keypad Scanner System                                                                       Thursday FEB 14th 2008




                                                          Section 4:Keypad Simulation

It simulates the matrix keyboard. It has same inputs has Matrix Key Board and emulates it by providing same
output. So this block gives us a scope to check the logic before we can actually proceed further.


After designing and verifying the components in order to simulate the entire system when all the separate parts are
put together we need keypad simulator. It has 3 inputs 1) Key[3..0] 2) Assert 3) Column Scanner output and has one
output R[3..0].




                                           Fig 4.1 Keypad Simulator Block


                                                                            Section 4.1:Discussion
Basic operation of the keypad simulator is
    1) When not asserted all the R[3..0] must be high
    2) When assert line is high then based on the value sent by the key corresponding column value gets transfred
        to the row value




                                             Fig 4.1.1 Keypad Simulator

Let us assume Key 5 is pressed and values in the C1 should pass into the R1


The Ohio State University || Project Report 1                              ECE 667 Digital Logic Lab || Page 9
Keypad Scanner System                                                                         Thursday FEB 14th 2008


Column scanner takes the task of oscillating the zero between the columns. And once the zero is reflected in the
R[3..0] the ZDET would be high and column scanner enable will be disabled looking column scanner in the same
postion.

Design:

We can observe that R0 get the values only if keys 0,1,2,3 are pressed. So when any of these keyvalue is pressed the
corresponding line of the 4:16 multiplexer is activated.

C0 is passed only if keys 0,4,8,9 are pressed. So keys are properly selected to be given as OR (as 4:16 is active low
and Or ing would just pass the value leaving other all at high). Then AND operation is performed to obtain R[3..0]

So Design Equation are

R0= (Key0)(C0)+ (Key1)(C1)+ (Key2)(C2)+ (Key3)(C3)
R1= (Key4)(C0)+ (Key5)(C1)+ (Key6)(C2)+ (Key7)(C3)
R2= (Key8)(C0)+ (Key9)(C1)+ (KeyA)(C2)+ (KeyB)(C3)
R3= (KeyC)(C0)+ (KeyD)(C1)+ (KeyE)(C2)+ (KeyF)(C3)



                                               Section 4.2:Implementation and Testing
 The above design equations are implemented and in hardware in Altera software




                                     Fig 4.2 Hardware design of Keypad Simulator



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Keypad Scanner System                                                                 Thursday FEB 14th 2008


The above circuit is simulated by feeding in arbitrary values for the keys and C[3..0]. in part ice when we
interconnect the whole circuit values of c[3..0] would be generated by the column scanner. However we
can observe that when key 8 is pressed values of C0 is passing that of R2 and we can observe the outputs.

Same can be observe in second shaded region.




                                       Fig 4.3 Functional verfication.

This hardware behavior model can be developed in either VHDL or AHDL

AHDL code:



SUBDESIGN P2

 (

     KEY[3..0]:INPUT;

     C[3..0]:INPUT;

     ASSERT1: INPUT;

     OUTPUT_R[3..0]:OUTPUT;

  )

VARIABLE

  K[15..0]:NODE;

  R[3..0]:NODE;

BEGIN


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Keypad Scanner System                                              Thursday FEB 14th 2008


 CASE KEY[] IS

 WHEN H"0" => R[0]=C[0];

 R[1]=VCC;

R[2]=VCC;

R[3]=VCC;

 WHEN H"1" => R[0]=C[1];R[1]=VCC;R[2]=VCC;R[3]=VCC;

 WHEN H"2" => R[0]=C[2];R[1]=VCC;R[2]=VCC;R[3]=VCC;

 WHEN H"3" => R[0]=C[3];R[1]=VCC;R[2]=VCC;R[3]=VCC;

 WHEN H"4" => R[0]=VCC;R[1]=C[0];R[2]=VCC;R[3]=VCC;

 WHEN H"5" => R[0]=VCC;R[1]=C[1];R[2]=VCC;R[3]=VCC;

 WHEN H"6" => R[0]=VCC;R[1]=C[2];R[2]=VCC;R[3]=VCC;

 WHEN H"7" => R[0]=VCC;R[1]=C[3];R[2]=VCC;R[3]=VCC;

 WHEN H"8" => R[0]=VCC;R[1]=VCC;R[2]=C[0];R[3]=VCC;

 WHEN H"9" => R[0]=VCC;R[1]=VCC;R[2]=C[1];R[3]=VCC;

 WHEN H"A" => R[0]=VCC;R[1]=VCC;R[2]=C[2];R[3]=VCC;

 WHEN H"B" => R[0]=VCC;R[1]=VCC;R[2]=C[3];R[3]=VCC;

 WHEN H"C" => R[0]=VCC;R[1]=VCC;R[2]=VCC;R[3]=C[0];

 WHEN H"D" => R[0]=VCC;R[1]=VCC;R[2]=VCC;R[3]=C[1];

 WHEN H"E" => R[0]=VCC;R[1]=VCC;R[2]=VCC;R[3]=C[2];

 WHEN H"F" => R[0]=VCC;R[1]=VCC;R[2]=VCC;R[3]=C[3];

 END CASE;

 IF ASSERT1==1 THEN OUTPUT_R[]=R[];

 ELSE OUTPUT_R[]=H"F";

 END IF;

END;




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Keypad Scanner System                                                                                Thursday FEB 14th 2008




                             Fig. 4.4 Output wave form of the Simulated AHDL circuit

Thus We can observe in the shaded region when key 5 is pressed value in C[1] is passed into the value in
R[1].


                                          Section5:4MHz to 1Khz Clock Divider
We have a master ossillator at 4 MHz and our keypad simulator need not operate that high speeds. So clock is
brought down by having a clock divider.


                                                                                    Section 5.1:Discussion
We must design a frequency divider that would reduce 4 Mhz to 1 Khz counter. Total number of bits needed to achive this would
be

(4x10^6)/(10^3)=(4x10^3)

So for every 4000 cycles of the master clock one cycle has to be completed to achieve frequency of 1 KHz. So need to design a
mod 2000 counter and which reset it every time at 2000 count value and use the 2000 count value to flip the state of the q in the
DFF. Let us take a closer look into it.



                                                 Section 5.2:Implementation and Testing
Up counter can be designed by simple technique…

Q10        Q09         Q08        Q07         Q06        Q05         Q04        Q03         Q02        Q01        Q00
0          0           0          0           0          0           0          0           0          0          0
0          0           0          0           0          0           0          0           0          0          1
0          0           0          0           0          0           0          0           0          1          0
0          0           0          0           0          0           0          0           0          1          1
0          0           0          0           0          0           0          0           1          0          0
0          0           0          0           0          0           0          0           1          0          1
0          0           0          0           0          0           0          0           1          1          0
0          0           0          0           0          0           0          0           1          1          1
0          0           0          0           0          0           0          1           0          0          0
….         …           …          …           …          …           …          …           …          …          …

The Ohio State University || Project Report 1                                      ECE 667 Digital Logic Lab || Page 13
                                                                                                                                       D1             D2                           D3                                           D4                                                                                D5                                                    D6                                   D7
                                                                                                                                                                                                                                                                                                                                                                                                                                                D8                             D9
                                                                                                                                            XOR                           XOR      DFF
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            D10                            D11
                                                                                                                              DFF                    DFF                                                         XOR                                               DFF                             XOR          DFF                                      XOR             DFF                        XOR           DFF                  XOR      DFF                  XOR      DFF
                                                                                                                                                                                         PRN                                                                                                                                                                                                                                                                                                       XOR      DFF                  XOR      DFF
                                                                                                                                  PRN                   PRN                             D Q                                                                           PRN                                             PRN                                                     PRN                                    PRN                              PRN                        PRN
                                                                                                                                 D Q                   D Q                                                                                                           D Q                                             D Q                                                     D Q                                    D Q                              D Q                        D Q                               PRN                        PRN
                                                                                                                                            inst14                        inst15                                                                                                                                                                                                                                                                                                                              D Q                           D Q
                                                                                                                                                                                                                 inst22                                                                            inst26                                                inst28                                     inst30                             inst32                        inst34
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              Keypad Scanner System




                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   inst36                        inst37
                                                                                                                                                                                        CLRN
                                                                                                                                     CLRN                 CLRN                     inst4                                                                                CLRN                                         CLRN                                                     CLRN                                     CLRN                          CLRN                          CLRN
                                                                                                                              inst                   inst3                                                                                                         inst11                                       inst12                                                   inst13                                   inst17                        inst18                        inst19                             CLRN                          CLRN
                                                                                                           pin_name   INPUT                                                                                                                                                                                                                                                                                                                                                                                 inst20                        inst21
                                                                                                                       VCC                                       AND2                          AND2                                                                                                                                                                                  AND2                                     AND2                          AND2
                                                                                                                                                                                                                                                                                          AND2                                     AND2                                                                                                                                                   AND2                          AND2


                                                                                                                                                                 inst23                        inst24                                                                                                                                                                                inst31                                   inst33                        inst35
                                                                                                                                                                                                                                                                                          inst27                                       inst29                                                                                                                                             inst39                        inst38




The Ohio State University || Project Report 1
                                                The above circuit is simulated for logical verification.
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      Table5.2.1: Upcounter




                                                                                                                                                                                                                                                                                                                                                AND2
                                                                                                                                                                                                                                                                                                               NOT                                                                            DFF
                                                                                                                                                                                                                                                                                                                                                               OR2                               PRN
                                                                                                                                                                                                                                                                                                               inst48                           inst49                                          D Q




                                                                                                                                                                                                             2
                                                                                                                                                                                                                                                                                                                                          NOT




                                                                                                                                                                                                                                                                                                                                                               inst51
                                                                                                                                                                                                                                                                                                                            ins t 52




                                                                                                                                                                                                                                                                                                                                                AND2
                                                                                                                                                                                                                                                                                                    ins t 25
                                                                                                                                                                                                                                                                                                                                                                                                   CLRN




                                                                                                                                                                                                        NAND1
                                                                                                                                                                                                                                                                                                                                                                                              inst40
                                                                                                                                                                                                                                                                                                                                                inst50

                                                                                                                                                                                                                   ins t 43
                                                                                                                                                                                                                                ins t 44
                                                                                                                                                                                                                                             ins t 45
                                                                                                                                                                                                                                                        ins t 46
                                                                                                                                                                                                                                                                               ins t 41




                                                                                                                                                                                                        NOT
                                                                                                                                                                                                                 NOT
                                                                                                                                                                                                                              NOT
                                                                                                                                                                                                                                           NOT
                                                                                                                                                                                                                                                                         NOT




                                                                                                                                                                                                                                                             VCC
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              Thursday FEB 14th 2008




ECE 667 Digital Logic Lab || Page 14
Keypad Scanner System                                                                               Thursday FEB 14th 2008


From the table we can observe that there is a change of state when previous Q values are all ones and
current q values is zero. So anding all the pervious values of q and ex-or with current q value would be
next state of the D filp flop.




                                                         Fig 5.2.1 Simulated output.

We can observe that there is a togle of the output value at 500us which is 0.5 ms…so total time period of the pulse
genarated is 1 ms and so frequency is 1 Khz.

This hardware behavior model can be developed in either VHDL or AHDL

AHDL code:

SUBDESIGN P3

( count[10..0],out: OUTPUT;

clock : INPUT;

)

VARIABLE

y[10..0],xf: DFFE; % Ten D flip-flops with enable %

var:node;

BEGIN

y[].ena = VCC; % flip-flops always enabled %

y[].clk = clock; % Specify the clock for the D flip-flops %

xf.clk = clock;

xf.ena=VCC;

y[].d = y[].q + 1; % Next count is current count plus one %

count[] = y[].q; % Assign the outputs of the flip-flops to the

output of the system %

if (count[]== H"7D0") then

y[].d=B"0";

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Keypad Scanner System                                                                      Thursday FEB 14th 2008

xf.d=not(xf.q);

out=xf.q;

else

xf.d=xf.q;

out=xf.q;

end if;

END;




                                      Fig 5.2.2 Simulated outputfor AHDL Code

We can observe that there is a togle of the output value at 500us which is 0.5 ms…so total time period of the pulse
genarated is 1 ms and so frequency is 1 Khz.




                                                                         Section 6: Integration
Towards our goal of designing Keypad Scanner System, We have designed all of its modules

       1) Column Scanner: Cable of scanning up to four columns in a standard matrix-type keypad.
       2) Row Encoder: Cable of reading the rows being scanned by the column scanner.
       3) Output Data Latch: Cable of latching the encoded values of the row and column in a register
          bank.
       4) Keypad Scanner System: Controller is designed to co-ordinate the signals in among the various
          components and outside world.
       5) Keypad Simulator: Simulates the keypad board used. This helps to remove the logical errors that might
          have caused in the during the design process.
       6) Clock Divider: Brings down the system clock to the desired frequency of interest.

Checked all the modules are working fine individually. Then logical symbols are created for each these blocks
and combined in another Block Diagram/Schematic file. Connections are shown below.




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Keypad Scanner System                                                              Thursday FEB 14th 2008




                                    Fig 6.1 Keypad Scanner System
After interconnecting the each module as shown in the above schematic it’s simulated.




                            Fig 6.2 Simulated Output of the Integrated Circuit

We can notice that the values pressed by key are getting latched in to O/P of the DFF. There is a delay of
10 pulses which is caused by keypad system controller as it waits for 10 ms to ascertain that its valid key
press.


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Keypad Scanner System                                                                    Thursday FEB 14th 2008


Now we remove the keypad simulator from the design and compile it again.




                                       Fig 6.1 Final Keypad Scanner System

Matrix keyboard connect externally would provide the values of R[3..0] to row encoder. So it the keypad
simulator is removed and loaded into the ALTREA Programmable chip.

                                   Section 7:Hardware Connection Scheme
After the circuit is simulated now it loaded into ALTERA MAX7000S series chip which has 80 pins. Assign the
output pins of the chip to the software terminals nodes when have created to connect to external world. Connections
are made to the matrix keypad and to data latch and BCD to 7 Segment decoder IC 7448 (TTL)

So parts used are

    1.   Altera CPLD: Altera's MAX(R) series of CPLDs are world-class, low cost solutions for a wide variety of
         digital applications. Instant-on MAX CPLDs represent the ultimate in flexibility, as they can be
         independent programmable solutions or complement other semiconductors in a system. MAX CPLDs are
         non-volatile, single-chip solutions that do not require additional configuration devices. This means that
         they can be preprogrammed and reprogrammed using in-system programmability (ISP) and will retain the
         programming algorithm securely, even when the device is powered off.




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Keypad Scanner System                                                                       Thursday FEB 14th 2008


    2.   Matrix Keypad Simulator: based on the key pressed corresponding column value is to the row value while
         others are kept at high. Row Encoder takes pain of encoding the low signal line to the digital equivalent bits
         and column encoder does that for columns and these values together give the value of the key pressed.




                                                 Fig 7.1 Matrix 4X4 Keypad

    3.   BCD to 7 Segment Display Decoder IC 7448: 7 segment display has 7 inputs used to control each of the
         LED. There would be a common pin connected to ground or Vcc. So by properly controlling the values of
         the lines a,b,c,d,e,f,g we can make the desired hex-decimal number displayed. IC 7448 does this task of
         controlling those lines. It converts the BCD number to 7 segment display equivalent so those LEDS could
         glow displaying the number.

    4.   Crystal oscillator: We have used 4 MHz Crystal oscillator and internally developed a module which can
         generate 1 KHz from this. So our internal FF work on 1 KHZ clock cycle.



Once the connections are made circuit is simulated. The Key pressed in 4x4 matrix keypad should be displayed in 7
segment display




                                                                           Section 8:Conclusion
We have started with identification of the sub modules required for the Keypad scanner and developed and tested
each of those sub modules independently and then integrated them in a single module by creating the symbols with
keypad simulator in first go. Once this is achieved key pad simulator is removed and 4X4 matrix keypad simulator is
added to the hardware of the chip by proper interconnections. Pins from chip to various ICs (IC 7448, Keypad
matrix) are connected properly. After loading program and proper interconnections circuit is operated.

We observe the value of key pressed in the matrix Keypad is getting latched and is displayed in the 7 segment
display. Thus we have developed Keypad scanner system.




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Keypad Scanner System                                                              Thursday FEB 14th 2008


                                                                       Section 8:Appendix
First three sub modules we presented in the previous lab report and

Homework 3 being related document is attached.




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