# Logic Circuits and Computer Architecture - PowerPoint

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```					Logic Circuits and
Computer Architecture

Appendix A
Digital Logic Circuits

Part 2:   Combinational and
Sequential Circuits

RLAC (2008-09) by Luciano Gualà   A-   1
Combinational circuits

• Each of the m outputs can be expressed as
function of n input variables
• Truth table has:
 n input columns
 m output columns
 2n rows (all possible input combinations)
RLAC (2008-09) by Luciano Gualà   A-   2

A=a3a2a1a0
C=c4c3c2c1c0 : the sum of A and B
B=b3b2b1b0

b3 a 3           b2 a2                b1 a1       b0 a0

Combinational Circuit
c4          c3               c2                   c1       c0

RLAC (2008-09) by Luciano Gualà             A-   3
Seven-segment decoder
It converts a 4-bit binary-coded decimal (BCD) value into the code
required to drive a seven-segment display

a
a
b                   f           b
A
Combinational         c                       g
B                               d
C            Circuit            e
D                               f                   e           c
g

d

A=0 B=1
C=1 D=1
A=0 B=0
C=0 D=0
RLAC (2008-09) by Luciano Gualà                     A-   4
The truth table

RLAC (2008-09) by Luciano Gualà   A-   5
Design Procedure

1.       Specification
     Write a specification for the circuit if one is not already
available
2.       Formulation
     Derive a truth table or initial Boolean equations that define
the required relationships between the inputs and outputs, if
not in the specification
     Apply hierarchical design if appropriate
3.       Optimization
     Apply 2-level and multiple-level optimization
     Draw a logic diagram or provide a netlist for the resulting
circuit using ANDs, ORs, and inverters

RLAC (2008-09) by Luciano Gualà                A-   6
Design Procedure

4. Technology Mapping
   Map the logic diagram or netlist to the
implementation technology selected
5. Verification
   Verify the correctness of the final design manually
or using simulation

RLAC (2008-09) by Luciano Gualà      A-   7
Design Example

1. Specification
   BCD to Excess-3 code converter
   Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
   BCD code words for digits 0 through 9: 4-bit patterns
0000 to 1001, respectively
   Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to each
BCD code word
   Implementation:
•   multiple-level circuit
RLAC (2008-09) by Luciano Gualà   A-   8
Design Example (continued)

2.       Formulation
    Conversion of 4-bit codes can be most easily formulated
by a truth table       Input BCD            Output Excess-3
    Variables                AB C D                  WXYZ
- BCD:
0000                   0011
A,B,C,D                 0001                   0100
    Variables                 0010                   0101
- Excess-3                0011                   0110
W,X,Y,Z                 0100                   0111
    Don’t Cares               0101                   1000
- BCD 1010                0110                   1001
to 1111                0111                   1010
1000                1011
1001                1100
RLAC (2008-09) by Luciano Gualà          A-   9
Design Example (continued)
z                                  C                y                                  C
1                              1                   1                     1
0        1           3           2                 0        1            3           2

3. Optimization             1
4        5           7
1
6
1
4        5
1
7           6

X        X           X         X           B       X        X            X        X            B
a. 2-level using             12       13          15        14                  12       13           15       14

A    1                    X         X               A   1                     X        X
K-maps                     8        9          11        10                   8        9           11       10

W = A + BC + BD                               D                                                  D
X = B’C + B’D + BC’D’
Y = CD + C’D’         x                                    C               w                                  C
1        1           1
Z = D’                           0           1         3           2                0           1         3            2

1                                                               1        1            1
4           5         7           6                4           5         7            6

X        X            X           X        B       X        X            X            X        B
12       13           15          14               12       13           15           14

A         8
1
9
X
11
X
10
A   1
8
1
9
X
11
X
10

RLAC (2008-09) by Luciano Gualà
D                                                  DA-       10
Design Example (continued)
3. Optimization (continued)
b. Multiple-level optimization: we start from
W = A + BC + BD
X = B C + B D + BCD
Y = CD + C D
Z=D                              G = 7 + 10 + 6 + 0 = 23
   …and we obtain:
W = A + BT
X = B’T + BC’D’                  where         T=C+D
Y = CD + C’D’
Z = D’                                     G = 19
RLAC (2008-09) by Luciano Gualà             A - 11
Design Example (continued)

A
W

B                                      X

C                                      Y
D
Z

RLAC (2008-09) by Luciano Gualà       A - 12
Beginning Hierarchical Design
• To control the complexity of the function mapping inputs to
outputs:
 Decompose the function into smaller pieces called blocks
 Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
 Any block not decomposed is called a primitive block
 The collection of all blocks including the decomposed ones is a
hierarchy
• Example: comparison circuit for 4-bit words
 Specification:
 Input: vectors A(3:0) and B(3:0); Ai Bi: i-th element of A and B,
respectively
 Output: a variable E; E=1 if and only if A=B
 Formulation:
 is it convenient to derive the truth table?
RLAC (2008-09) by Luciano Gualà            A - 13
A0
A1
A2
A3
B0         E
B1
B2
B3

Ni=0 iff Ai=Bi
RLAC (2008-09) by Luciano Gualà   A - 14
Reusable Functions

• Whenever possible, we try to decompose a
function blocks
• These blocks are
 verified and well-documented
 placed in libraries for future use

RLAC (2008-09) by Luciano Gualà   A - 15
Top-Down versus Bottom-Up

• A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
• A bottom-up design starts with detailed primitive blocks and
combines them into larger and more complex functional blocks

• Design usually proceeds top-down to known building blocks
ranging from complete CPUs to primitive logic gates or
electronic components.

RLAC (2008-09) by Luciano Gualà           A - 16
Functions and Functional Blocks
• The functions considered are those found to be very
useful in design
• Corresponding to each of the functions is a
combinational circuit implementation called a functional
block
• In the past, functional blocks were packaged as small-
scale-integrated (SSI), medium-scale integrated (MSI),
and large-scale-integrated (LSI) circuits.
• Today, they are often simply implemented within a
very-large-scale-integrated (VLSI) circuit.

RLAC (2008-09) by Luciano Gualà     A - 17
Real circuits

 74LS00 - has four 2-input NAND gates
 Small scale integration (SSI)
RLAC (2008-09) by Luciano Gualà   A - 18
Integrated circuits

• Scales of integration

•   (Small)        SSI: 1-10 gates
•   (Medium)       MSI: 10-100 gates
•   (Large)        LSI: 100-100.000 gates
•   (Very Large)   VLSI: > 100.000 gates

RLAC (2008-09) by Luciano Gualà   A - 19
Decoder (n-to-2n)

• Convert n inputs to exactly one of 2n outputs
i.e., given an n-bit value i in input the decoder
activates only the i-th output line

An example
decoder
2-to-4
0        D0
A0       20             1        D1
A1       21             2        D2
3        D3

RLAC (2008-09) by Luciano Gualà   A - 20
Decoder Examples
A   D0 D1
D0    A              1-to-2 decoder
0       1    0
1       0    1         A                        D1    A

A0
A1 A0       D0 D1 D2 D3
A1
0   0       1      0       0   0                                         D0   A1 A0
0   1       0      1       0   0
1   0       0      0       1   0
1   1       0      0       0   1                                         D1   A1 A0

(a)
D2   A1 A0

2-to-4 decoder
D3   A1 A0
RLAC (2008-09) by Luciano Gualà                    A - 21
(b)
A 3-to-8 decoder

RLAC (2008-09) by Luciano Gualà   A - 22
a                                                    a b c d
b
c                    equivalent to
d

a                                                    a b c d
b
c                    equivalent to
d

A2
Inputs

A1

A0

3-to-8 decoder
D0 D1      …          D7
RLAC (2008-09) by Luciano Gualà             A - 23
A different circuit for a 3-to-8 decoder

RLAC (2008-09) by Luciano Gualà   A - 24
Decoder Expansion

• General procedure for building a decoder with n inputs
and 2n outputs
• This procedure builds a decoder backward from the
outputs
• We take 2n 2-input AND gates (output AND gates)
• The output AND gates are driven by two decoders with
their numbers of inputs either equal or differing by 1
• These decoders are then designed using the same
procedure until 2-to-1-line decoders are reached

RLAC (2008-09) by Luciano Gualà    A - 25
Decoder Expansion - Example 1

• 3-to-8-line decoder
 Number of output ANDs = 8
 Number of inputs to decoders driving output ANDs = 3
 Closest possible split to equal
• 2-to-4-line decoder
• 1-to-2-line decoder
 2-to-4-line decoder
• Number of output ANDs = 4
• Number of inputs to decoders driving output ANDs = 2
• Closest possible split to equal
 Two 1-to-2-line decoders

RLAC (2008-09) by Luciano Gualà         A - 26
Decoder Expansion - Example 2
• 6-to-64-line decoder
 Number of output ANDs = 64
 Number of inputs to decoders driving output ANDs = 6
 Closest possible split to equal
• two 3-to-8-line decoders
 3-to-8-line decoder
• Number of output ANDs = 8
• Number of inputs to decoders driving output ANDs = 3
• Closest possible split to equal
 2-to-4-line decoder
 1-to-2-line decoder
 …

RLAC (2008-09) by Luciano Gualà           A - 27
RLAC (2008-09) by Luciano Gualà   A - 28
Decoder with Enable

• See truth table below for function
 Note use of X’s to denote both 0 and 1
 Combination containing two X’s represent four binary combinations

EN A1 A0      D0 D1 D2 D3

0    X   X   0   0   0   0
1    0   0   1   0   0   0
1    0   1   0   1   0   0
1    1   0   0   0   1   0
1    1   1   0   0   0   1

RLAC (2008-09) by Luciano Gualà              A - 29
E
S1

S0

RLAC (2008-09) by Luciano Gualà   A - 30
3-to-8 decoder from
two 2-to-4 decoders with enable
decoder
2-to-4
A0                             0       D0
20             1       D1
A1
21             2       D2
3       D3
A2
Enable

decoder
2-to-4
0           D4
20             1           D5
21             2           D6
3           D7
Enable

RLAC (2008-09) by Luciano Gualà        A - 31
Combinational Logic Implementation
- Decoder and OR Gates

• Implement m functions of n variables with:
 Sum-of-minterms expressions
 One n-to-2n-line decoder
 m OR gates, one for each output
• Approach 1:
 Find the truth table for the functions
 Make a connection to the corresponding OR from
the corresponding decoder output wherever a 1
appears in the truth table
• Approach 2
 Find the minterms for each output function
 OR the minterms together

RLAC (2008-09) by Luciano Gualà   A - 32
Decoder and OR Gates Example

A0               0                 F1
A1               1
2
A2               3
Finding sum of                              4
A3                                 F2
minterms expressions                        5
6
7
F1 = m (1,2,5,6,8,11,12,15)                8
F2 = m (1,3,4,6,8,10,13,15)                9
10                 F3
F3 = m (2,3,4,5,8,9,14,15)                11
12
13
14
15

RLAC (2008-09) by Luciano Gualà   A - 33
Exercise

• Use a decoder and or gates to build a
combinatorial circuit with
 INPUT: 3 boolean variables
 OUTPUT: the number of 1s in the input (expressed in
binary)

RLAC (2008-09) by Luciano Gualà   A - 34
Solution: Truth Table

A0      A1      A2      D1       D0
0      0       0        0       0
0      0       1        0       1
0      1       0        0       1
0      1       1        1       0
1      0       0        0       1
1      0       1        1       0
1      1       0        1       0
1      1       1        1       1

RLAC (2008-09) by Luciano Gualà   A - 35
Solution: the implementation
OR Gates

A0

A1

A2

D1     D0
RLAC (2008-09) by Luciano Gualà        A - 36
Encoding

• Encoding - the opposite of decoding - the conversion of an
m-bit input code to a n-bit output code with n m  2n
such that each valid code word produces a unique output
code
• Circuits that perform encoding are called encoders
• An encoder has 2n (or fewer) input lines and n output lines
which generate the binary code corresponding to the input
values
• Typically, an encoder converts a code containing exactly
one bit that is 1 to a binary code corresponding to the
position in which the 1 appears.
RLAC (2008-09) by Luciano Gualà     A - 37
a truth table for a 8-to-3 encoder

A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7
RLAC (2008-09) by Luciano Gualà   A - 38
Encoder Example

• A decimal-to-BCD encoder
 Inputs: 10 bits corresponding to decimal digits 0
through 9, (D0, …, D9)
 Outputs: 4 bits with BCD codes
 Function: If input bit Di = 1, then the output (A3,
A2, A1, A0) is the BCD code for i
• Exercise: design and realize it

RLAC (2008-09) by Luciano Gualà       A - 39
Priority Encoder

• An encoder has two drawbacks:
 If more than one input value is 1, then the
encoder just designed does not work
 if all inputs are 0, the encoder responds as when
D0=1
• Priority encorder
 Among the 1s that appear, it selects the most
significant input position (or the least significant
input position) containing a 1 and responds with
the corresponding binary code for that position

RLAC (2008-09) by Luciano Gualà       A - 40
Priority encoder with 4 inputs

V=1 iff at least one input is 1
Xs in input part of table represent 0 or 1;
thus table entries correspond to product terms

RLAC (2008-09) by Luciano Gualà   A - 41
RLAC (2008-09) by Luciano Gualà   A - 42
Selecting
• Selecting of data or information is a critical
function in digital systems and computers
• Circuits that perform selecting have:
 A set of information inputs from which the
 A single output
 A set of control lines for making the selection
• Logic circuits that perform selecting are
called multiplexers

RLAC (2008-09) by Luciano Gualà       A - 43
Multiplexer (Mux) 2n-to-1

• 2n data inputs -- 1 output
• n controls, to select one of the inputs to be
“sent” to the output
Example: 4-to-1 mux                Truth table
S1 S0   F
0   0   D0
Logic symbol                     0   1   D1
1   0   D2
1   1   D3
RLAC (2008-09) by Luciano Gualà                A - 44
Logic circuit for a 4-to-1 Mux

RLAC (2008-09) by Luciano Gualà   A - 45
Example: 4-to-1-line Multiplexer

Decoder
S1

S0                                      Enabling circuits
Decoder
S1

S0
D0

D1
Y

F

D2

D3

RLAC (2008-09) by Luciano Gualà                    A - 46
Exercise

• Consider a 2-to-1 multiplexer:
 2 data inputs: D0 and D1
 1 control input: S0
 1 data output: F
• Write
 Truth table
 Logic circuits which implements it
• Extend it to deal with 4 bits at a time

RLAC (2008-09) by Luciano Gualà   A - 47
2-to-1 mux

S F                   D0
0 D0                  D1                 F

1 D1
S

D0
F
S
D1

RLAC (2008-09) by Luciano Gualà           A - 48

RLAC (2008-09) by Luciano Gualà   A - 49
How to use multiplexers to
implement functions

• 2n-to-1 mux for a n-variable function

A   B   C   F
0
0   0   0   0                  1
0   0   1   1                  1
0
0   1   0   1                  0                  F
0
0   1   1   0                  1
1
1   0   0   0
1   0   1   0
1   1   0   1                           ABC
1   1   1   1
RLAC (2008-09) by Luciano Gualà       A - 50
How to use multiplexers to
implement functions

• 2n-1-to-1 mux for a n-variable function

A   B   C   F
0   0   0   0                                  C
F=C
0   0   1   1                                  C’
0   1   0   1                                   0          F
F=C’
0   1   1   0                                   1
1   0   0   0
F=0
1   0   1   0
1   1   0   1                                        A B
F=1
1   1   1   1
RLAC (2008-09) by Luciano Gualà             A - 51
De-multiplexer (Demux)

• 1 input -- 2n data outputs --
• n controls, to select exactly one of the outputs
S0 S1 D0 D1 D2 D3
Example: 1-to-4 demux
0 0 E
input: E, controls: S0 , S1
1 0       E
outputs: D0 , D1 , D2 , D3
0       1        E
1       1             E

Truth table
RLAC (2008-09) by Luciano Gualà                 A - 52
Logic circuit for a 1-to-4 Demux

It is equal to a decoder with enable
Sometimes it is called decoder/demultiplexer
RLAC (2008-09) by Luciano Gualà   A - 53
Programmable Logic Device (PLD)

• What is a PLD?
 A circuit that can be “programmed” after the
manufacturing process
• Why PLD?
 A PLD can be:
• programmed to implement large numbers of different low-
volume designs

RLAC (2008-09) by Luciano Gualà         A - 54
How to program a PLD
• Different programming technologies are used to control
connections
• Some technologies:
   Fuse
   Antifuse
   Single-bit storage element
   Stored charge on a floating transistor gate
• We will see two PLDs:
 PLA: Programmable Logic Array

RLAC (2008-09) by Luciano Gualà   A - 55

• They are just a
A0    A1     A   D3   D2   D1      D0
combinational circuits                             2
with n inputs and m                   0      0     0   1    0    0        0
output!
0      0     1   0    0    0        1
• It can be viewed as a
memory with the inputs                0      1     0   0    0    0        1
as addresses of data                  0      1     1   0    0    1        1
(output values)                       1      0     0   0    0    0        1
• data are embedded into                1      0     1   0    0    1        1
the circuit                           1      1     0   1    0    1        1
• 2n words of m bits                    1      1     1   0    1    0        1

RLAC (2008-09) by Luciano Gualà                      A - 56
ROM: the circuit

• A ROM is made by a decoder followed by a
second module combining minterms to give the
desired functions (matrix of OR gates)
• First module: a decoder
 Fixed AND array with 2n outputs implementing all n-
literal minterms.
• Second module:
 Programmable OR Array with m outputs lines to form
up to m sum of minterm expressions

RLAC (2008-09) by Luciano Gualà    A - 57
The implementation
programmable OR array

A0

A1

A2

D3      D2   D1   D0
RLAC (2008-09) by Luciano Gualà             A - 58
…a ROM not yet programmed…
programmable OR array

A0

A1

A2

D3      D2   D1   D0
RLAC (2008-09) by Luciano Gualà             A - 59
Programmable Logic Array (PLA)

• A PLA for sum of products is made by
 a first module combining inputs to form products
(programmable array of AND gates), followed by
 a second module combining products to give the
desired functions (programmable array of OR gates)
• A PLA having a decoder as first module is a
ROM

RLAC (2008-09) by Luciano Gualà   A - 60
An example

A   B   C   X    Y
0   0   0   1    0                    X=AB+A’B’
0   0   1   1    0
Y=AB+BC+AC
0   1   0   0    0
0   1   1   0    1
1   0   0   0    0
1   0   1   0    1
1   1   0   1    1
1   1   1   1    1

RLAC (2008-09) by Luciano Gualà       A - 61
The PLA implementation

A
Inputs

B                                       AND Gates

C

AB BC     AC A’B’

Outputs
OR Gates                                        X

Y

RLAC (2008-09) by Luciano Gualà           A - 62
Programmable Configurations
• ROM: a fixed array of AND gates and a programmable array of OR
gates
• PLA: a programmable array of AND gates feeding a programmable
array of OR gates

Fixed   Programmable Programmable
Inputs              AND array                OR array        Outputs
(decoder) Connections
ROM

Programmable ProgrammableProgrammable Programmable
Inputs                                                       Outputs
Connections AND array Connections     OR array

PLA
RLAC (2008-09) by Luciano Gualà         A - 63

Carries    1   0          1         1            0   0
Addend-1       1          0         1            1   0 +
Addend-2       1          0         1            1   1 =
Sum        1    0         1          1           0   1

RLAC (2008-09) by Luciano Gualà             A - 64

• Functional Blocks:
functional block,
functional block,
 Ripple Carry Adder, a circuit performing binary
structure to improve performance.

RLAC (2008-09) by Luciano Gualà       A - 65

• It’s just a 2-input, 2-output circuit that performs the
following computations:
X          0          0            1    1
+Y         +0         +1           +0   +1
CS         00         01           01   10

• A half adder adds two bits to produce a two-bit sum
• The sum is expressed as a
sum bit , S and a carry bit, C

RLAC (2008-09) by Luciano Gualà             A - 66

• Sum two binary inputs without the carry-in
Truth table                     Logic Circuit

X    Y   S   C
0    0   0   0
0    1   1   0
1    0   1   0
1    1   0   1

RLAC (2008-09) by Luciano Gualà   A - 67

• A full adder is similar to a half adder, but includes a
carry-in bit from lower stages. Like the half-adder, it
computes a sum bit, S and a carry bit, C.
Z          0      0    0      0
 For a carry-in (Z) of
0, it is the same as               X          0      0    1      1
the half-adder:                   +Y         +0     +1   +0     +1
CS         00     01   01     10

 For a carry- in                    Z         1       1    1      1
(Z) of 1:                          X         0       0    1      1
+Y        +0      +1   +0     +1
CS         01     10   10     11
RLAC (2008-09) by Luciano Gualà             A - 68

• Has to be able to deal                          Truth table
with the carry-in                      X        Y   Z   S     C
0        0   0   0     0
0        0   1   1     0
0        1   0   1     0
0        1   1   0     1

Z represents the carry-in              1        0   0   1     0
1        0   1   0     1
1        1   0   0     1
1        1   1   1     1

RLAC (2008-09) by Luciano Gualà                 A - 69

S = X’Y’Z+X’YZ’+XY’Z’+XYZ                 C = XY + XZ + YZ
=XYZ                                    = XY + XY’Z + X’YZ
= XY + Z.(XY’+X’Y)
= XY + Z.(X  Y)

RLAC (2008-09) by Luciano Gualà            A - 70
The logic circuit of a full adder

RLAC (2008-09) by Luciano Gualà   A - 71

• Has to be able to deal with more bits

RLAC (2008-09) by Luciano Gualà   A - 72
Ideal behaviour of circuits

• Consider an inverter (NOT gate)

RLAC (2008-09) by Luciano Gualà   A - 73
The real behaviour
• Propagation delay: time needed for a change in
the input to affect the output (gate delay)
• Fall time: time taken for the signal to fall from
high level to low level
• Rise time: time taken to rise from low to high

RLAC (2008-09) by Luciano Gualà   A - 74
Carry Propagation

• Signals must propagate from inputs for output
to be valid
• Carry and sum outputs of a single full-adder are
valid c “gate-delays” after inputs are stable
• Value of c depends on the used technology
• In a binary adder of n bits the last carry is valid
cn “gate-delays” after inputs are stable
• For n large it may be unacceptable !

RLAC (2008-09) by Luciano Gualà   A - 75

• each carry is a function of the inputs (A and B)
• Hence, each carry can be computed by a two-
level circuit
• Idea: pre-computing all carries by means of a
(two-level) combinatorial circuit

RLAC (2008-09) by Luciano Gualà   A - 76
Solution

• Write a general expression               ai      bi   ci   si   ci+1

for a carry                              0       0    0    0     0
0       0    1    1     0
 When is a carry generated
0       1    0    1     0
in the output?
0       1    1    0     1
 When does an input carry               1       0    0    1     0
propagates to the output?              1       0    1    0     1
1       1    0    0     1
1       1    1    1     1

RLAC (2008-09) by Luciano Gualà                  A - 77
General expression

• General expression for the (i+1)-th carry
   ci+1 = aibi + ci (ai + bi) = gi +cipi
   gi = aibi  generate carry
   pi = ai+bi  propagate carry
   Iterate the expression for ci

RLAC (2008-09) by Luciano Gualà   A - 78
General expression (2)

ci+1 = gi + pici
= gi + pi(gi-1+ci-1pi-1) = gi+pigi-1+pipi-1ci-1 =
= gi+pigi-1+pipi-1(gi-2+ci-2pi-2)
= gi+pigi-1+pipi-1gi-2+pipi-1pi-2ci-2
= gi+pigi-1+pipi-1gi-2+pipi-1pi-2gi-3+pipi-1pi-2pi-3gi-4+...
• It could be developed until the least significant
input bits
• Every ci depends only on c0, pj, gj (j<i)

RLAC (2008-09) by Luciano Gualà            A - 79
Carry expressions for a 4-bit adder

•   c1=   g0   +   p0c0
•   c2=   g1   +   p1g0 + p1p0c0
•   c3=   g2   +   p2g1 + p2p1g0 + p2p1p0c0
•   c4=   g3   +   p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

RLAC (2008-09) by Luciano Gualà   A - 80
b3 a3                b2 a2                   b1 a1               b0 a0

generation/propagation
p3         g3        p2         g2         p1        g1          p0        g0

b3 a3      c3        b2 a2       c2        b1 a1       c1    b0 a0         c0
c4

FA                   FA                    FA                    FA

s3                   s2                    s1
RLAC (2008-09) by Luciano Gualà
s0        A - 81
A practical problem

•   c1=   g0   +   p0c0
•   c2=   g1   +   p1g0 + p1p0c0
•   c3=   g2   +   p2g1 + p2p1g0 + p2p1p0c0
•   c4=   g3   +   p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

there is a limit due to circuit fan-in:
the maximum number of inputs
RLAC (2008-09) by Luciano Gualà   A - 82
Practical solution for n bits

consecutive bits (4-8 is typical)
• Each of these is a stage
• Use n/m stages connected by means of the
ripple-carry technique
• The overall delay is now (more or less) only
cn/m “gate delays”

RLAC (2008-09) by Luciano Gualà   A - 83
A mixed solution

b[15…12] a[15..12]     b[11…8] a[11..8]    b[7…4] a[7..4]        b[3…0] a[3..0]

c16                c12                 c8                     c4
CLA4                 CLA4                CLA4                 CLA4             c0

s[15..12]            s[11..8]              s[7..4]              s[3..0]

RLAC (2008-09) by Luciano Gualà                         A - 84
Sequential circuits

• More difficult to analyze since there is feedback:
output is fed back to input
• Need to introduce a concept of state
 Current state and next state
• Asynchronous: change of state of an element is
fed into other elements without any coordination
• Synchronous: change of state of each element
is fed into other elements only at a given instant,
the same for all elements

RLAC (2008-09) by Luciano Gualà   A - 85
Introduction to Sequential
Circuits
• A Sequential                         Inputs                           Outputs
circuit contains:                                       Combina-
tional
 Storage elements:                                    Logic
• Latches or Flip-Flops
 Combinational Logic:                                       Next
• Implements a multiple-output
State        State
boolean function
• Inputs are signals from the outside
• Outputs are signals to the outside
• Other inputs, State or Present State, are
signals from storage elements
Storage
• The remaining outputs, Next State are
Elements
inputs to storage elements
RLAC (2008-09) by Luciano Gualà                 A - 86
Initial examples

• What does this circuit do ?

• Replace inverters with NOR gates

RLAC (2008-09) by Luciano Gualà   A - 87
SR-Latch

• Intuition:
 it is a storage element that can store one bit
 Q is the bit stored into the SR-Latch
 two states:
• set: Q=1 (Q’=0)
• reset: Q=0 (Q’=1)
 inputs S and R can be used to write the bit (i.e. to change state)
RLAC (2008-09) by Luciano Gualà            A - 88
Analysis of SR-Latch

• Two kinds of analysis
• COMBINATIONAL
 Consider all possible configurations of S,R,Q and check their
feasibility
 i.e. check which cofigurations are stable
• SEQUENTIAL
 Consider all possible configurations of S,R,Q at a generic step k
and check what happens for Q at step k+1
 i.e. consider all configurations and check if a stable
configuration is reached

RLAC (2008-09) by Luciano Gualà                A - 89
SR-Latch Truth Table:
Combinational View

• 8 possible combinations (Q= NOT Q’)
Q’   Q   S       R
1    0    0      0                stable
1    0    0      1                stable
1    0    1      0              unstable
1    0    1      1              unstable
0    1    0      0                stable
0    1    0      1              unstable
0    1    1      0                stable
0    1    1      1              unstable
RLAC (2008-09) by Luciano Gualà   A - 90
SR-Latch: sequential View

• Next state as a function of current state
S   R   Q(k)   Q(k+1)      Q’(k+1)
0   0    0       0              1                 reset (stable)
0   0    1       1              0                      set (stable)
0   1    0       0              1                 reset (stable)
0   1    1       0              1                reset (transient)
1   0    0       1              0                 Set (transient)
1   0    1       1              0                      Set (stable)
1   1    0       0              0                 unacceptable!
1   1    1       0              0                 unacceptable!
RLAC (2008-09) by Luciano Gualà                  A - 91
Q’

RLAC (2008-09) by Luciano Gualà   A - 92
First reason to avoid S=R=1

• When both inputs go from 1 to 0:
 a race condition happens
• Both outputs are driven from 0 to 1
• Due to unpredictable physical differences one of
the NOR gates may commute earlier from 0 to 1
• Then it will prevent the commutation of the
other gate
• Conclusion: output value is unpredictable !

RLAC (2008-09) by Luciano Gualà   A - 93
Second reason to avoid S=R=1

• When both inputs go from 1 to 0:
 a race condition happens
• Both outputs are driven from 0 to 1
• Both the NOR gates commute from 0 to 1
almost at the same time
 This drives both outputs from 1 to 0
 Both gates are again forced to commute
 This repeats again and again
• Conclusion: output values oscillate !

RLAC (2008-09) by Luciano Gualà   A - 94
Temporal evolution of SR-latch

Time ->

S
R
Q
Q’

RLAC (2008-09) by Luciano Gualà   A - 95
Transition table for SR-Latch

A synthetic description

S      R     Qn+1

0      0       Qn

0      1       0

1      0       1

1      1       ---

RLAC (2008-09) by Luciano Gualà   A - 96

• An additional input (the clock) is used to ensure the
latch commutes only when required             clock cycle

pulses of a clock

• The latch senses S and R only when Clock=1

RLAC (2008-09) by Luciano Gualà   A - 97
The role of the clock

• A clock ensures commutation is propagated
from the input to the output only when required
• But the general system clock is running
continuously: how can it be used to control a
circuit only when needed?
Enable              Clock for the specific circuit
System Clock

RLAC (2008-09) by Luciano Gualà                 A - 98
Circuit clock from system clock

Enable                      Clock for the specific circuit
System Clock

System Clock

Circuit Enable

Circuit Clock

RLAC (2008-09) by Luciano Gualà                   A - 99
A more subtle problem:
the latch timing problem
while clock=1,
outputs of the latch change whenever the inputs
change
during the same clock cycle

Q’

RLAC (2008-09) by Luciano Gualà      A -100
…as a consequence…
• In a commutation from (S=1,R=0) to (S=0,R=1) or from (S=0,R=1)
to (S=1,R=0) the SR-latch outputs may be (for some time) in the
unacceptable state where both outputs are 0

Initial    Input   Transient   Stable
state     change     state      state

S     1         0         0           0
R     0         1         1           1
Q     1         1         0           0
Q’     0         0         0           1

• If Q and Q’ are in input to a further circuit, this receives wrong input
values, hence its computed output may differ from the required one

RLAC (2008-09) by Luciano Gualà            A -101
…one more consequence…

• Consider the following circuit and suppose that initially Q = 0

S

R

• As long as C = 1, the value of Q continues to change!

Clock                                                    Desired behavior:
Q changes only once
Q
per clock pulse
RLAC (2008-09) by Luciano Gualà                 A -102
The solution: master-slave Flip-Flop
circuit
• it consists of two SR Latches (master and slave)
 the master (connected to circuit’s inputs only) can change its state
(flip) when clock=1
 The slave (connected to circuit’s outputs only) can changes its state
(flop) when clock=0
• Hence:
 the slave reads master’s outputs after they have stabilized
 the next circuit reads slave’s outputs in the next clock commutation
to 1, when they have stabilized
• In a chain of circuits this allows to control exactly when the
(commuted) output of the i-th circuit acts on the input of the
(i+1)-th circuit
RLAC (2008-09) by Luciano Gualà            A -103
The solution: master-slave Flip-Flop
circuit

RLAC (2008-09) by Luciano Gualà   A -104
SR flip-flop: execution example

0
1                              0
1           0
1
0
1                              0
1
0                              1
0           1
0

RLAC (2008-09) by Luciano Gualà       A -105
D flip-flop: a secure SR flip-flop
• Forcing R to always be NOT(S) the critical
condition S=R=1 is avoided
SR flip-flop

D                S                     Q

C

R                         Q

RLAC (2008-09) by Luciano Gualà       A -106
Use of D flip-flop
• A D flip-flop is a memory cell, since it stores
what is presented at its input
Symbol                      Truth table
D       Qn+1
0        0
1        1

RLAC (2008-09) by Luciano Gualà          A -107
JK flip-flop: using also S=R=1

RLAC (2008-09) by Luciano Gualà   A -108
Tabular description for JK-FF

• Input: J, K; State: Q; Output: Q
J   K    Qn    Qn+1
0    0    0      0
0    1    0      0
1    0    0      1
1    1    0      1
0    0    1      1
0    1    1      0
1    0    1      1
1    1    1      0

RLAC (2008-09) by Luciano Gualà   A -109
Transition Tables

• Synthetic description of flip-flop dynamics

S   R   Qn+1           D    Qn+1                  J   K   Qn+1
0   0   Qn             0      0                   0   0   Qn
0   1    0             1      1                   0   1    0
1   0    1                                        1   0    1
1   1   ---                                       1   1   Q’n

RLAC (2008-09) by Luciano Gualà                  A - 110
Use of D-FF:
WE: Write-Enable
4 bit register                                    Pr: Preset - signals to prepare the gate
writes all 1s

X0                 X1                   X2                    X3

WE

WE.Pr
D                      D                  D                   D
Q                  Q
Q                      Q
Ck                     Ck                 Ck                  Ck

WE.Ck

RE

Y0                  Y1                     Y2                 Y3

RLAC (2008-09) by Luciano Gualà                      A - 111
Use of D flip-flop (2)

• A D flip-flop is a delay unit, since it replicates at
the output - one propagation delay later - what
is presented at its input (delay flip-flop)
• A chain of n D flip-flops can be used to delay a
bit value for n clock pulses

RLAC (2008-09) by Luciano Gualà   A - 112
SE: Shift-Enable
4 bit delay unit

SE
Din        D                    D                   D                    D
Q                    Q                     Q                  Q        Dout

Ck                   Ck                  Ck                   Ck

SE.Ck

RE

Y0                 Y1                      Y2                 Y3

RLAC (2008-09) by Luciano Gualà                          A - 113
4 bit shift register
X0                 X1                   X2                    X3

WE

SE
D                      D                  D                   D
Din                                                              Q                  Q        Dout
Q                      Q
Ck                     Ck                 Ck                  Ck

(SE.Ck)+
(WE.Ck)
RE

Y0                  Y1                     Y2                 Y3

RLAC (2008-09) by Luciano Gualà                      A - 114
Register Control Signals

• WE (Write Enable): needed since many registers
are attached to (i.e., receive data from) the
same data bus
• SE (Shift Enable): allows a register output to
drive next register input
• RE (Read Enable): needed since many registers
are attached to (i.e., put data on) the same
data bus

RLAC (2008-09) by Luciano Gualà   A - 115
Counters                                I
D0

• It counts the number of                              D1

clock cycles in which I=1                 I.D0

• IDEA: A single JK-FF with a
periodic input commutes its                          D2

output with twice the                 I.D0.D1
period of its input
• Use a chain of JK-FF each                            D3

time doubling the period of         I.D0.D1.D2
the input
• A counter modulo 24 is                               COUT
Ck
shown
RLAC (2008-09) by Luciano Gualà   A - 116
Temporal behaviour (1)

0   1   2   3   4   5      6     7    8     9    1        1   1   1   1   1        1
I=Ck                                                    0        1   2   3   4   5        6

D0

RLAC (2008-09) by Luciano Gualà                       A - 117
Temporal behaviour (2)

0   1   2   3   4   5      6     7    8     9    1        1   1   1   1   1        1
I=Ck                                                    0        1   2   3   4   5        6

D0

D1

RLAC (2008-09) by Luciano Gualà                       A - 118
Temporal behaviour (3)

0   1   2   3   4   5      6     7    8     9    1        1   1   1   1   1        1
I=Ck                                                    0        1   2   3   4   5        6

D0

D1

D2

RLAC (2008-09) by Luciano Gualà                       A - 119
Temporal behaviour (4)

0   1   2   3   4   5      6     7    8     9    1        1   1   1   1   1       1
I=Ck                                                    0        1   2   3   4   5       6

D0

D1

D2

D3

RLAC (2008-09) by Luciano Gualà                       A -120
Temporal behaviour (5)

0       1       2       3       4       5       6       7       8       9       1       1       1       1       1       1        1
I=Ck                                                                                    0       1       2       3       4       5        6

D0         1       0       1       0       1       0       1       0       1       0       1       0       1       0       1        0       1

D1         0       1       1       0       0       1       1       0       0       1       1       0       0       1       1        0       0

D2
0       0       0       1       1       1       1       0       0       0       0       1       1       1       1        0       0

D3         0       0       0       0       0       0       0       1       1       1       1       1       1       1       1        0       0

COUT

RLAC (2008-09) by Luciano Gualà                                                 A -121
Finite State Machines (FSM)
• Called also Finite State Automata (FSA)
• Formal model useful to describe a sequential circuit
• Described by a table of transitions between states as a
consequence of inputs
• If an input is true in a given state, a transition changes the
state and may produce an output
• Two formal models exist:
 Moore Model: outputs are a function only of states
 Mealy Model: outputs are a function of inputs and states

RLAC (2008-09) by Luciano Gualà          A -122
Graphical representation

• States are circles, transition are arrows, input
are arrow labels, output are arrow (Mealy) or
state (Moore) labels:
Input / Output
Current                        Next            Mealy model
state                         state

Input
Current                          Next
Moore model       state/Output                    state/output

RLAC (2008-09) by Luciano Gualà                  A -123
A very simple example of FSM

• A FSM with a binary input x, and a binary output z.
The output z=1 iff the number of 1s in the input
sequence is even

1/0

0/1               even                                odd   0/0

1/1
initial state
RLAC (2008-09) by Luciano Gualà          A -124
Tabular description for this FSM

• Next state as   Current state          Input      Next state
even                0         even
a function of
even                1          odd
current state
odd                 0          odd
and input             odd                 1         even

• Output as a     Current state          Input       Output

function of           even                0           1
even                1           0
current state
odd                 0           0
and input
odd                 1           1

RLAC (2008-09) by Luciano Gualà             A -125
Abstraction process

• FSM describe sequential networks (SN)
• SN realizes Finite State Machines

• The analysis of a SN allows to write the corresponding FSM
• From a FSM a SN is obtain through a synthesis process

• Similar to boolean functions and logical circuits
 Boolean Functions (BF) describe logical circuits (LC)
 LC realize Boolean Functions

 The analisys of a LC produces a BF
 LC are combinational networks (memoryless) synthesizing BF
RLAC (2008-09) by Luciano Gualà           A -126
FSA for D flip-flop

•   Use Q as state descriptor (state variable)
•   Use D as input
•   Use Q as output
•   Check for completeness
1/0
0/0   0                              1      1/1
0/1

RLAC (2008-09) by Luciano Gualà         A -127
Its tabular description

• Output values as a function of input and current
state values
• Next state values as a function of input and
state value
 D flip-flop
D    Qn     Qn                     D   Qn   Qn+1
0     0     0                      0   0     0
0     1     1                      0   1     0
Output:    1     0     0             State:   1   0     1
1     1     1                      1   1     1

RLAC (2008-09) by Luciano Gualà                A -128
FSA for SR flip-flop

•   Use Q as state variable
•   Use S and R as input
•   Use Q as output
•   Transitions with multiple conditions
10/0
00,01/0      0                                1      00,10/1
01/1

• Unacceptable input configurations are NOT
represented

RLAC (2008-09) by Luciano Gualà             A -129
FSA for JK flip-flop

• Just add condition 11 to existing transitions
• Note stability and instability of states according
to input values

10,11/0
00,01/0     0                                     1   00,10/1
01,11/1

RLAC (2008-09) by Luciano Gualà                 A -130
Synthesis of a SN from a FSA

• Identify input, output and state variables
 how many FFs are needed?
 for n states we need k FFs with 2k  n
 label each state with a k-length bit string
• Build (and minimize) truth tables for output variables as
a function of input and state values
• Build (and minimize) transition tables for state variables
as a function of input and state values
• Decide which FF to use to store state values
 a D-FF is the simplest choice
 to store 0 present 0 at the input
 to store 1 present 1 at the input

RLAC (2008-09) by Luciano Gualà   A -131
Generic architecture of a SN

RLAC (2008-09) by Luciano Gualà   A -132
Example
1/0

0/1         even
0                                odd
1     0/0

1/1

Q X Q’ Z
X                         Z
0   0   0   1
0   1   1   0
1   0   1   0
1   1   0   1

Q’= X  Q
Z= X  Q
RLAC (2008-09) by Luciano Gualà         A -133
Example 1: a given FSA

1/1
10
0/1

0/0                                 0/1
00               11
0/0

1/0
1/0

01
1/1

RLAC (2008-09) by Luciano Gualà          A -134
Example 1: variables

X          Combinational              Y
circuit
An                       An+1
Bn                       Bn+1

Bn           Bn+1
An           An+1
Storage
elements

RLAC (2008-09) by Luciano Gualà       A -135
Example 1: transition tables

• Transition table for output and state variables
An   Bn   X     Y    An+1 Bn+1
0    0    0     0      1      1
0    0    1     0      0      0
0    1    0     0      1      1
0    1    1     1      0      0
1    0    0     1      0      1
1    0    1     1      0      0
1    1    0     1      1      0
1    1    1     0      0      1

RLAC (2008-09) by Luciano Gualà   A -136
Example 1: minimization
State variables                               Output
An+1        X               Bn+1        X                Y         X
0   1                       0   1                      0   1
AB     11   1   0           AB     11   0   1            AB   00   0   0
01   1   0                  01   1   0                 01   0   1
00   1   0                  00   1   0                 11   1   0
10   0   0                  10   1   0                 10   1   1

RLAC (2008-09) by Luciano Gualà                     A -137
Example 1: circuits
B                                 A’

X’                                X’

B’
D            A          X’                D     B
A’                                A                 Ck
Ck
B
X’                                X

A’
B
X

A
B’                            Y
A

X’

RLAC (2008-09) by Luciano Gualà            A -138
Example 2: specification

• Two input values are presented together
• Recognize with output 10 and 01, respectively, when a
couple 00 or a couple 11 is presented
• Recognize with output 11 when two consecutive couples
of identical values (00 00 or 11 11) are presented
• Output is 00, otherwise
• Example:

INPUT    01   01    00   00    00   11    11    10   11   11   11   11
OUTPUT   00   00    10   11    10   01    11    00   01   11   01   11

RLAC (2008-09) by Luciano Gualà                       A -139
Example 2: corresponding FSA

• Show also the initial state (double circle)
01,10/00
11/11        00
11/01
01,10/00
00/11
00/10
01,10/00

00/10
01                                       10
11/01

RLAC (2008-09) by Luciano Gualà                      A -140
Example 2: variables

X                                     W
Y           Combinational             Z
circuit
An                     An+1
Bn                     Bn+1

Bn         Bn+1
An         An+1
Storage
elements

RLAC (2008-09) by Luciano Gualà       A -141
Example 2: transition tables
An   Bn   X    Y     W      Z    An+1 Bn+1
0    0    0     0     1     0      1      0
0    0    0     1     0     0      0      0
0    0    1     0     0     0      0      0
0    0    1     1     0     1      0      1
Note: here
0    1    0     0     1     0      1      0
0    1    0     1     0     0      0      0
unspecified
0    1    1     0     0     0      0      0     inputs can be
0    1    1     1     1     1      0      0        used for
1    0    0     0     1     1      0      0
1    0    0     1     0     0      0      0
minimization
1    0    1     0     0     0      0      0
1    0    1     1     0     1      0      1
1    1    0     0    --     --    --      --
1    1    0     1    --     --    --      --
1    1    1     0    --     --    --      --
1    1    1     1    --    --      --     --
RLAC (2008-09) by Luciano Gualà         A -142
Example 2: circuits
A’
X’           D       A
Y’

Ck
B
X                                           W
Y

A
X’                                          Z
Y’

B’
X            D       B
Y

Ck

RLAC (2008-09) by Luciano Gualà       A -143
What happens when the FSA is not
complete?

1/1
10
0/1

0/0                                 0/1
00               11
0/0

1/0

01
1/1

RLAC (2008-09) by Luciano Gualà          A -144
…uncomplete FSA…

• Transition table for output and state variables
An   Bn   X     Y    An+1 Bn+1
0    0    0     0      1      1
Note: here
unspecified
0    0    1     -      -      -
inputs cannot
0    1    0     0      1      1
be used for
0    1    1     1      0      0
minimization
1    0    0     1      0      1
1    0    1     1      0      0
1    1    0     1      1      0
1    1    1     0      0      1

RLAC (2008-09) by Luciano Gualà         A -145
State variables                               Output
An+1        X               Bn+1        X                Y         X
0   1                       0   1                      0   1
AB     11   1   0           AB     11   0   1            AB   00   0   --
01   1   0                  01   1   0                 01   0   1
00   1   --                 00   1   --                11   1   0
10   0   0                  10   1   0                 10   1   1

• NOTE: we are setting all unspecified values to 0

RLAC (2008-09) by Luciano Gualà                      A -146
• …hence:
An   Bn   X     Y    An+1 Bn+1
0    0    0     0      1      1
0    0    1     0      0      0
0    1    0     0      1      1
0    1    1     1      0      0
1    0    0     1      0      1
1    0    1     1      0      0
1    1    0     1      1      0
1    1    1     0      0      1

RLAC (2008-09) by Luciano Gualà   A -147
…the corresponding FSA…

1/1

10
0/1
1/0
0/0                                   0/1
00                  11
0/0

1/0

01
1/1
RLAC (2008-09) by Luciano Gualà                    A -148
…a different choice…

State variables                                    Output

An+1        X                 Bn+1        X                Y         X
0   1                         0   1                      0   1
AB     11   1   0             AB     11   0   1            AB   00   0   --
01   1   0                    01   1   0                 01   0   1
00   1   --                   00   1   --                11   1   0
10   0   0                    10   1   0                 10   1   1

… hence we would implement …

RLAC (2008-09) by Luciano Gualà                      A -149
• …hence:
An   Bn   X     Y    An+1 Bn+1
0    0    0     0      1      1
0    0    1     1      1      0
0    1    0     0      1      1
0    1    1     1      0      0
1    0    0     1      0      1
1    0    1     1      0      0
1    1    0     1      1      0
1    1    1     0      0      1

RLAC (2008-09) by Luciano Gualà   A -150
…the corresponding FSA…

1/1

10
1/1
0/1

0/0                                 0/1
00                 11
0/0

1/0

01
1/1

RLAC (2008-09) by Luciano Gualà          A -151

```
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