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2020 Design Change Information in Template - Excel

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2020 Design Change Information in Template - Excel Powered By Docstoc
					   ORTC
                       2008 Overall Roadmap Technology Characteristics
   INDEX


                       Link to file for System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process
 2007 ITRS
 Chapters              Structures (PIDS)

                       Link to file for Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Proc
                       Lithography, Interconnect, Factory Integration, and Assembly & Packaging

                       Link to file for Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulat

                       Link to the 2008 Update Overview

                       Link to the 2007 ITRS chapters

                       TO ACCESS THE ITWG TABLES LISTED BELOW, USE THE LINKS ABOVE

                       System Drivers
TEXT                   Table SYSD1
             UPDATED Table SYSD2
                       Table SYSD3
                       Table SYSD4

                       Design
TEXT                 Table DESN1
TEXT         ADDED   Table DESN X
             UPDATED Table DESN2
TEXT         UPDATED Table DESN3
                     Table DESN4
TEXT                 Table DESN5
                     Table DESN6
TEXT                 Table DESN7
                     Table DESN8
                     Table DESN9
TEXT                 Table DESN10
TEXT                 Table DESN11
TEXT                 Table DESN12

                       Test and Test Equipment
TEXT                   Table TST1
             UPDATED   Table TST2
                       Table TST3
                       Table TST4
                       Table TST5
             UPDATED   Table TST6
             UPDATED   Table TST7
             UPDATED   Table TST8
                 Table TST9
TEXT             Table TST10
                 Table TST11
                 Table TST12
TEXT             Table TST13
                 Table TST14
                 Table TST15

                 RF and AMS for Wireless
       UPDATED Table RFAMS1
       UPDATED Table RFAMS2
       UPDATED Table RFAMS3
       UPDATED Table RFAMS4
       UPDATED Table RFAMS5
                 Table RFAMS6
                 Table RFAMS7
                 Table RFAMS8

                 Process Integration, Devices, and Structures (PIDS)
TEXT             Table PIDS1
       UPDATED   Table PIDS2
       UPDATED   Table PIDS3a and b
       UPDATED   Table PIDS3c and d
                 Table PIDS4
       UPDATED   Table PIDS5
TEXT             Table PIDS6
                 Table PIDS7


                 Emerging Research Devices
                 Please refer to the ERD summary in the 2008 Update Overview

                 Emerging Research Materials
                 Please refer to the ERM summary in the 2008 Update Overview

                 Front End Processes
TEXT             Table FEP1
       UPDATED   Table FEP2
       UPDATED   Table FEP3
       UPDATED   Table FEP4a
       UPDATED   Table FEP4b
       UPDATED   Table FEP5
       DELETED   Table FEP6
       UPDATED   Table FEP7
       UPDATED   Table FEP8
                 Table FEP9

                 Lithography
TEXT             Table LITH1
TEXT             Table LITH2
       UPDATED Table LITH3
       UPDATED Table LITH4AB
               Table LITH4C
       UPDATED Table LITH5AB
       UPDATED Table LITH5CD
       UPDATED Table LITH5EF
               Table LITH6

                 Interconnect
TEXT             Table INTC1
       UPDATED Table INTC2
       UPDATED Table INTC3
               Table INTC4
TEXT           Table INTC5
       UPDATED Table INTC6
               Table INTC7

                 Factory Integration
TEXT           Table FAC1
TEXT           Table FAC2
               Table FAC3
       UPDATED Table FAC4
               Table FAC5
       UPDATED Table FAC6
               Table FAC7
TEXT           Table FAC8
TEXT           Table FAC9

                 Assembly and Packaging
TEXT             Table AP1
                 Table AP2
       UPDATED   Table AP3
       UPDATED   Table AP4
       ADD       Table AP4B
       UPDATED   Table AP5A
       UPDATED   Table AP5B
       UPDATED   Table AP5C
                 Table AP6
                 Table AP7
TEXT             Table AP8
       UPDATED   Table AP9
TEXT   UPDATED   Table AP10
       UPDATED   Table AP11
                 Table AP12a and b
TEXT             Table AP12c
TEXT             Table AP13
TEXT             Table AP14
TEXT   UPDATED   Table AP15
TEXT   UPDATED   Table AP16
TEXT             Table AP17
TEXT             Table AP18
TEXT   UPDATED   Table AP19
                 Table AP20
       UPDATED   Table AP21

                 CROSSCUT WORKING GROUP TABLES
                 Environment, Safety, and Health
TEXT             Table ESH1
       UPDATED Table ESH2a
       UPDATED Table ESH2b
               Table ESH3
               Table ESH4a
               Table ESH4b
       UPDATED Table ESH5
               Table ESH6

                 Yield Enhancement
TEXT             Table YE1
TEXT             Table YE2
       UPDATED   Table YE3
       UPDATED   Table YE4
       UPDATED   Table YE5
       UPDATED   Table YE6

       UPDATED Table YE7

       UPDATED Table YE8
       UPDATED Table YE9


                 Metrology
TEXT             Table MET1
                 Table MET2
                 Table MET3
               Table MET4a and b
               Table MET4c and d
       UPDATED Table MET5a
               Table MET5b
               Table MET6

                Modeling and Simulation
TEXT   UPDATED Table MS1
       UPDATED Table MS2a
       UPDATED Table MS2b
       UPDATED Table MS3
Roadmap Technology Characteristics

 System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process Integration, Devices, &
IDS)

Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Processes (FEP),
nterconnect, Factory Integration, and Assembly & Packaging

Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulation

08 Update Overview

07 ITRS chapters

THE ITWG TABLES LISTED BELOW, USE THE LINKS ABOVE


              Major Product Market Segments and Impact on System Drivers
              SOC Consumer Driver Design Productivity Trends
              Projected Mixed-Signal Figures of Merit for Four Circuit Types
              Embedded Memory Requirements


              Overall Design Technology Challenges
              Description of Improvement
              System-Level Design Requirements
              Correspondence Between System-Level Design Requirements and Solutions
              Logical/Circuit/Physical Design Technology Requirements
              Correspondence Between Logical/Circuit/Physical Requirements and Solutions
              Design Verification Requirements
              Correspondence Between Design Verification Requirements and Solutions
              Design for Test Technology Requirements
              Design for Manufacturability Technology Requirements
              Correspondence Between Design for Manufacturability Requirements and Solutions
              Near-term Breakthroughs in Design Technology for AMS
              Design Technology Improvements and Impact on Designer Productivity

t Equipment
              Summary of Key Test Drivers, Challenges, and Opportunities
              Multi-site Test for Product Segments
              System on Chip Test Requirements
              Logic Test Requirements
              Vector Multipliers
              Memory Test Requirements
              Mixed-signal Test Requirements
              RF Test Requirements
            Burn-in Requirements
            Test Handler and Prober Difficult Challenges
            Prober Requirements
            Handler Requirements
            Probing Difficult Challenges
            Wafer Probe Technology Requirements
            Test Socket Technology Requirements

S for Wireless
              RF and Analog Mixed-Signal CMOS Technology Requirements
              RF and Analog Mixed-Signal Bipolar Technology Requirements
              On-Chip Passives Technology Requirements
              Embedded Passives Technology Requirements
              Power Amplifier Technology Requirements
              Base Station Devices Technology Requirements
              Millimeter Wave 10 GHz–100 GHz Technology Requirements
              RF and Analog Mixed-Signal RFMEMS

gration, Devices, and Structures (PIDS)
             Process Integration Difficult Challenges
             High-performance Logic Technology Requirements
             Low Standby Power Technology Requirements
             Low Operating Power Technology Requirements
             DRAM Technology Requirements
             Non-volatile Memory Technology Requirements
             Reliability Difficult Challenges
             Reliability Technology Requirements

esearch Devices
 o the ERD summary in the 2008 Update Overview

esearch Materials
 o the ERM summary in the 2008 Update Overview


            Front End Processes Difficult Challenges
            Starting Materials Technology Requirements—Near and Long-term Years
            Front End Surface Preparation Technology Requirements—Near and Long-term Years
            Thermal, Thin Film, Doping and Etching Technology Requirements—Near-term Years
            Thermal, Thin Film, Doping and Etching Technology Requirements—Long-term Years
            DRAM Stacked Capacitor Technology Requirements—Near and Long-term Years
            DRAM Trench Capacitor Technology Requirements—Near and Long-term Years
            FLASH Non-volatile Memory Technology Requirements
            Phase Change Memory (PCM) Technology Requirements—Near and Long-term Years
              FeRAM Technology Requirements—Near and Long-term Years



              Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection Lithography
              Lithography Difficult Challenges
              Lithography Technology Requirements—Near and Long-term Years
              Resist Requirements—Near and Long-term Years
              Resist Sensitivities
              Optical Mask Requirements—Near and Long-term Years
              EUVL Mask Requirements—Near and Long-term Years
              Imprint Template Requirements—Near and Long-term Years
              Maskless Technology Requirements—Near and Long-term Years


              Interconnect Difficult Challenges
               MPU Interconnect Technology Requirements—Near and Long-term Years
              DRAM Interconnect Technology Requirements—Near and Long-term Years
              Interconnect Surface Preparation Technology Requirements—Near and Long-term Years
              Options for Interconnects Beyond the Metal/Dielectric System
              High Density Through Silicon via Draft Specification
              M inimum Density of Metallic SWCNTs Needed to Exceed Minimum Cu Wire Conductivity


               Factory Integration Difficult Challenges—Near and Long-term Years
               Key Focus Areas and Issues for FI Functional Areas Beyond 2007
               Factory Operations Technology Requirements—Near and Long-term Years
               Production Equipment Technology Requirements—Near and Long-term Years
               Material Handling Systems Technology Requirements—Near and Long-term Years
               Factory Information and Control Systems Technology Requirements—Near and Long-term Years
               Facilities Technology Requirements—Near and Long-term Years
               Crosscut Issues Relating to Factory Integration
               List of Next Wafer Size Challenges

d Packaging
              Assembly and Packaging Difficult Challenges
                Single-chip Packages Technology Requirements—Near and Long-term Years
              Chip-to-package Substrate Technology Requirements—Near and Long-term Years
              Substrate to Board Pitch—Near and Long-term Years
              Warpage at Peak Temperature
              Package Substrates—Near and Long-term Years
              Polymer Package Substrate Design Parameters—Near and Long-term Years
              Cost Performance Glass-ceramic Substrates (high end FCBGA)
              Wafer Level Packaging—Near and Long-term Years
           Key Technical Parameters for Stacked Architectures Using TSV
           Comparison of SoC and SiP Architecture
           Package Level System Integration
           Processes for SiP
           System in Package Requirements—Near and Long-term Years
           Thinned Silicon Wafer Thickness 200 mm/300 mm—Near and Long-term Years
           Challenges and Potential Solutions in Thinning Si Wafers
           SiP Failure Modes
           Some Common Optoelectronic Packages and Their Applications
           Optical Communications and Interconnect
           Optoelectronic Packaging Challenges and Potential Solutions
           MEMS Packaging Methods
           MEMS Packaging Examples
           Materials Challenges
           Package Substrate Physical Properties
            Automotive Operating Environment Specifications

WORKING GROUP TABLES
, Safety, and Health
             ESH Difficult Challenges
             ESH Intrinsic Requirements—Near-term Years
             ESH Intrinsic Requirements—Long-term Years
             Chemicals and Materials Management Technology Requirements
             Process and Equipment Management Technology Requirements—Near-term Years
             Process and Equipment Management Technology Requirements—Long-term Years
             Facilities Energy and Water Optimization Technology Requirements
             Sustainability and Product Stewardship Technology Requirements


           Definitions for the Different Interface Points
           Yield Enhancement Difficult Challenges
           Defect Budget Technology Requirement Assumptions
           Yield Model and Defect Budget MPU Technology Requirements
           Yield Model and Defect Budget DRAM/Flash Technology Requirements
           Defect Inspection on Patterned Wafer Technology Requirements
           Defect Inspection on Unpatterned Wafers: Macro, and Bevel Inspection Technology Requirements
           Defect Review and Automated Defect Classification Technology Requirements
           Technology Requirements for Wafer Environmental Contamination Control


           Metrology Difficult Challenges
           Metrology Technology Requirements
           Lithography Metrology (Wafer) Technology Requirements
            Lithography Metrology (Mask) Technology Requirements: Optical
            Lithography Metrology (Mask) Technology Requirements: EUV
            Front End Processes Metrology Technology Requirements—Near-term Years
            Front End Processes Metrology Technology Requirements—Long-term Years
            Interconnect Metrology Technology Requirements—Near and Long-term Years

d Simulation
            Modeling and Simulation Difficult Challenges
            Modeling and Simulation Technology Requirements: Capabilities—Near-term Years
            Modeling and Simulation Technology Requirements: Capabilities—Long-term Years
            Modeling and Simulation Technology Requirements: Accuracy—Near-term Years
http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_A.xls


http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_B.xls

http://www.itrs.net/Links/2008ITRS/Update/2008Tables_CROSSCUT.xls

http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf
http://www.itrs.net/Links/2007ITRS/Home2007.htm
n Lithography
   2008
  INDEX


 2007 ITRS
 Chapters


             Overall Roadmap Technology Characteristics [ORTC]

UPDATED      Trends Graphic
UPDATED      Table 1a&b
UPDATED      Table 1c&d
UPDATED      Table 1e&f
UPDATED      Table 1g&h
UPDATED      Table 1i&j
UPDATED      Table 2a&b
UPDATED      Table 3a&b
UPDATED      Table 4a&b
UPDATED      Table 4c&d
UPDATED      Table 5a&b
UPDATED      Table 6a&b
UPDATED      Table 7a&b
Roadmap Technology Characteristics [ORTC]


           Product Generations and Chip Size Model Technology Trend Targets
           DRAM and Flash Production Product Generations and Chip Size Model
           DRAM Introduction Product Generations and Chip Size Model
           MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model
           High-Performance MPU and ASIC Product Generations and Chip Size Model
           Lithographic-Field and Wafer Size Trends
           Performance of Packaged Chips: Number of Pads and Pins
           Performance and Package Chips: Pads, Cost
           Performance and Package Chips: Frequency On-chip Wiring Levels
           Electrical Defects [**]
           Power Supply and Power Dissipation
           Cost
2008 Update Trend Graphic, including ITRS 7/15 meetings Final Litho Printed Ga
ngs Final Litho Printed Gate Length Proposal
Table 1a&bProduct Generations and Chip Size Model Technology Trend Targets

Year of Production                                     2007   2008      2009   2010   2011   2012   2013   2014
Flash ½ Pitch (nm) (un-contacted Poly)(f)              54     45        40     36     32     28     25     23
DRAM ½ Pitch (nm) (contacted)                          65     57        50     45     40     36     32     28
DRAM ½ Pitch (nm) (contacted)                          68     59        52      45     40     36     32     28
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                      68     59        52     45     40     36     32     28
MPU Printed Gate Length (nm)                            42     38        34     30     27     24     21     19
MPU Printed Gate Length (GLpr) (nm) ††                  54     47        41     35     31     28     25     22
MPU Physical Gate Length (GLph) (nm)                    25     23        20     18     16     14     13     11
MPU Physical Gate Length (GLph) (nm)                    32     29        27     24     22     20     18     17
ASIC/Low Operating Power Printed Gate Length (nm) ††    54     48        42     38     34     30     27     24
ASIC/Low Operating Power Printed Gate Length (nm) ††    64     54        47     41     35     31     25     22
ASIC/Low Operating Power Physical Gate Length (nm)      32     28        25     23     20     18     16     14
ASIC/Low Operating Power Physical Gate Length (nm)      38     32        29     27     24     22     18     17
2015
20
25
 25
 25
 17
 20
 10
 15
 21
 20
 13
 15
2016   2017   2018   2019   2020   2021   2022
17.9   15.9   14.2   12.6   11.3   10.0   8.9
 23     20     18     16     14     13    11
22.5   20.0   17.9   15.9   14.2   12.6   11.3
22.5   20.0   17.9   15.9   14.2   12.6   11.3
 15     13     12     11    9.5    8.4    7.5
17.7   15.7   14.0   12.5   11.1   9.9    8.8
8.9    8.0    7.1    6.3    5.6    5.0    4.5
14.0   12.8   11.7   10.7   9.7    8.9    8.1
 19     17     15     13     12     11    9.5
17.7   15.7   14.0   12.5   11.1   9.9    8.8
 11     10    8.9    8.0    7.1    6.3    5.6
14.0   12.8   11.7   10.7   9.7    8.9    8.1
Table 1c&d DRAM and Flash Production Product Generations and Chip Size Model

Year of Production                                  2007       2008       2009       2010       2011       2012       2013       2014       2015
DRAM ½ Pitch (nm) (contacted)                        68         59         52         45         40         36         32         28         25
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                   68         59         52         45         40         36         32         28         25
MPU Physical Gate Length (nm)                        32         29         27         24         22         20         18         17         15
DRAM Product Table
Cell area factor [a]                                  6          6          6          6          6          6          6          6          6
                             2
Cell area [Ca = af2] (um )                          0.028      0.021      0.016      0.012      0.0096     0.0077     0.0061     0.0048     0.0038
Cell array area at production (% of chip size) §   56.08%     56.08%     56.08%     56.08%     56.08%     56.08%     56.08%     56.08%     56.08%
Generation at production §                            2G         2G         2G         4G         4G         4G         8G         8G         8G
Functions per chip (Gbits)                           2.15       2.15       2.15       4.29       4.29       4.29       8.59       8.59       8.59
                                 2
Chip size at production (mm )§                       107        81         61         93         74         59         93         74         59
Gbits/cm2 at production §                            2.01       2.65       3.50       4.62       5.82       7.33       9.23      11.63      14.65
Flash Product Table
Flash ½ Pitch (nm) (un-contacted Poly)(f)            53.5       45.0       40.1       35.7       31.8       28.3       25.3       22.5       20.0
Cell area factor [a]                                  4          4          4          4          4          4          4          4          4
                      2      2
Cell area [Ca = af ] (um )                          0.0115     0.0081     0.0064     0.0051     0.0041     0.0032     0.0026     0.0020     0.0016
Cell array area at production (% of chip size) §   68.35%     68.35%     68.35%     68.35%     68.35%     68.35%     68.35%     68.35%     68.35%
Generation at production § SLC                       8G         8G         8G         16G        16G        16G        32G        32G        32G
Generation at production § MLC [2 bits/cell]         16G        16G        16G        32G        32G        32G        64G        64G        64G
Generation at production § MLC [4 bits/cell]         32G        32G        32G        64G        64G        64G       128G       128G       128G
Functions per chip (Gbits) SLC                       8.59       8.59       8.59      17.18      17.18      17.18      34.36      34.36      34.36
Functions per chip (Gbits) MLC [2 bits/cell]        17.18      17.18      17.18      34.36      34.36      34.36      68.72      68.72      68.72
Functions per chip (Gbits) MLC [4 bits/cell]        34.36      34.36      34.36      68.72      68.72      68.72      137.44     137.44     137.44
                                 2
Chip size at production (mm )§ SLC                  143.96     101.80     80.80      128.26     101.80     80.80      128.26     101.80     80.80
Chip size at production (mm2)§ MLC
[2 bits/cell & 4 bits/cell]                         143.96     101.80     80.80      128.26     101.80     80.80      128.26     101.80     80.80
           2
Bits /cm       at production § SLC                 5.97E+09   8.44E+09   1.06E+10   1.34E+10   1.69E+10   2.13E+10   2.68E+10   3.38E+10   4.25E+10
Bits/cm2 at production § MLC [2 bits/cell]         1.19E+10   1.69E+10   2.13E+10   2.68E+10   3.38E+10   4.25E+10   5.36E+10   6.75E+10   8.51E+10
 2016       2017       2018       2019       2020       2021       2022
  22.5       20.0       17.9       15.9       14.2       12.6       11.3
  22.5       20.0       17.9       15.9       14.2       12.6       11.3
  14.0       12.8       11.7       10.7       9.7        8.9        8.1


   6          6          6          6          6          6          6
 0.0030     0.0024     0.0019     0.0015     0.0012    0.00096    0.00076
56.08%     56.08%     56.08%     56.08%     56.08%     56.08%     56.08%
  16G        16G        16G        32G        32G        32G        64G
 17.18      17.18      17.18      34.36      34.36      34.36      68.72
  93         74         59         93         74         59         93
 18.46      23.26      29.31      36.93      46.52      58.61      73.85


  17.9       15.9       14.2       12.6       11.3       10.0       8.9
   4          4          4          4          4          4          4
 0.0013     0.0010    0.00080    0.00064    0.00051    0.00040    0.00032
68.35%     68.35%     68.35%     68.35%     68.35%     68.35%     68.35%
  64G        64G        64G       128G       128G       128G       256G
 128G       128G       128G       256G       256G       256G       512G
 256G       256G       256G       512G       512G       512G       1024G
 68.72      68.72      68.72      137.44     137.44     137.44     274.88
 137.44     137.44     137.44     274.88     274.88     274.88     549.76
 274.88     274.88     274.88     549.76     549.76     549.76    1099.51
 128.26     101.80     80.80      128.26     101.80     80.80      128.26

 128.26     101.80     80.80      128.26     101.80     80.80      128.26
5.36E+10   6.75E+10   8.51E+10   1.07E+11   1.35E+11   1.70E+11   2.14E+11
1.07E+11   1.35E+11   1.70E+11   2.14E+11   2.70E+11   3.40E+11   4.29E+11
Table 1e&f DRAM Introduction Product Generations and Chip Size Model

Year of Production                                    2007     2008     2009     2010     2011     2012     2013     2014     2015
DRAM ½ Pitch (nm) (contacted)                         68       59       52        45       40       36       32       28       25
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                     68       59       52       45       40       36       32       28       25
MPU Physical Gate Length (nm)                          32       29       27       24       22       20       18       17       15
Cell area factor [a]                                   6        6        6        6        6        6        6        6        6
                     2    2
Cell area [Ca = af ] (um )                           0.028    0.021    0.016    0.012    0.0096   0.0077   0.0061   0.0048   0.0038
Cell array area at introduction (% of chip size) §   73.52%   73.76%   73.97%   74.16%   74.30%   74.47%   74.61%   74.70%   74.83%
Generation at introduction §                          16G      16G      16G      32G      32G      32G      64G      64G      64G
Functions per chip (Gbits)                           17.18    17.18    34.36    34.36    34.36    68.72    68.72    68.72    68.72
                               2
Chip size at introduction (mm ) §                     652      493      745      563      446      706      560      444      351
 2016     2017     2018     2019     2020     2021      2022
 22.5     20.0     17.9     15.9     14.2     12.6      11.3
 22.5     20.0     17.9     15.9     14.2     12.6      11.3
 14.0     12.8     11.7     10.7     9.7       8.9       8.1
  6        6        6        6        6        6         6
0.0030   0.0024   0.0019   0.0015   0.0012   0.00096   0.00076
74.93%   75.00%   75.09%   75.18%   75.27%   75.36%    75.45%
 128G     128G     128G     256G     256G     256G      512G
137.44   137.44   137.44   274.88   274.88   274.88    549.76
 557      442      350      555      440      349       553
Table 1g&h MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model

Year of Production                                                  2007   2008    2009    2010    2011    2012    2013    2014    2015
DRAM ½ Pitch (nm) (contacted)                                       68      59      52      45      40      36      32      28      25
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                   68     59      52      45      40      36      32      28      25
MPU Physical Gate Length (nm)                                        32     29      27      24      22      20      18      17      15
SRAM Cell (6-transistor) Area factor ++                             97.5   100.7   104.1   107.8   106.7   105.7   104.8   104.1   103.4
Logic Gate (4-transistor) Area factor ++                            279    292     306     320     320     320     320     320     320
SRAM Cell (6-transistor) Area efficiency ++                         0.63   0.63    0.63    0.63    0.63    0.63    0.63    0.63    0.63
Logic Gate (4-transistor) Area efficiency ++                        0.5     0.5     0.5     0.5     0.5     0.5     0.5     0.5     0.5
SRAM Cell (6-transistor) Area (um2)++                               0.45   0.35    0.28    0.22    0.17    0.13    0.11    0.084   0.066
SRAM Cell (6-transistor) Area w/overhead (um2)++                    0.73   0.57    0.45    0.35    0.27    0.22    0.17    0.13    0.11
Logic Gate (4-transistor) Area (um2) ++                             1.3     1.0    0.82    0.65    0.51    0.41    0.32    0.26    0.20

Logic Gate (4-transistor) Area w/overhead (um2) ++                  2.6     2.1     1.6     1.3     1.0    0.82    0.65    0.51    0.41
                                               2
Transistor density SRAM (Mtransistors/cm )                          827    1,057   1,348   1,718   2,187   2,781   3,532   4,484   5,687
                                           2
Transistor density logic (Mtransistors/cm )                         154    194     245     309     389     490     617     778     980
Generation at introduction *                                        p10c   p10c    p13c    p13c    p13c    p16c    p16c    p16c    p19c
Functions per chip at introduction (million transistors
[Mtransistors])                                                     773    773     1546    1546    1546    3092    3092    3092    6184
                                 2
Chip size at introduction (mm ) ‡                                   280    222     353     280     222     353     280     222     353
                                           2
Cost performance MPU (Mtransistors/cm at
introduction) (including on-chip SRAM) ‡                            276    348     438     552     696     876     1104    1391    1753
Generation at production *                                          p07c   p07c    p07c    p10c    p10c    p10c    p13c    p13c    p13c
Functions per chip at production (million transistors
[Mtransistors])                                                     386    386     386     773     773     773     1546    1546    1546
                             2
Chip size at production (mm ) §§                                    140    111      88     140     111      88     140     111      88
                                           2
Cost performance MPU (Mtransistors/cm              at production,
including on-chip SRAM) ‡                                           276    348     438     552     696     876     1104    1391    1753
2016    2017    2018     2019     2020     2021     2022
22.5    20.0     17.9     15.9     14.2     12.6     11.3
22.5    20.0     17.9     15.9     14.2     12.6     11.3
14.0    12.8     11.7     10.7     9.7      8.9      8.1
102.8   102.2   101.7    101.3    100.9    100.5    100.1
320     320      320      320      320      320      320
0.63    0.63     0.63     0.63     0.63     0.63     0.63
 0.5     0.5     0.5      0.5      0.5      0.5      0.5
0.052   0.041   0.032    0.026    0.020    0.016     0.01
0.083   0.066   0.052    0.041    0.032    0.026    0.020
0.16    0.13     0.10    0.081    0.064    0.051    0.040

0.32    0.26     0.20     0.16     0.13     0.10     0.08
7,208   9,130   11,558   14,625   18,497   23,394   29,588
1,235   1,555   1,960    2,469    3,111    3,920    4,938
p19c    p19c    p22c     p22c     p22c     p25c     p25c

6184    6184    12368    12368    12368    24736    24736
280     222      353      280      222      353      280


2209    2783    3506     4417     5565     7012     8834
p16c    p16c    p16c     p19c     p19c     p19c     p22c

3092    3092    3092     6184     6184     6184     12368
140     111      88       140      111      88       140


2209    2783    3506     4417     5565     7012     8834
Table 1i&j High-Performance MPU and ASIC Product Generations and Chip Size Model

Year of Production                                                       2007    2008    2009    2010    2011    2012    2013     2014     2015
DRAM ½ Pitch (nm) (contacted)                                             68      59      52      45      40      36      32       28       25
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                        68      59      52      45      40      36      32       28       25
MPU Physical Gate Length (nm)                                             32      29      27      24      22      20      18       17       15
Logic (Low-volume Microprocessor) High-performance ‡
Generation at Introduction                                               p10h    p10h    p13h    p13h    p13h    p16h    p16h     p16h     p19h
Functions per chip at introduction (million transistors)                 2212    2212    4424    4424    4424    8848    8848     8848     17696
                                 2
Chip size at introduction (mm )                                           620     492     391     620     492     391     620      492      391
Generation at production **                                              p07h    p07h    p07h    p10h    p10h    p10h    p13h     p13h     p13h
Functions per chip at production (million transistors)                   1106    1106    1106    2212    2212    2212    4424     4424     4424
                             2
Chip size at production (mm ) §§                                         310     246     195     310     246     195      310      246      195
                                               2
High-performance MPU Mtransistors/cm               at introduction and
production (including on-chip SRAM) ‡                                    357     449     566     714     899     1133    1427     1798     2265
ASIC
                              2
ASIC usable Mtransistors/cm          (auto layout)                       357     449     566     714     899     1133    1427     1798     2265
                                           2
ASIC max chip size at production (mm ) (maximum lithographic
field size)                                                              858     858     858     858     858     858      858      858      858
ASIC maximum functions per chip at production
(Mtransistors/chip) (fit in maximum lithographic field size)             3,061   3,857   4,859   6,122   7,713   9,718   12,244   15,427   19,436
2016     2017     2018     2019     2020     2021      2022
 22.5     20.0     17.9     15.9     14.2     12.6     11.3
 22.5     20.0     17.9     15.9     14.2     12.6     11.3
 14.0     12.8     11.7     10.7     9.7      8.9       8.1


p19h     p19h     p22h     p22h     p22h     p25h      p25h
17696    17696    35391    35391    35391    70782    70782
 620      492      391      620      492      391       620
p16h     p16h     p16h     p19h     p19h     p19h      p22h
8848     8848     8848     17696    17696    17696    35391
 310      246      195      310      246      195      310


2854     3596     4531     5708     7192     9061     11416


2854     3596     4531     5708     7192     9061     11416


 858      858      858      858      858      858      1716

24,488   30,853   38,873   48,977   61,707   77,746   195,906
Table 2a&b Lithographic-Field and Wafer Size Trends

Year of Production                               2007   2008   2009   2010   2011   2012   2013   2014   2015
DRAM ½ Pitch (nm) (contacted)                    68     59     52      45     40     36     32     28     25
Flash ½ Pitch (nm) (un-contacted Poly)(f)         54     45     40     36     32     28     25     22     20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                68     59     52     45     40     36     32     28     25
MPU Physical Gate Length (nm)                     32     29     27     24     22     20     18     17     15
Lithography Field Size
                                            2
Maximum Lithography Field Size—area (mm )        858    858    858    858    858    858    858    858    858
Maximum Lithography Field Size—length (mm)        33     33     33     33     33     33     33     33     33
Maximum Lithography Field Size—width (mm)         26     26     26     26     26     26     26     26     26
Maximum Substrate Diameter (mm)—High-volume
Production (>20K parts wafer starts per month)
Bulk or epitaxial or SOI wafer                   300    300    300    300    300    450    450    450    450
2016   2017   2018   2019   2020   2021   2022
22.5   20.0   17.9   15.9   14.2   12.6   11.3
 18     16     14     13     11     10     9
22.5   20.0   17.9   15.9   14.2   12.6   11.3
14.0   12.8   11.7   10.7   9.7    8.9    8.1


858    858    858    858    858    858    858
 33     33     33     33     33     33     33
 26     26     26     26     26     26     26



450    450    450    450    450    450    450
Table 3a&bPerformance of Packaged Chips: Number of Pads and Pins

Year of Production                             2007       2008       2009        2010       2011       2012       2013       2014       2015
DRAM ½ Pitch (nm) (contacted)                   68         59         52          45         40         36         32         28         25
Flash ½ Pitch (nm) (un-contacted Poly)(f)       54         45         40          36         32         28         25         22         20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)              68         59         52          45         40         36         32         28         25
MPU Physical Gate Length (nm)                   32         29         27          24         22         20         18         17         15
Number of Chip I/Os (Number of Total Chip
Pads)—Maximum
Total pads—MPU unchanged                       3,072      3,072      3,072      3,072       3,072      3,072      3,072      3,072      3,072
Signal I/O—MPU (% of total pads)               33.3%      33.3%      33.3%      33.3%      33.3%       33.3%      33.3%      33.3%      33.3%

Power and ground pads—MPU (% of total pads)    66.7%      66.7%      66.7%      66.7%      66.7%       66.7%      66.7%      66.7%      66.7%

Total pads—ASIC High Performance unchanged     4,400      4,400      4,600      4,800       4,800      5,000      5,400      5,400      5,600
Signal I/O pads—ASIC high-performance (% of
total pads)                                    50.0%      50.0%      50.0%      50.0%      50.0%       50.0%      50.0%      50.0%      50.0%
Power and ground pads—ASIC high-performance
(% of total pads)                              50.0%      50.0%      50.0%      50.0%      50.0%       50.0%      50.0%      50.0%      50.0%

Number of Total Package Pins—Maximum [1]

Microprocessor/controller, cost-performance   600–2140   600–2400   660–2801   660–2783   720- 3061   720–3367   800–3704   800-4075   880–4482
Microprocessor/controller, high-performance    4000       4400       4620        4851       5094       5348       5616       5896       6191
ASIC (high-performance)                        4000       4400       4620        4851       5094       5348       5616       5896       6191
  2016      2017       2018        2019         2020         2021        2022
  22.5       20.0       17.9       15.9         14.2         12.6        11.3
   18        16         14          13           11           10          9
  22.5       20.0       17.9       15.9         14.2         12.6        11.3
  14.0       12.8       11.7       10.7          9.7          8.9         8.1



 3,072      3,072      3,072       3,072       3,072         3,072       3,072
 33.3%      33.3%      33.3%      33.3%        33.3%        33.3%       33.3%

 66.7%      66.7%      66.7%      66.7%        66.7%        66.7%       66.7%

 6,000      6,000      6,200       6,200       6,200         6,840       6,840

 50.0%      50.0%      50.0%      50.0%        50.0%        50.0%       50.0%

 50.0%      50.0%      50.0%      50.0%        50.0%        50.0%       50.0%




880–4930   960-5423   960–5966   1050-6562   1050 - 7218   1155-7940   1155-8337
  6501      6826       7167        7525         7902         8297        8712
  6501      6826       7167        7525         7902         8297        8712
Table 4a&b Performance and Package Chips: Pads, Cost

Year of Production                                          2007       2008       2009       2010      2011      2012      2013       2014        2015
DRAM ½ Pitch (nm) (contacted)                                68         59         52         45         40        36        32         28          25
Flash ½ Pitch (nm) (un-contacted Poly)(f)                    54         45         40         36         32        28        25         22          20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                           68         59         52         45         40        36        32         28          25
MPU Physical Gate Length (nm)                                32         29         27         24         22        20        18         17          15
Chip Pad Pitch (micron)
Pad pitch—ball bond                                          30         30         25         25         25        20        20         20          20
Pad pitch— Wedge bond                                        25         25         20         20         20        20        20         20          20
Pad Pitch— Area array flip-chip (cost-performance, high-
performance)                                                 130        130        130        130       120       110       110        100         100
Pad Pitch— 2-row staggered-pitch (micron)                    55         50         45         45         45        40        40         40          40
Pad Pitch— Three-tier-pitch pitch (micron)                   60         60         60         55         55        50        45         45          45
Cost-Per-Pin
Package cost (cents/pin) (Cost per Pin Minimum for
Contract Assembly – Cost-performance) —
minimum–maximum                                            .69-1.19   .66-1.13   .63-1.70   .60-1.20   .57-.97   .54-.92   .51-.87   .48 - .83   .46 - .79
Package cost (cents/pin) (Low-cost, hand-held and
memory) — minimum–maximum                                  .27-.50    .25-.48    .24-.46    .23-.44    .22-.42   .21-.40   .20-.38   .20-.36     .20 -.34
 2016        2017        2018        2019        2020       2021        2022
  22.5        20.0        17.9        15.9        14.2       12.6       11.3
   18          16          14          13          11         10         9
  22.5        20.0        17.9        15.9        14.2       12.6       11.3
  14.0        12.8        11.7        10.7        9.7        8.9         8.1


   20          20          20          20          20         20         20
   20          20          20          20          20         20         20

   95          95          90          90          85         85         80
   35          35          35          35          35         35         35
   45          45          45          45          45         45         45




.44 - .75   .42 - .71   .39 - .68   .37 - .64   .35 - .61   .33-.58   0.32-0.55

.20-.32     .20-.30     .20-.29     .20-.27     .20-.26     .19-.25    .19-.25
Table 4c&d Performance and Package Chips: Frequency On-chip Wiring Levels

Year of Production                                       2007         2008         2009         2010        2011         2012         2013         2014         2015
DRAM ½ Pitch (nm) (contacted)                             68           59           52           45          40           36           32           28           25
Flash ½ Pitch (nm) (un-contacted Poly)(f)                 54           45           40           36          32           28           25           22           20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                        68           59           52           45          40           36           32           28           25
MPU Physical Gate Length (nm)                             32           29           27           24           22          20           18           17           15
Chip Frequency (MHz)
On-chip local clock [1]                                  4.700        5.063        5.454       5.875        6.329        6.817        7.344        7.911       8.522
Maximum number wiring levels [3] [**]                     11           12           12           12           12          12           13           13           13


[**] [Note ** : The Interconnect TWG has deleted their "optional levels" from table 80a&b, therefore the ORTC "Maximum number wiring levels - maximum" line is deleted; also the "Maximum nu
                       2016        2017         2018         2019         2020         2021         2022
                       22.5         20.0         17.9        15.9         14.2         12.6         11.3
                        18           16          14           13           11           10           9
                       22.5         20.0         17.9        15.9         14.2         12.6         11.3
                       14.0         12.8         11.7        10.7          9.7          8.9          8.1


                      9.180        9.889       10.652       11.475       12.361       13.315       14.343
                        13           14          14           14           14           15           15


" line is deleted; also the "Maximum number wiring levels - minimum" is now just "Maximum number of wiring levels."
Table 5a&b Electrical Defects [**]

Year of Production                                    2007   2008   2009   2010   2011   2012   2013   2014   2015
DRAM ½ Pitch (nm) (contacted)                         68     59     52      45     40     36     32     28     25
Flash ½ Pitch (nm) (un-contacted Poly)(f)              54     45     40     36     32     28     25     22     20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                     68     59     52     45     40     36     32     28     25
MPU Physical Gate Length (nm)                          32     29     27     24     22     20     18     17     15
Flash Random Defect D 0 at production chip size and
                         2
89.5% yield (faults/m ) §                             2503   2503   2503   2503   2503   2503   2503   2503   2503
Flash Random Defect D 0 at production chip size and
                         2
89.5% yield (faults/m ) §                             2503   2503   2503   2503   2503   2503   2503   2503   2503
DRAM Random Defect D 0 at production chip size and
                         2
                                                      3517   2957   2957   2957   2957   2957   2957   2957   2957
89.5% yield (faults/m ) §
DRAM Random Defect D 0 at production chip size and
                         2                            2430   2430   2430   2430   2430   2430   2430   2430   2430
89.5% yield (faults/m ) §
MPU Random Defect D 0 at production chip size and
                     2
83% yield (faults/ m ) §§                             1395   1395   1395   1395   1395   1395   1395   1395   1395
# Mask Levels—MPU                                      33     35     35     35     35     35     37     37     37
# Mask Levels—DRAM                                     24     24     24     26     26     26     26     26     26
# Mask Levels—Flash [to be added in 2009]              ??     ??     ??     ??     ??     ??     ??     ??     ??
2016   2017   2018   2019   2020   2021   2022
22.5   20.0   17.9   15.9   14.2   12.6   11.3
 18     16     14     13     11     10     9
22.5   20.0   17.9   15.9   14.2   12.6   11.3
14.0   12.8   11.7   10.7   9.7    8.9    8.1


2503   2503   2503   2503   2503   2503   2503


2503   2503   2503   2503   2503   2503   2503

2957   2957   2957   2957   2957   2957   2957


2430   2430   2430   2430   2430   2430   2430



1395   1395   1395   1395   1395   1395   1395
 37     39     39     39     39     39     39
 26     26     26     26     26     26     26
 ??     ??     ??     ??     ??     ??     ??
Table 6a&b Power Supply and Power Dissipation

Year of Production                                       2007   2008   2009   2010   2011   2012   2013   2014   2015
DRAM ½ Pitch (nm) (contacted)                            68     59     52      45     40     36     32     28     25
Flash ½ Pitch (nm) (un-contacted Poly)(f)                 54     45     40     36     32     28     25     22     20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                        68     59     52     45     40     36     32     28     25
MPU Physical Gate Length (nm)                             32     29     27     24     22     20     18     17     15
Power Supply Voltage (V)
Vdd (high-performance)                                   1.1    1.0    1.0    1.0    0.95   0.90   0.90   0.90   0.80
Vdd (high-performance)                                   1.1    1.1    1.1    1.1    1.0    1.0    1.0    1.0    1.0


V dd (Low Operating Power, high V dd transistors)[WAS]   0.80   0.80   0.80   0.70   0.70   0.70   0.60   0.60   0.60
V dd (Low Operating Power, high V dd transistors)        0.90   0.80   0.80   0.80   0.77   0.70   0.70   0.65   0.60
Allowable Maximum Power [1]
High-performance with heatsink (W)                       102    146    143    146    161    158    149    152    143
Maximum Affordable Chip Size Target for High-
performance MPU Maximum Power Calculation                310    310    310    310    310    310    310    310    310
Maximum High-performance MPU Maximum Power
Density for Maximum Power Calculation                    0.33   0.47   0.46   0.47   0.52   0.51   0.48   0.49   0.46
Cost-performance (W)                                     102    146    143    146    161    158    149    152    143
Maximum Affordable Chip Size Target for Cost-
performance MPU Maximum Power Calculation                140    140    140    140    140    140    140    140    140
Maximum Cost-performance MPU Maximum Power
Density for Maximum Power Calculation                    0,57   0.86   0.9    0.96   1.13   1.11   1.1    1.17   1.19
Battery (W)—(low-cost/hand-held)                          3      3      3      3      3      3      3      3      3
2016   2017   2018   2019   2020   2021   2022
22.5   20.0   17.9   15.9   14.2   12.6   11.3
 18     16     14     13     11     10     9
22.5   20.0   17.9   15.9   14.2   12.6   11.3
14.0   12.8   11.7   10.7   9.7    8.9    8.1


0.80   0.70   0.70   0.70   0.65   0.65   0.65
0.90   0.90   0.90   0.90   0.80   0.80   0.80


0.50   0.50   0.50   0.50   0.50   0.45   0.45
0.60   0.60   0.60   0.57   0.50   0.50   0.50


130    130    136    133    130    130    130

310    310    310    310    310    310    310

0.42   0.42   0.44   0.43   0.42   0.42   0.42
130    130    136    133    130    130    130

140    140    140    140    140    140    140

1.07   1.12   1.19   1.27   1.24   1.63   1.73
 3      3      3      3      3      3      3
Table 7a&b Cost

Year of Production                                               2007   2008   2009   2010   2011   2012   2013   2014   2015
DRAM ½ Pitch (nm) (contacted)                                    68     59     52      45     40     36     32     28     25
Flash ½ Pitch (nm) (un-contacted Poly)(f)                         54     45     40     36     32     28     25     22     20
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)                                68     59     52     45     40     36     32     28     25
MPU Physical Gate Length (nm)                                     32     29     27     24     22     20     18     17     15
Affordable Cost per Function ++

DRAM cost/bit at (packaged microcents) at samples/introduction   2.6    1.9    1.3    0.9    0.7    0.5    0.3    0.2    0.2
DRAM cost/bit at (packaged microcents) at production §           0.96   0.68   0.48   0.34   0.24   0.17   0.12   0.08   0.06
Cost-performance MPU (microcents/transistor)
(including on-chip SRAM) at introduction §§                      22.0   15.6   11.0   7.8    5.5    3.9    2.8    1.9    1.4
Cost-performance MPU (microcents/transistor)
(including on-chip SRAM) at production §§                        13.3   9.4    6.7    4.7    3.3    2.4    1.7    1.2    0.83
High-performance MPU (microcents/transistor)
(including on-chip SRAM) at production §§                        12.2   8.6    6.1    4.3    3.0    2.2    1.5    1.1    0.76
2016   2017   2018   2019   2020   2021   2022
22.5   20.0   17.9   15.9   14.2   12.6   11.3
 18     16     14     13     11     10     9
22.5   20.0   17.9   15.9   14.2   12.6   11.3
14.0   12.8   11.7   10.7   9.7    8.9    8.1



0.1    0.1    0.1    0.0    0.0    0.0    0.0
0.04   0.03   0.02   0.01   0.01   0.01   0.01

0.97   0.69   0.49   0.34   0.24   0.17   0.12

0.59   0.42   0.29   0.21   0.15   0.10   0.07

0.54   0.38   0.27   0.19   0.13   0.10   0.07

				
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