QUARTUS II INTRODUCTION USING VERILOG DESIGN by kikel

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									     VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY
INTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER
                       (ICDREC)




  QUARTUS II INTRODUCTION 
   USING VERILOG DESIGN


                 By NGO DUC HOANG
                 DEPUTY DIRECTOR

                      FEB – 18 - 2007
A TYPICAL FPGA CAD FLOW
                  Design Entry

                    Synthesis

              Functional Simulation

     No
                 Design correct?

                            Yes

             Fitting (Place and Route)


          Timing Analysis and Simulation

     No
             Timing requirements met?

                                Yes

          Programming and Configuration
  QUARTUS II DEVELOPMENT
         SYSTEM
 Fully-integrated Design Tool
 Multiple Design Entry Methods
 Logic Synthesis
 Place and Route
 Simulation (functional and timing)
 Timing and Power Analysis
 Device Programming and Configuration
       Design Entry (1 of 2)
The desired circuit is specified by:
   A schematic diagram

   A hardware description language,

    such as:
     Verilog

     VHDL

      AHDL…
Design Entry (2 of 2)
Design Entry by a schematic diagram
Design Entry by a hardware 
   description language
                  Synthesis
   The entered design is synthesized into a 
    circuit that consists of the logic elements 
    (LEs) provided in the FPGA chip.
   LE is the smallest unit of logic of Altera’s 
    FPGA. It’s compact and provides 
    advanced features with efficient logic 
    ultilization.
   This course doesn’t cover the architecture 
    of Altera’s FPGA
LE logic element
    Fitting (placement and routing)
   The placement of the LEs defined in the 
    netlist into the LEs in an actual FPGA chip, 
    also choose routing wires in the chip to 
    make the required connections between 
    specific LEs
             Timing Analysis
   Analyze the propagation delays along the 
    various paths in the fitted circuit 
             Timing Simulation
   The fitted circuit is tested to verify both its 
    functional correctness and timing
Programming and Configuration
   The design circuit is implemented in a 
    physical FPGA chip by programming the 
    configuration switches that configure the 
    LEs and establish the required wiring 
    connections
Quartus II Project Management
  What is a Project ?
   ­ A logic circuit or subcircuit
   ­ A project is:
       + checked for design entry errors
       + compiled
       + simulated (functional or timing)
       + analyzed for timing
       + used to generate programming file
 Quartus II works on one project at a time and 
   keeps all information for that project in a single 
   directory (folder).
Quartus II Project –New Project
                Select File > New Project Wizard
                New Project Wizard help us create a new
                  project and preliminary project
            1     settings, including the following:
                • Project name and directory
                • Name of the top-level design entity
                • Project files and libraries

        2       • Target device family and device
                • EDA tool settings
                You can change or add the settings of the
                  project with the Settings command
                  (Assignment menu)
Quartus II Project – Directory, Name, Top-
               Level Entity
                          • You can choose any
                          directory name if you
                          prefer. If we have not yet
                          created the directory of
                          the project, Quartus II
                          asking if it should create
                          the desired directory.
                          • The project must have a
                          name, which is usually
                          the same as the top-level
                          design entity
Quartus II Project – Add Files
                 To specify existing
                 files should be
                 included in the
                 project.

                 Click Next if we do
                 not have any existing
                 files.

                      3
Quartus II Project – Family and Device
                Settings
                      To specify the type of
                      device in which the
                      designed circuit will be
                      implemented. In case of
                      DE2 board, we choose:

                       • The target device family
                       is Cyclone II

                       • The device is
                       EP2C35F672C6 which
                       is the FPGA used on
                       DE2 board
    Quartus II Project – EDA Tools
                Settings
                     To specify any third-
                     party tools that
                     should be used. EDA
                     is means Electronic
                     Design Automation,
                     a commonly used
                     term for CAD
                     software for
4                    electronic circuits.
    Quartus II - Summary




5
  Design Entry using Verilog – An
             example




module   light(x1,x2,f);
         input     x1,x2;
         output    f;
         assign    f = (x1&~x2)|(~x1&x2);
endmodule
Design Entry using Verilog – Quartus II
         Text Editor (1 of 6)
                               Select File >
                               New to get
              3
                               the right
       1                       figure, then
                               choose
                               Verilog
 2
                               HDL File,
                               and click
                  4            OK
Design Entry using Verilog – Quartus II
         Text Editor (2 of 6)
                          Quartus II open the
                          Text Window
                          Editor. The default
                          name of design file
                          is Verilog1.v. The
                          first step is to
                          specify a name for
                          the file that will be
                          created. Select File
                          > Save As
Design Entry using Verilog – Quartus II
         Text Editor (3 of 6)
                       In the box labeled Save
                       as type choose Verilog
                       HDL File.
                        In the box labeled
                        File name , type light
                       Put a checkmark in the
                       box Add file to current
                       project

                       Click Save
Design Entry using Verilog – Quartus II
         Text Editor (4 of 6)
                          Type the Verilog
                          code of our
                          design into Text
                          Editor.
                          Save the file
                          light.v by choose
                          File > Save.
Design Entry using Verilog – Quartus Text
             Editor (5 of 6)
Design Entry using Verilog – Quartus II Text
              Editor (6 of 6)

                               We can change
                               the options of
                               Text Editor of
                               Quartus II by
                               the settings in
                               Tools >
                               Options > Text
                               Editor
Design Entry using Verilog – Adding
           Design Files
                      If light.v is not a part of
                      the project, this file must
                      be added to the project.
                      For example: if you did
                      not use the Quartus II Text
                      Editor, then you place a
                      copy of the file light.v,
                      which you created using
                      some other text editor, into
                      the directory
                      introductorial. To add this
                      file to the project, click on
                      the light.v file and click
                      Open
    Compilation (1 of 2)
               Verilog code in the design file
               light.v is processed by the
               application program called the
               Compiler.
               The Compiler :

1
               - Analyze the code
               - Synthesize the circuit
               - Generate an implementation of
               the circuit for the target chip.
           2   Selecting Processing > Start
               Compilation
Compilation (2 of 2)




    3
             Pin Assignment
 Purpose: map the I/O signals of your design to
  the physical pins of selected FPGA.
 Pin assignments are made by:
• Assignment Editor (manual), or
• Import a pin assignment from a special file
  format – comma separated value (CSV)
  format.
Note: All relevant pin assignments for the DE2
  board are given in the file called
  DE2_pin_assignments.csv in the CD-ROM or
  on the Altera’s DE2 web pages.
    Pin Assignment – Assignment Editor

                         Select Assignments >
                         Assignments Editor
                         We will use two toggle
                         switches, labeled SW0
1                        (PIN_N25) and
                         SW1(PIN_N26), to provide
                         the external inputs, x1 and
                         x2.
                     2
                         We will connect the output f
                         to the green light-emitting
                         diode labeled LEDG0
                         (PIN_AE22)
Pin Assignment – Assignment Editor
                       1. Select Pin in Category


                       2. Double click on the
                       entry <<new>> which
                       is highlighted in blue
                       in the column labeled
                       To. The drop-down
                       menu appear. Click on
                       x1
                       3. Double click on the
                          box into the column
                          labeled Location.
                          The drop-down
                          menu appear. Scroll
                          down and select
                          PIN_N25
Pin Assignment – Assignment Editor
                           1. Use the
                              same
                              procedure to
                              assign input
                              x2 to
                              PIN_N26
                              and output f
                              to
                              PIN_AE22.
                           2. Choose File
                              > Save
                           3. Recompile
Pin Assignments – Using
DE2_pin_assignments.csv
                   We can
                   download
                   DE2_pin_assign
                   ments.csv from
                   http://www.altera
                   .com/education/u
                   niv/materials/boa
                   rds/DE2_pin_assi
                   gnments.csv
          Pin Assignments – Using
          DE2_pin_assignments.csv
If we want to make the pin assignments for our 
   circuit by importing DE2_pin_assignments.csv, 
   we would have to use the same names in 
   Verilog coding:

1 module light1(SW,LEDG);
2    input         [1:0]SW;
3    output         [0:0]LEDG;
4    assign LEDG[0] = (SW[0]&~SW[1])|(~SW[0]&SW[1]);
5 endmodule
Pin Assignments – Using
DE2_pin_assignments.csv




        Chossing Assignments > Import
        Assignments
        Type (or browse to find) the full path to the
        directory that hold
        DE2_pin_assignments.csv
        Recompile
            Simulating


    1
1
        2




                         3
Simulating



             4




             5
    Simulating
6




                 7
8       Simulating
                          10. Enter 200ns in this dialog box




                                                  11




    9. Setting the interval time for simulating
12
     Simulating




      13. Setting displays the entire simulation range of
             0 to 200ns in the waveform window
14
        Simulating



                                                 16. This utility
                                                   has a filter
                                                     used to
                                                 indicated what
                                                  type of nodes
                                                 are to be found




     15. To include the input and output nodes
           of the circuit to be simulated
                                   Simulating




17. Set the filter to Pins:all if we are interested
            in input and output pins                  18
    Simulating




                              20. Click the > sign to add it to
                                    Selected Nodes box




19. Click on the x1 signal to select it
          Simulating   23        25




                            24




21   22
Simulating




             26
Simulating
             27. Click on x1 to draw
              the waveforms for x1
                      node.
To setting x1 to 1 in the
  time interval 100 to
                               Simulating
200ns, you do as follows:




                                     28. Press the mouse     29. Dragging it
      30. Choose the logic 1          at the start of the   To the end of the
           In the toolbar              interval (100ns)      Interval (200ns)
 31.We setted x1 to 1
 from 100ns to 200ns.
                           Simulating
For setting x2 to 1from
50 to 100ns and also 150
    to 200ns, you do
       as follows:




 32. Press the mouse
at 50ns and drag it to
 100ns.Then, choose
the logic 1 in the tool        33. Press the mouse
          bar                 at 150ns and drag it to
                               200ns.Then, choose
                              the logic 1 in the tool
                                        bar
          Simulating – Functional Simulating



34




     35
Simulating – Functional simulating
                                     36




                                     37




           38
Simulating – Functional Simulation
                     39




40
Simulating – Functional Simulating




                           41
     Simulating – Functional Simulating



42




                               43
Simulating – Functional Simulating




                          44
Simulating – Functional Simulating
                     If your report window does
                    not show the entire time range
                      (200ns) you do as follows:




               45




          46
Simulating – Functional Simulating




           Check the value of f as
          the output of EX-OR with
            two inputs x1 and x2:
                f=0 iff x1 = x2
 Simulating ­ Timing Simulation



             47




48
Simulating – Timing Simulation

                                 49




                        50




       51
     Simulating – Timing Simulation



52




                           53
Simulating – Timing Simulation




54
Simulating – Timing Simulation




 There is a delay of about 6ns in producing
 a change in the signal f from the time
 when the input signal x1 or x2 change
 the their values. The delay is due to the
 propagation delay in the logic element and
 the wires in the FPGA device.
    Programming and Configuring – 
         JTAG Programming
 JTAG = Joint Test Action Group
 If the FPGA is configured in JTAG 

  mode, it will retain its configuration as 
  long as the power remain turned on and 
  lost when the power turned off.
 In this mode, you must flip the 

  RUN/PROG switch of DE2 board into 
  the RUN position
          Programming and Configuring – 
               JTAG Programming



55




     56
Programming and Configuring – 
     JTAG Programming



                                 57
            58. If not ready
           choose by default,
           select JTAG in the
               Mode box
 Programming and Configuring – 
      JTAG Programming




59


                                  60
     Programming and Configuring – 
          JTAG Programming




                                      62


61. If the USB-Blaster
is not choosen by defaut,
select USB-Blaster in
this window
Programming and Configuring – 
     JTAG Programming




             64        63. Click on the
                       Programm/Configure
                       Check box
    Programming and Configuring – AS 
             Programming
   AS = Active Serial 
   If the FPGA is configured in AS mode, the 
    configuration data has to be loaded into the 
    configuration device, which is identified by the 
    name EPCS16. Then, this data is loaded into 
    the FPGA upon power up or reconfiguration.
   In this mode, you must flip the RUN/PROG 
    switch of DE2 board into the PROG position
 Programming and Configuring – AS 
          Programming




65

                  66
Programming and Configuring – AS 
         Programming




 67
                             68
Programming and Configuring – AS 
         Programming




                              69


          70


               71
Programming and Configuring – AS 
         Programming




       72
Programming and Configuring – AS 
         Programming




    73. Recompile the
     designed circuit
Programming and Configuring – AS 
         Programming




   74
          Programming and Configuring – 
               JTAG Programming



75




     76
Programming and Configuring – AS 
         Programming




                                   77
            78. If not ready
            choose by default,
            select Active Serial
            Programming in the
            Mode box
Programming and Configuring – AS 
         Programming




79. If you are changing the
Mode from the previously
 JTAG mode, this box ask if you
want to clear all devices
     Programming and Configuring – AS 
              Programming




                                     81. Select the
80. If the configuration file        file light.pof
                                83
 is not already listed in the
  window, press Add File
Programming and Configuring – AS 
         Programming




                                  84. Check mark
                                  on the Program/
                                Configure check box



85. Press Start. Note to flip
the RUN/PROG switch on
the DE2 board to the PROG
position
                 Some references
   "Altera's Quartus® II software is such a superior
    development environment that I am quickly
    forgetting about any other PLD (programmable logic
    device) design tool."
       Can Nguyen, Principal Staff Engineer, 
        Broadband Communications Sector, Motorola


   "Quartus® II software is superior compared to other 
    programmable logic tool offerings, which allows us 
    to focus our time on meeting customer needs, rather 
    than laboring over tool usage.“
       Dr. Greg Caso, VP Engineering, Escape Communications

								
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