Analogue integrated circuit design for sustained neurons in a

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							Analogue integrated-circuit design for
sustained neurons in a fly
                                                                                Eqn. 2 can be shown to be identical to eqn. 1 by rearranging its
G.B. Zhang, G. Bayramoglu, J. Liu and H. Ogmen
                                                                                terms and by letting z, = V,, a = Vale,p = Zap/Va y = &/e.
                                                                                                                                      and
        An analogue integratedcircuit design of a fly’s sustained neurons       The output of the second multiplier MUL2 is proportional to the
        is presented. Circuit simulation of the design shows that the           excitatory input to the ith cell. Inhibitory inputs from adjacent
        output exhibits non-associative learning in agreement with              spatial locations are subtracted from this excitatory input by using
        electrophysiologicalstudies of these neurons. The output is shown       inverter and adder circuits (not shown in Fig. I) to produce the
        to encode the contrast of the input.                                    output of the sustained cell at the ith location.

Introduction: The fly offers an excellent prototype for biomimetic
vision processors and navigation systems, due to its robust opto-
motor behaviour and its relatively simple nervous system.
                                                                                       2‘6   1              peak

Recently, several neuromorphic vision sensors based on the fly’s
visual system have been built and tested [I]. Neurophysiological
studies [2, 31 suggest that the fly optomotor system receives inputs
from sustained neurons located in the first optic ganglion, the lam-
ina. Existing neuromorphic vision sensors have not yet incorpo-
rated a model for these neurons into their design and do not
capture the full functionality of the fly optomotor system. We
present here an analogue integrated-circuit design for these sus-
 tained neurons. The design can be used as an ‘early visual proces-
 sor’ with spatio-temporal adaptation properties. The proposed                         2.0
 circuit can also be integrated as a front end to opto-motor naviga-
 tion systems.
                                                                                       1.9 J                                                          I
                                                                                           0        0.05   0.10       0.15     0.20     0.25      0.30
   t      f        f              VED                           VED                                                 time, ms
                                                                                                                                            1449/21
                                                                                Fig. 2 Response of sustained unit to step input with onset and rise times
                                                                                of 0.1 and 0.01 ms, respectively
                                                                                Inputs Z and J were 2 and 20 pA, respectively
                                                               flu:

                                                                                      2.5 1
                                                                T      vc

                                                      output          GND

          a                                       b                                   2.3
                                                                                  >
                                                                 1449/1(          a-
                                                                                  C
                                                                                  Q
Fig. 1 Model and circuit design for sustained units
                                                                                  ??
a Model
b Circuit design                                                                        .
                                                                                       21



Circuit design: Our design is based on a neural network model for
the fly’s sustained neurons [4] whose activities had been recorded
in the chiasm between the lamina and the second optic ganglion,                        1.9    I                                                           1
the medulla [5, 61. The model is shown in Fig. la. The luminance                             10-1                      100                            101
signal at the spatial position i is denoted by 4. A baseline signal I                                             Weber contrast
is added to J, to represent the spatially uniform background lumi-
nance, as well as the internal signal that sets a baseline neural
activity when the external signal is zero (the dark current). The               Fig. 3 Peak and plateau values o response against Weber contrast
                                                                                                                f
                                                                            ’   (defined as J/I)
suinmed signal is transmitted via synapses whose gain zichanges
as a function of the input, following                                           0 peak
                                                                                0 plateau
                   dzi
                   -=4
                   dt        P - .i)   - ?%(I+ J i )
                                                                                Results: We designed and simulated the circuits with Cadence
where t is time, and a,p and y are parameters related to the syn-               Analog Artist and SPICE in TSMC 0.35 pn process. Fig. 2 shows
aptic transmission process [4, 71. These Variable-gain synapses are             the output waveform obtained for a step input. Following the
depicted by hatched rectangular shapes in Fig. la. The output of                onset of the step, the output initially rises to approximately 2.5V
this stage is given by the product of the input and the synaptic                and rapidly decays to a plateau value of 2.3 V. This output wave-
gain, i.e. z,(Z + JJ, and provides the excitatory drive (depicted by            form illustrates the non-associative learning property of sustained
semicircularhatched synaptic symbols) for the sustained neuron at               neurons. Non-associative learning consists of sensitisation and
the spatial location i. The sustained neuron also receives inhibitory           habituation. Sensitisation corresponds to an increased response to
inputs (depicted by semicircular open synaptic symbols) from                    novel stimulus, which in our simulations is observed as an over-
adjacent spatial locations.                                                     shoot response to stimulus onset. Habituation corresponds to a
   Key elements of the circuit design for the sustained neuron are              decreased response to sustained stimuli, which in our simulations
shown in Fig. lb. Two modified Gilbert multipliers (MULI and                    is observed as a decay of the response. Similar output waveforms
MUL2) are the main components of the circuit. Let the voltage                   had been reported in neurophysiological studies [5, 61 and model
across the capacitor C be denoted by V,. Using the symbols                      simulations [4]. Non-associative learning in our model leads to
defined in Fig. 1, this voltage can be written as                               adaptive and nonlinear encoding of the input luminance, a crucial
ELECTRONICS LETTERS                    5th July 2001                    c
                                                               Vol. 37 N 3. 14                                                                            867
aspect of early vision processing. We studied the dependence of                                         CMOS current-mode exponential-control
the output on the amplitude of the input in a series of simulations,                                    variable-gain amplifier
which showed that the peak and the plateau values of the response
are nonlinear monotonic increasing functions of J and nonlinear                                         C.-C. Chang, M.-L. Lin and %-I. Liu
monotonic decreasing functions of I. Together, these results sug-
gest that the circuit encodes the contrast rather than the absolute                                             A CMOS current-mode exponential-control variable-gain
amplitude of the input. Fig. 3 shows that the peak and the pla-                                                 amplifier is presented. It consists of a first-order current-mode
teau values of the response are approximately linear functions of                                               pseudo-exponential circuit and a current-mode multiplier. Based
Weber contrast on a logarithmic scale. Fig. 4 shows that the peak                                               on the Taylor’s series expansion, the pseudo-exponential circuit
and the plateau values of the response are approximately linear                                                 can be realised by MOSFETs in saturation. The proposed circuit
functions of Michelson contrast on a linear scale, in particular                                                has been fabricated in a 0.5 pm N-well CMOS process with a gain
when contrast is above 0.3.                                                                                     control range of 15dB. The experimental results confitm the
                                                                                                                feasibility of the proposed varidble-gain amplifier.


        2’6   1                                                             /                           Introduction: A multiplier with an input signal and an exponential
                                                                                                        input can realise a variable-gain amplifier (VGA). Traditionally,
        2.4   -                                                                                         the exponential input circuit is implemented in bipolar technology
                                                                                                        due to the exponential characteristics. It could not be realised
   >                                                                                                    directly by MOSFETs in saturation due to square-law characteris-
   ai
   6    2.2   -                                                                                         tics. Thus, several pseudo-exponential functions [l - 61 have been
   Q                                                                                                    explored. In this Letter, a CMOS current-mode VGA,which con-
   2                                                                                                    sists of a pseudo-exponential circuit and a current-mode multi-
                                                                                                        plier. is presented. The pseudo-exponential circuit is based ton the
        2.0 -                                                                                           approximated Taylor’s series. The proposed circuits have been
                                                                                                        fabricated in a 0.5 pn N-well CMOS process and the experimental
                                                                                                        results are given to demonstrate this proposed VGA.
        1.84
              0
                  ‘   ‘    -
                          0.2
                                . . .
                                        0.4
                                              .   ’   ’
                                                          0.6
                                                                .   ’   ‘
                                                                            0.8
                                                                                  ’   ‘   ‘
                                                                                              1.o
                                   Michelson contrast
                                                                                  1449/41
Fig. 4 Peak and plateau values of response against Michelson contrast
(defined as J/(J f 21))
0 peak
0 plateau                                                                                                              a                                b
                                                                                                                                                                      1052/11
                                                                                                                                                                      I    1

                                                                                                        Fig. 1 First-order pseudo-exponential circuit and current-mode mur‘tiplier
Conclusion: Simulations of the proposed design have shown that                                          a Exponential circuit
the circuit exhibits non-associative learning and encodes the con-                                      b Multiplier
trast rather than the absolute amplitude of the input. These prop-
erties result from temporal and spatial adaptation achieved
through variable-gain synapses and lateral inhibition, respectively.

0 IEE 2001                                                                            8 May 2001
Electronics Letters Online No: 20010631
D 01: IO. 1049/el:20010631
G.B. Zhang and J. Liu (Department of Electrical Engineering, The                                        Fig. 2 Photograph showing pseudo-exponential circuit ana’ multijdier
,University of Texas at Dallas, PO Box 830688, EC33, Richardson, T X
75083-0688, USA)
                                                                                                        Circuit implementation: The proposed VGA consists of a current-
G. Bayramoglu and H. Ogmen (Department of Electrical & Computer                                         mode multiplier and a current-mode first-order pseudo-exponen-
Engineering, University of Houston. Houston, T.Y 77204-4005, USA)
                                                                                                        tial circuit. The pseudo-exponential circuit is shown in Fig. l a
E-mail: ogmen@uh.edu                                                                                    [2, 61, the PMOS and NMOS transistors being in saturati” and
                                                                                                        having the same transconductance parameters, K. The drain cur-
                                                                                                        rents of A41 and M 2 can be given as
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                                                                                                                           ~          -      Furthermore, according to the
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                                                                                                                                                            Z           ,,
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   Physiol. A , 1993, 173, pp. 187-192                                                                  4 . 5 7 5 5 IcTRIKGZ 5 0.815 and the output dynamic range can be
   CARPENTER, G.A , and GROSSBERG, s.: ‘Adaptation and transmitter                                      15dB. Inversely, taking the output current, I y , from the two
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868
    1981, 1, pp. 1-42                                                                                   function can be obtained as
                                                                                                    ELECTRONICS LETTERS              5th July2001           Vol. 37       No. 74
                                                                                                                                                                                     .

						
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