Microframe Technologies

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Microframe Technologies Powered By Docstoc
					              Home Network Ready!
                Design Issues and
              Verification Challenges
                       Thomas Chow
                Mentor Graphics Corporation
                    Inventra, IP Division



May 9, 2001                                   2
              Historic Trend




May 9, 2001                    3
              Appliance Semiconductor
              Market Snap Shot




May 9, 2001                             4
              Technology Trend




May 9, 2001                      5
              Home Network
              Gateway Growth




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              Typical Home Network

   HN                                 Network
  Device                               Shops


                           Internet   Network
     HN
                 Gateway               Bank
    Device



     HN                               Network
    Device                             BtoB

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              Typical Network
              Appliance Architecture


                Device     uP / uC    Firmware
                 logic
                  and                              I/F
                User I/F

                           Network Transfer Protocol




May 9, 2001                                              9
                      SoC is Difficult
                      Because It’s a SYSTEM
                                              System
                                             Trade-Offs
                                 SOFTWARE                                HARDWARE
              Reiteration Loop




                                                                                                           Reiteration Loop
                                                              Embedded            Digital
                                 Embedded                                          Logic/         Analog
                                  Software                      Cores             Memory
                                                                  Integration &         Integration &
                                                                   Verification          Verification

                                              Integration &
                                               Verification

                                             Manufacturing


   Multiple Technologies - Hardware/Software, Analog/Digital
   Multiple Teams - Hardware (Analog/Digital), Software, System
   Multiple Embedded Systems - IP Cores

May 9, 2001                                                                                                                   10
                   SoC Design Flow
                                                               Hardware Design
                                                EARLY DESIGN   Re-usable IP
                                                               Infrastructure Services


     INSPIRATION



                     POST-SILICON
                      On-Chip Debug IP
                      Synchronized Debugging

                                                                          PRE-SILICON
                                                                      Multi-core Debugging
                                                                      Co-Verification
                                                                      HW Acceleration
              NEW PRODUCTS

May 9, 2001                                                                                   11
              Traditional Waterfall
              ASIC Design Flow
                           Specification Development

                            RTL Code Development

                            Functional Verification

                                   Synthesis

                               Timing Verification

                                Place and Route

                            Prototype Build and Test
                                                                   RMM II, Chapter 2, fig. 2.2

                 Deliver to system integration and software test
May 9, 2001                                                                                      12
              Spiral SoC Design Flow
  Parallel, concurrent development of HW-SW
  Parallel verification and synthesis of modules
  Floorplanning and P&R included in the
   synthesis process
  Planned iteration throughout




May 9, 2001                                         13
                            SoC Verification /
                            Debug Environment
       Driver /                      Driver /
       Control                       Control               Port B                           Test bench
                                        B                                                 Self-stimulating
          A



         Port A                      Test Board
                                                                                                                I/F Bus
                                                                Firmware                  Soft Core            Behavior
                                                                                                                 Model

                                                   8-bit MCU
                                                   Embedded


                                                                                                 SRAM/ROM
                                                                                                   Model
                                     In Circuit Emulator
      IEEE-1284




                                                                           OCI / JTAG
                                                                                                  M8051
                                                                                                 E- Warp
                                                                                        EPP      Debugger    JTAG
      Source Level Debugger Tcl/Tk
        Command Line Interface
May 9, 2001                                                                                                               14
              Choice Processor
              Selection Criteria
  Preserve legacy 8051 investments
       – Tools (off-the-shelf compilers, debuggers)
       – Applications
  8-bit architecture
       – Boost performance
       – Address power consumption issues
       – Address post-integration issues



May 9, 2001                                           15
                 M8051Warp
                 Power/Performance Balance
  In other words,
                                                                                                                                                                                  X6
                                                   50                                                                                           100 MHz M8051Warp Core

   M8051Warp executes
   6X faster than the                              40


   standard part




                                                                                           33 MHz 'Turbo' Part




                                                                                                                                               60 MHz M8051 Core
                                                   30

  Power management

                                          'MIPS'




                                                                                                                 40 MHz 80C51 Part
                                                                                                                                                                                  X3




                                                             12 MHz 80C51 Part
       – Gated clock
                                                   20



              Separate clock controls             10                                                                                                                             X1
                for state machine, CPU,
                Timers and Serial I/F
                                                        10                       20   30                         40                    50      60                  70   80   90        100
                                                                                                                                     Clock Speed (MHz)


May 9, 2001                                                                                                                                                                                  16
                Fully Evolved:
                The M8051E-Warp
                                    The need to test SW on an embedded
                                          core grew in importance:
                                               Post Silicon IP
                                  Debugger system available through
                                   partnership with First Silicon
                                   Solutions (FS2)
                                   – PC (Windows) Based Software
                                   – In-Target System Analyzer provides
                                     interface to PC
                                  On-Chip Instrumentation (OCI)
                M8051E-Warp        designed into M8051E-Warp for test
              In-Circuit Debug     access via JTAG port
                                  Performance and low-power
                                   benefits of the M8051Warp retained
May 9, 2001                                                               17
                    Embedded System
                    Development

              System Design
              Hardware Design
              Prototype Build
              Hardware Debug
              Software Design
              Software Coding
              Software Debug
              Project Complete




May 9, 2001                           18
              Benefits for Software
              Designers
       Embedded Code   Stub Code to Emulate Hardware   HW Simulation




  More time to develop and debug your code
  Validate code against hardware as you develop
  Maintain software design integrity

May 9, 2001                                                            19
              Typical Network Appliance
              Architecture



                Device     uP / uC    Firmware
                 logic
                  and                              I/F
                User I/F

                           Network Transfer Protocol




May 9, 2001                                              20
                  Network Transport
                  Selection - USB 2.0
   Topology
               Tiered Star
               127 connections (max)
               6 Tiers (max)                                             USB

   Bus Transactions
               480 / 12 / 1.5 Mbps
   Configuration
               Dynamic insertion/removal
               Auto configuration                     HUB                     HUB         HOST/HUB
   Physical Layer
               2-wire differential signaling,
                NRZI, bit-stuffing, CMOS               Kbd                 Monitor          PC
                level (3.3V)
               4-pin connector                  Pen         Mouse   Speaker
   High Speed (480 Mbps)                                                            Mic     Phone

               Multi-Media, Video, Storage,
                Broadband Access, Imaging
May 9, 2001                                                                                           21
                USB Focus on Low Cost,
                High Volume Applications
              BANDWIDTH       DEVICE COST APPLICATIONS         ATTRIBUTES          STD FEATURE

              LOW             $5-25       Input Devices        Very Low cost         1997
   USB        10 - 100Kb/s                Control Functions    Ease of Use
                                                               Lots of fanout
    1.1
              FULL          $15-150       Telephony/ Modem     Low cost              1997
              200K - 10Mb/s               Audio, Scanner       Guaranteed latency


    USB       HIGH            $60 - 300   Entertainment, A/V   High Speed            2000+
     2.0      120 - 480Mb/s               Imaging

    1394A
              HIGH            $100-500    Entertainment, A/V   Peer-to-peer          1999
    for CE
              100 - 400Mb/s               Imaging              Multiple channels


    1394B     COMPUTE         $200-500    Primary Disk         Very High bandwidth 1999
    Gigabit   1+ Gb/s                     Home Backbone        Fiber capability


May 9, 2001                                                                                      22
              Inventra USB 2.0 Device
              Demo System and Diagram




May 9, 2001                             23
                 High Speed Function
                 Controller
   USB 2.0 compliant for high/full speed functions
                                                                                               DMA
   Configurable
                                                                                               Add
       – 1 to 16 endpoints                               CONTROL
                                                 (Transaction State Machine)
       – Endpoint Direction
       – FIFO depth
                                                                                               Cntl

   16/32bit VCI-compliant                                                              MCU
                                                                                         I/F
    CPU Interface                                     Packet Enc/Dec
                                    PP
                                                      CRC Gen/Check
   DMA access to FIFOs             H
                            USB Bus MC
                                           Re-                               FIFO
                                                                                               Data

                                     H    Sync                             Controller
   Synchronous Single-             YY
    port RAM interface for
    FIFOs                  Outside of       High Speed Function Controller
                              Soft Core               Soft Core
May 9, 2001                                                                                           24
                  USB High Speed Function
                  Controller - Testbench

                                USBHSFC Testbench Architecture



                                               8/16 Bit
                                    UTMI                  Synthesisable                   BVCI
                                 Transceiver              USB Function      16/32 Bit
                                                                                        Interface
         Host Model   USB Bus
                                  MacroCell               Controller Core                 Model
                                    Model




          Host Data                                         Behavioral                  MCU Data
           Buffers                                            RAM                        Buffers




May 9, 2001                                                                                         27
              USB High Speed Function
              Core - Deliverables
   VHDL or Verilog RTL source code
   Test bench (VHDL or Verilog)
       – Achieves > 99% code coverage
   Example synthesis and scan-test scripts (dc_shell)
       – Targeted an example 0.18 micron technology
       – Fault cover of > 98%
   Simulation scripts (ModelSim)
   Sample Firmware
       – C code generated to match your configuration
   Configuration GUI
   User Guide, Product Spec, Datasheet sheet
May 9, 2001                                              28
                 Designed for Ease of Reuse
  High quality RTL code
  Tested on popular EDA tools
              Mentor Graphics: ModelSim, Leonardo Spectrum
              Synopsys: Design Compiler
              TransEDA: VHDLCover, Verisure
              Cadence: VerilogXL

  VCI complaint CPU Interface
  Configuration GUI


May 9, 2001                                                   29
              Friendly GUI
              Let You Define Your Own USB Parameters




May 9, 2001                                        30
              Gatecount Example
                                               Gatecount Analysis


                              40
                              35
              Area (kgates)




                              30
                              25
                                                                          High Speed
                              20
                              15                                          Full Speed
                              10
                               5
                               0
                                   1   2   4       8     10     13   15
                                           # User Endpoints


      FIFO depths fixed at 64bytes  High Speed: Approx. 1500 gates
      Number of endpoints varied     for each additional endpoint
                                                        Full Speed: Approx. 800 gates
                                                         for each additional endpoint
May 9, 2001                                                                              31
              From SoC to Final Product
               Custom               ROM
                Logic
                          Logic      RAM
              I/O Logic




                                   Embedded
                                     Core
                          Custom




May 9, 2001                                   32
              Xilinx Home
              Networking Forum


  Xilinx selected Inventra USB 2.0 + M8051E-Warp
   cores for Home Networking Reference Design
       – Our cores plus Kawasaki’s UTMI PHY are in two
         Spartan devices
  Press Release on January 29, 2001
  Demonstrated at their Forum during
   February 1,2001
  Additional solutions to follow
May 9, 2001                                              33
         For More information about
         Inventra IP’s USB products,
                 please visit:
              www.mentor.com/inventra
                       and
                   www.usb.org

May 9, 2001                             35

				
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