ELECTRICAL CHARACTERISATION OF THIN SILICON WAFERS AND SOLAR CELLS

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ELECTRICAL CHARACTERISATION OF THIN SILICON WAFERS AND SOLAR CELLS Powered By Docstoc
					ELECTRICAL CHARACTERISATION OF THIN SILICON WAFERS AND SOLAR CELLS AS A FUNCTION OF
                                 INGOT POSITION

                                          A. Lawerenz, M. Bähr and S. Dauwe
        CiS Institut für Mikrosensorik gGmbH, SolarZentrum Erfurt, Konrad-Zuse-Str. 14, D-99099 Erfurt, Germany
                                              e-mail: alawerenz@cismst.de


    ABSTRACT: Multicrystalline silicon wafers of various thicknesses (between 120 and 330 µm) were taken from
    different positions of two ingots and processed to solar cells using an industrial type process. We investigated the
    carrier lifetime in as grown and processed wafers. Whereas as grown wafers from the bottom and top region of the
    ingots have lifetimes much lower than wafers from medium heights, this difference can be eliminated by the solar
    cell process to a large extent. The strong improvement of the carrier lifetime is also reflected by the improvement of
    the carrier lifetime in the border layer close to the crucible walls, whereas the increase of the carrier lifetime in areas
    with high dislocation densities near the bottom of the ingot is small compared to areas with lower dislocation
    densities. The dependence of the open-circuit voltage on wafer thickness and material quality enables an estimation
    of the effective rear surface recombination velocity to be 1600 cm/s.
    Keywords: Recombination, c-Si, Multi-Crystalline


1   INTRODUCTION                                                      concentrated on the open-circuit voltage because this
                                                                      parameter reflects the influence of the material quality to
     The demand for silicon solar cells has recently
                                                                      the solar cell performance best. Additionally we analysed
increased significantly. While the production capacity of
                                                                      the carrier lifetimes of the wafers prior to and after solar
silicon solar modules, cells and wafers has been
                                                                      cell process steps; thereby the effectiveness of the
expanded to meet this demand, that of solar silicon
                                                                      gettering and hydrogen passivation as a function of wafer
feedstock has not grown at the same pace. In order to
                                                                      position could be determined.
damp the shortage of solar silicon, a possible means is to
increase the wafer yield of an ingot. This can be done by
                                                                      2   EXPERIMENTAL
using thinner wafers for the production of solar cells.
     Several groups have investigated the influence of                     From two different multicrystalline boron doped
wafer thickness on solar cell parameters as short-circuit             silicon ingots eight blocks were taken. The topmost and
current, open-circuit voltage and conversion efficiency. It           bottommost parts of these blocks were already cropped
could be confirmed experimentally that with decreasing                prior to wafering. Six blocks from the first ingot were
cell thickness, the efficiency of thinner wafers is to a              sawn by PV Silicon AG into 120, 220 and 330 µm thick
lesser degree affected by the bulk recombination and to a             wafers (for each thickness one central block and one
greater extent by the surface recombination [1, 2]. Also              block adjacent to the former crucible walls); one central
the effect of light-induced degradation is lower in thinner           and one side block of the other ingot was sawn into
cells than in thicker ones [1]. In fact, for thinner cells of a       170 µm thick wafers. From each block, 2 mm thick
comparable low bulk lifetime, cell efficiencies were                  wafers were also sawn at different ingot heights and
found to be higher compared to thicker ones [3]. The                  received a polish etch for further analysis. The wafers are
influence of cell thickness on the open-circuit voltage               156 x 156 mm2 in size and were processed in an
was described by Tool et al [2]. This influence is                    industrial type solar cell process (KOH damage etching,
strongly dependent on the rear surface recombination.                 phosphorus diffusion, amorphous hydrogenated silicon
Theory predicts that the open-circuit voltage is                      nitride antireflection coating, screen printing of a front
decreasing with decreasing cell thickness if the surface              Ag contact grid, an Ag rear bus bar, and Al rear
recombination velocity exceeds a value that depends on                electrode, co-firing). By etching the saw damage, the
the bulk carrier diffusion length.                                    wafer thickness was reduced by 20 µm.
     In case of multicrystalline silicon grown from ingots                 Carrier lifetime measurements using the microwave
there is another important aspect, that is the dependence             detected photoconductance decay (MW-PCD) method
of the cell efficiency on the wafer quality and especially            were performed on the 2 mm thick wafers and on partly
on the wafer position in the ingot. The improvement of                processed thin wafers after the phsoporus diffusion using
the carrier lifetime after phosphorus diffusion processes             the doping profile as a surface passivation. After cell
can be different on wafers from bottom and top regions                processing, we measured carrier diffusion length
[4]. This improvement also depends on different                       topograms of solar cells with the spectrally resolved light
diffusion processes. The position dependent lifetime                  beam induced current (SR-LBIC) method using three
improvement is caused by the different impurity contents              different wavelengths. We removed all contacts and
and their interaction with crystalline defects. Regions               surface layers of some of the solar cells in order to
with higher metal concentrations (present in the edge                 measure the bulk carrier lifetime of the processed cells,
regions and especially in the top region) can be gettered             thereby reducing the wafer thickness of another 20 µm.
by the solar cell process and thus the change of the                  The surface recombination was largely supressed by a
carrier lifetime after the solar cell process is strongly             standard iodine ethanol surface passivation [6].
influenced by the iron content [5].
     This work combines both subjects, the open-circuit
voltage reached on various wafer thicknesses and their
dependence on wafer quality and position. We
                                                                                          9                                                         60

                                                                                          8

                                                                                          7




                                                                                                                                                         Carrier lifetime (µs)
                                                                                          6                                                         40




                                                                  Carrier lifetime (µs)
                                                                                          5

                                                                                          4

                                                                                          3                                                         20

                                                                                          2
                                                                                                                      as grown
                                                                                          1                           after cell processing

                                                                                          0                                                          0
                                                                                              0   10    20     30     40     50      60       70   80
                                                                                                       Distance to edge of the wafer (mm)
a)
                                                              Figure 3: Carrier lifetime profile of a wafer in the
                                                              neighbourhood of the crucible wall before and after cell
                                                              processing.

                                                              3                       RESULTS
                                                              3.1 Comparison of lifetime prior to and after solar cell
                                                              process steps
                                                                   As can be seen in Fig. 1, the carrier lifetime of wafers
                                                              from the bottom region is rather low before cell
                                                              processing (mean value: 0.5 µs). The lifetime is found to
                                                              be higher at the grain boundaries in comparison to the
                                                              bulk of the grains. We attribute this to the gettering of
b)                                                            defects in the vicinity of grain boundaries. After
                                                              phosphorus diffusion, where defects within the total
Figure 1: Lifetime mapping of an as grown, 2 mm thick         sample are gettered, we found a drastic increase of the
wafer (near the bottom of the ingot, a) and a mapping of      carrier lifetime in the bulk of the grains that exceed that
the effective diffusion length of a neighbouring solar cell   of the grain boundaries. A behaviour that is similar to the
(b).                                                          grain boundaries characterizes larger areas, one of which
                                                              is marked by the arrows in Fig. 1. These areas are
                                                              identified as areas with high dislocation densities. The
                                                              improvement of the carrier lifetime values in these areas
                                                              is rather low (for the highlighted area in Fig. 2 the
                                                              lifetime increases from 1.5 µs to 3 µs). For a general
                                                              description of the changes of the carrier lifetime the
                                                              dislocation density has to be taken into account.
                                                                   As grown wafers taken from the edge region of the
                                                              ingot show the impact of the ingot edges on the carrier
                                                              lifetime values due to impurity diffusion from the ingot
                                                              edges (Fig. 2 a). After solar cell processing the carrier
                                                              lifetime of this region improved to the same level as in
                                                              the inner parts of the wafer - except for a very thin region
                                                              adjacent to the ingot edge where the improvement was
                                                              lower (Fig. 2 b). This can be examined in more detail by
a)
                                                              regarding the linescans perpendicular to the wafer edges
                                                              (Fig. 3). We attribute the improvement to a combined
                                                              effect of gettering by the phosporus diffusion and bulk
                                                              passivation by silicon nitride deposition and firing.
                                                              3.2 Lifetime and open-circuit voltage in dependence of
                                                              wafer position and wafer thickness
                                                                   For all blocks and ingot heights the carrier lifetime is
                                                              strongly improved by the solar cell process (Fig. 4). In
                                                              the middle of the block the lifetime increases from about
                                                              6 µs to 30 - 40 µs. The improvement is even more
                                                              pronounced in the bottom and top region, especially in
                                                              the bottom region of the 170 µm thick wafers, where the
                                                              lifetime values attain the same values as in the central
                                                              part of the block. There is also the tendency that the
                                                              relative change of the lifetime is more enhanced in the
b)                                                            bottom region than in the top region.
                                                                   The open-circuit voltage values have a similar
Figure 2: Lifetime mapping of an as grown wafer (a) and       dependence on the ingot height as the lifetime (Fig. 5).
a mapping of the effective diffusion length of a
neighbouring solar cell (b).
                                                                                         45                                          0.620
                                                             Wafer thickness 330 µm                                                                                     Wafer thickness 330 µm
                              10                                                         40
                                                                                                                                     0.615
                                                                                         35
                              8                                                                                                      0.610




                                                                                                Carrier lifetime (µs)
      Carrier lifetime (µs)




                                                                                         30

                                                                                         25




                                                                                                                          Voc (mV)
                                                                                                                                     0.605
                              6
                                                                                         20
                                                                                                                                     0.600
                              4               as grown, near centre of ingot             15
                                              as grown, near edge of ingot                                                           0.595
                                              after diffusion, near centre of ingot      10
                              2                                                                                                                                       centre
                                              after diffusion, near edge of ingot
                                                                                         5                                           0.590                            edge
                                       after cell processing, near centre of ingot
                              0                                                          0
                                   0   20           40           60           80       100                                                   0   20          40           60            80        100
                                            Distance to bottom (arb. units)                                                                           Distance to bottom (arb. units)

                                                                                         45                                          0.620
                                                                                                                                                                         Wafer thickness 220 µm
                                                              Wafer thickness 220 µm     40
                              10                                                                                                     0.615
                                                                                         35
                              8                                                                                                      0.610
                                                                                              Carrier lifetime (µs)
Carrier lifetime (µs)




                                                                                         30

                                                                                         25

                                                                                                                          Voc (mV)
                                                                                                                                     0.605
                              6
                                                                                         20
                                                                                                                                     0.600
                              4                                                          15

                                                                                         10                                          0.595
                              2
                                                                                         5                                           0.590
                              0                                                          0
                                   0   20           40           60           80       100                                                   0   20          40           60            80        100
                                            Distance to bottom (arb. units)                                                                           Distance to bottom (arb. units)

                                                                                         45                                          0.620

                                                              Wafer thickness 170 µm                                                                                     Wafer thickness 170 µm
                              10                                                         40
                                                                                                                                     0.615
                                                                                         35
                              8                                                                                                      0.610
                                                                                         30
     Carrier lifetime (µs)




                                                                                                  Carrier lifetime (µs)




                                                                                         25
                                                                                                                          Voc (mV)




                                                                                                                                     0.605
                              6
                                                                                         20
                                                                                                                                     0.600
                              4                                                          15

                                                                                         10                                          0.595
                              2
                                                                                         5                                           0.590
                              0                                                          0
                                   0   20           40           60           80       100                                                   0   20          40           60            80        100
                                            Distance to bottom (arb. units)                                                                           Distance to bottom (arb. units)

                                                                                         45                                          0.620
                                                              Wafer thickness 120 µm                                                                                  Wafer thickness 120 µm
                              10                                                         40
                                                                                                                                     0.615
                                                                                         35
                              8                                                                                                      0.610
                                                                                              Carrier lifetime (µs)
     Carrier lifetime (µs)




                                                                                         30

                                                                                         25
                                                                                                                          Voc (mV)




                                                                                                                                     0.605
                              6
                                                                                         20
                                                                                                                                     0.600
                              4                                                          15

                                                                                         10                                          0.595
                              2
                                                                                         5                                           0.590
                              0                                                          0
                                   0   20           40           60           80       100                                                   0   20          40           60            80        100
                                            Distance to bottom (arb. units)                                                                           Distance to bottom (arb. units)

Figure 4: Carrier lifetime as a function of wafer position                                                                Figure 5: Open-circuit voltage in dependence of wafer
for the four investigated wafer thicknesses.                                                                              position for the four investigated wafer thicknesses.
                                                                                                                          Centre and edge refer to the position of the block within
                                                                                                                          the ingot.
    A negative slope in the central part of blocks is           values from the MWPCD measurements after cell
clearly visible in the 170 µm wafers and less distinct in       processing for the centre of the blocks (30 µs, s. Fig. 4)
the other ones, which are coming from another ingot. In         and assuming Dn to be 30 cm/s, we get Seff > 1000 cm/s.
the bottom region of the 330 µm wafers the voltage is               For the bottommost wafers where the open-circuit
decreasing towards the bottom. This behaviour is less           voltage is assumed to be constant and where the lifetime
pronounced for the 170 and 120 µm thick solar cells. A          is approximately 16 µs, Seff can thus be estimated to be
discussion of the dependence of the solar cell parameters       1600 cm/s.
on cell thickness and on the Al rear pastes used is
included elsewhere [7].                                         5   CONCLUSION
                                                                    This paper presents the effect of the solar cell process
4   DISCUSSION
                                                                on the carrier lifetime and the open-circuit voltage in
     The lifetime improvement by the phosphorus                 different positions of the ingot and for different cell
diffusion can be very different for bottom and top regions      thicknesses. We could demonstrate that the extent of the
as shown by Riepe et al [4]. In contrast to their results,      border layer in the vicinity of the crucible walls which
where the lifetime improvement is more enhanced in the          has much lower lifetime values than the inner parts of the
top than in the bottom region (s. Fig. 4 and 5 in [4]), this    ingot can greatly be reduced by the solar cell process. A
improvement is in our case more balanced or even more           much lower influence is observed for bottom-near areas
distinct in the bottom region. These variations can be          having high dislocation densities. After the solar cell
attributed to different cell processes and starting material.   process the dependence of the carrier lifetimes on the
     Areas of high dislocation densities have in the central    block height is much lower than before. This is also
parts of multicrystalline ingots in as grown wafers as          reflected in the open-circuit voltage values. From the
well as in solar cells lower diffusion lengths than areas of    influence of the cell thickness on these values an
low dislocation densities. However, this can be different       estimation of the effective surface recombination velocity
in solar cells originating from lower parts of                  could be given.
multicrystalline ingots. For these regions Rinio observed,
that the internal quantum efficiency at 830 nm is               6   ACKNOWLEDGEMENTS
increasing with increasing dislocation density [8]. In our
                                                                    The close cooperation with ErSol Solar Energy AG is
case we find the same behaviour in the as grown wafers.
                                                                highly appreciated. The financial support of the
The reason for the comparably small lifetime
                                                                Bundesministerium für Wirtschaft und Arbeit is
improvement of the areas with high dislocation densities
                                                                gratefully acknowledged.
in the bottom region can be the insufficient gettering
efficiency of defects that are agglomerated at
                                                                7   REFERENCES
dislocations.
     The strong improvement of the carrier lifetime for the     [1] K. A. Münzer, K. T. Holdermann, R. E. Schlosser, S.
edge regions of the ingot is also reflected by the                  Sterk, IEEE Trans. Electron Devices Vol. 46, No 10
reduction of the extent of the side region of the ingots            (1999) 2055.
(Fig. 2). The remaining defects responsible for the low         [2] C. J. J. Tool, A.R. Burgers, P. Manshanden, A.W.
carrier lifetime in the region closest to the crucible walls        Weeber, Proc. 17th European Photovoltaic Solar
can possibly be attributed to metal precipitates. Rinio et          Energy Conference, Munich (2001) 1551.
al found in such a solar cell region of a multicrystalline      [3] D. Kray, H. Kampwerth, E. Schneiderlöchner, A.
ingot iron precipitates that were dissolved and gettered            Grohe, F. J. Kamerewerd, A. Leimenstoll, D.
by the phosphorus diffusion [9]. In our case the                    Osswald, E. Schäffer, S. Seitz, S. Wassie, S. W.
improvement of the carrier lifetimes to the same values             Glunz, G. P. Willeke, Proc. 19th European
as in the inner regions occurs in regions with original             Photovoltaic Solar Energy Conference, Paris (2004)
lifetimes exceeding approximately 1 µs.                             608.
     From Fig. 5 the dependence of Voc on cell thickness        [4] S. Riepe, M. Ghosh, A. Müller, H. Lautenschlager,
can be estimated. For the central part of the blocks Voc            D. Grote, W. Warta, R. Schindler, Proc. 19th
decreases from 604 mV (for 330 µm wafer thickness) to               European Photovoltaic Solar Energy Conference,
approximately 600 mV (for 120 µm wafer thickness).                  Paris (2004) 986.
Because of the large scattering of the Voc values the           [5] L. J. Geerligs, Proc. 3rd World Conference on
dependence on the wafer thickness for the bottom part of            Photovoltaic Energy Conversion, Osaka (2003).
the blocks is less discernible. We estimate this decrease       [6] T. S. Horanyi, T. Pavelka, P. Tütto, Applied Surface
to be less than 4 mV. The open-circuit voltage of both              Science, Vol 63 (1993) 306.
wafer thicknesses (330 and 120 µm) near the bottom is           [7] M. Bähr, S. Dauwe, A. Lawerenz, L. Mittelstädt, this
approximately 597 mV. Wafers with a thickness of 170                conference.
µm are not considered here, because these wafers were           [8] M. Rinio, PhD thesis, TU Bergakademie Freiberg,
taken from another ingot (although the bottommost solar             2004.
cells show a similar decrease in the open-circuit voltage       [9] M. Rinio, C. Ballif, T. Buonassisi, D. Borchert, Proc.
in comparison to the neighbouring cells).                           19th European Photovoltaic Solar Energy
     Tool et al [2] calculated the dependence of the open-          Conference, Paris (2004) 762.
circuit voltage on wafer thickness W and effective rear
surface recombination velocity Seff. Voc is decreasing with
decreasing cell thickness if Seff > Dn / Ln (Dn: minority
carrier diffusion coefficient, Ln: minority carrier diffusion
length for the solar cell base). By taking the lifetime