# Exam 2 Study Questions by fionan

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```									                              Exam 2 Study Questions
Chapters 8, 10-14, Appendices A-B of Nelson’s Text
July 23, 2008

1. Derive the logic for a full adder.

2. Show how to build a two’s compliment, 3-bit adder/subtracter using full adders. Assume the
design has an input called sub that causes it to subtract when 1 and add when 0.

3. Design an unsigned, 4-bit, +1 adder. In other words, design an adder that takes an unsigned,
4-bit input, I[3:0], and outputs a 5-bit number equal to I+1. Note that you should not use a
full adder for this design since it will have unused inputs, and therefore unused logic. (FYI,
the logic slice you should design is called a half adder.)

4. Modify the equation F = A’BC’ + AD + BCD’ so that the logic is hazard free.

5. Can the logic equation F = X’Y + WZ + XZ have false outputs? Why or why not?

6. Which of the following should be used as the worst case delay of a gate: tprop, tprop-rise, or
tprop-fall?

7. Complete the timing diagram on the right based on the gate-level schematic on the left.
Assume the following gate delays: tNAND = 5 ns, tOR = 20 ns, tAND = 10 ns. Indicate if there
are any false outputs.

8. Consider the following equations:

X = ABC + B’D’ + AB’D + C’D’
Y = BC + D’
Z = CD + B’D’ + A’BC

a.) What size PLA is needed to implement these functions, as written? In other words, how
many inputs, outputs, and word lines are necessary?
b.) Modify the equations for X, Y, and Z so that they can be implemented on a PLA that has
6 word lines.
c.) Show the PLA table that would be used to describe this PLA to a CAD tool.

WSF                                         ECEn/CS 224                                      Page 1/5
9. What is bistability? What is its relationship to data storage?

10. Draw (from memory or derive) the schematic for the SR latch and gated D latch.

11. Draw (from memory or derive) the transition table for the SR latch and gated D latch. Do you
understand the meaning of these transition tables?

12. Draw (from memory or derive) the schematic for a rising edge triggered D flip flop, T flip
flop, and JK flip flop.

13. Draw (from memory or derive) the transition table for the rising edge triggered D, T, and JK
flip flops. Do you understand the meaning of these transition tables?

14. Define tsetup, thold, and tCLK-Q.

15. Identify the critical path for tCLK-Q in the schematic for the falling edge triggered D flip flop
in Figure 11.14 of Nelson’s text. What is the equation for the critical path as a function of
tNOT, tAND, and tNOR? What is it for the rising edge triggered D flip flop of Figure 11.17?

16. Identify the critical path for tsetup in the schematic for the falling edge triggered D flip flop of
Figure 11.14 in Nelson’s text. What is the equation for the critical path as a function of tNOT,
tAND, and tNOR? What is it for the rising edge triggered D flip flop of Figure 11.17?

17. Identify the critical path for thold in the schematic for the falling edge triggered D flip flop of
Figure 11.14 in Nelson’s text. What is the equation for the critical path as a function of tNOT,
tAND, and tNOR? What is it for the falling edge triggered flip flop of Figure 11.17?

18. When S is asserted to set an SR latch, which output changes first, Q or Q’? How about when
the flip flop is reset?

19. Complete the timing diagram on the right based on the schematic shown on the left. Assume
the clock frequency is 100 MHz and assume the following delays: tsetup = 1 ns, thold = 0.5 ns,
tCLK-Q = 2.5 ns, tNOT = 1 ns. Additionally, assume Q1 and Q0 are initially 0. Label the
transitions on Q1 and Q0 with the time at which they occur, assuming the diagram starts at
time 0 ns.

WSF                                          ECEn/CS 224                                       Page 2/5
20. Why is it considered bad practice to gate the clock of a flip flop? What’s an accepted
alternative?

21. Design a 4-bit register that can shift left by one bit, shift right by two bits, invert its contents,
and load a new value (respectively, ctrl = 00, 01, 10, 11). Provide a shift_in input and a
shift_out output for use when left shifting. When right shifting, the register should shift in
zeros and the shift out should be ignored.

22. Design a 3-bit counter that counts in the sequence 101, 010, 000, 111, 101… Choose flip
flops with the appropriate control signals so that a single reset signal causes the counter to
load the initial value 101. Draw the gate-level schematic of the resulting circuit.

23. Repeat the previous problem with T flip flops then with JK flip flops. For this problem, just
give the next state equations in minimum sum of products form.

24. Design a counter, with an inc input, that counts in the sequence 00, 01, 00, 10, 00… This is
tricky because this counter appears to give the same value twice in the count sequence.

25. Which of the following do we usually care about: minimum period, maximum period,
minimum frequency, or maximum frequency?

26. What is the period of a 20 MHz clock? Give your answer in ns, and solve the problem
without a calculator.

27. Suppose you are using flip flops with a setup time of 2 ns, a hold time of 0.5 ns, and a clock-
to-Q time of 1 ns. What is the longest possible critical path in the input forming logic of a
state machine that will allow for a maximum clock rate of 200 MHz?

28. The diagram below shows a counter with outputs driving a 4-bit register. Assume that the
critical path for the input forming logic of the counter is 4 ns, the critical path for the output
forming logic is 6 ns, tsetup is 3 ns, and tCLK-Q is 2 ns. What is the maximum operating
frequency of the circuit shown below?

4

IFL         4                 4       OFL         4                4
D    Q                                D    Q

CLK

29. What is the equation for the delay between the clock edge and a Moore output of a counter
changing?

WSF                                          ECEn/CS 224                                        Page 3/5
30. Design a 2-bit gray code counter (i.e., having the sequence 00, 01, 11, 10, 00…) with clr, set,
and inc inputs. Make clr the highest priority, followed by set and inc. The clr input should
cause the counter to load zeros, the set input should cause the counter to load ones, and the
inc input should cause the counter to transition to the next sequential gray code value.

31. Add two outputs to the counter of the previous problem. The max output should be high
when the count value is 10. The roll output should be one when the counter is about to roll
over from 10 to 00. What kind of outputs are roll and max (Moore or Mealy)?

32. Assuming the asynchronous RESET signal is asserted briefly before the clock begins to
oscillate, what is the count sequence output on A B C for the circuit shown below. Note that
the RESET signal is connected to asynchronous SET inputs on these flip flops.

33. Consider the following transition table:

IN      Q1      Q0       N1      N0       X       Y
0      0       0        0       1        1       1
0      0       1        1       1        1       1
0      1       0        0       0        0       0
0      1       1        1       0        0       0
1      0       0        1       0        0       1
1      0       1        0       0        0       1
1      1       0        1       1        1       0
1      1       1        0       1        1       0

Is X a Mealy or a Moore outputs? How about Y?

WSF                                       ECEn/CS 224                                     Page 4/5
34. What does the following Verilog module do?

module mystery(r, a);
parameter IW = 16, OW = 32;
input [IW-1:0] a;
output [OW-1:0] r;

wire [OW-1:0] al;

assign al = {{(OW-IW){a[IW-1]}} , a};

assign r = (al << 2) + (al << 1) + al;
endmodule

35. What does the following Verilog module do?

module mystery(f, i);
parameter N = 4;
input [N-1:0] i;
output [(1<<N)-1:0] f;

assign f = 1 << i;
endmodule

36. If a has the value 2’b10 and b has the value 2’b01, what does the following Verilog
expression evaluate to? How many bits wide is the result?

a + b>>1?{2'b01,a}^{b,b}&3 + 6 : {2{a % b-1}}

37. What does the following Verilog module do? What are the common names for the v, w, x, y,
and z signals?

module mystery(v, w, x, y, z);
input v, w, x, y;
output reg z;

always @(posedge v)
begin
if(w == 1’b1)
z <= 1’b0;
else if(x == 1’b1)
z <= y;
end
endmodule

WSF                                      ECEn/CS 224                                      Page 5/5

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