Driving the DSL highway high speed, high density, low by unj14631


									ESSCIRC 2002

        Driving the DSL highway : high speed, high density, low power, low cost.

                                       Jan Sevenhans*, IEEE Fellow

                               Wim De Wilde*, Elve Moons*, Peter Reusens*,

                      Laurent Berti*, Lajos Kiss*, Herman Casier**, Georges Gielen***

                  *     Alcatel BND, Francis Wellesplein 1, B2018 Antwerpen, Belgium

               ** Alcatel Microelectronics, Westerring 15, B9700 Oudenaarde, Belgium

           *** K.U.Leuven,ESAT-MICAS, Kasteelpark Arenberg 10, B3001 Leuven, Belgium

   Abstract                                              Telecommunication companies have now
                                                         developed high-speed wireline connections
   DSL is in deployment for a few years, but             such as ADSL which today are full
   what is next? The broadband market is                 deployed. Looking ahead on the need for
   open for the home user, but what can we               speed generated by the offering of more
   do on the silicon integration level to make           extensive services such as multiple real-
   it cheaper? What are the bottlenecks today            time video channels combined with Voice
   to make it more power efficient and reduce            over Internet Protocol (VoIP) and more in
   the hardware size, on the central office side         general Voice over Broadband (VoB), more
   (CO) and the customer premises side                   generally referred to as Voice over Packet
   (CPE). Which new technologies do we                   (VoP), the development of the next
   need to further increase performance and              generations of wireline communication
   density of CO lines per board and reduce              such as VDSL (Very high speed Digital
   the power dissipation per rack? How do                Subscriber Loop) is now ongoing. The wide
   we tailor the DSL product to the user                 spread of ADSL was long time hampered
   categories? Can we make DSL a success                 by the absence of affordable solutions for
   for a century, like the plain old telephone           the modems. Up to the end of 1999 only
   system (POTS)? These are all questions in             600000 lines were installed over a three-
   the minds of telecom analog and digital               year time span, but this has grown by an
   ASIC and system designers. In this paper              order of magnitude in 2000. Despite the
   we may not give all the answers, but at               low economy in 2001, the installed base
   least we point out the trends in silicon              was at around 18 million lines by the year
   integration for future-safe DSL products,             end. Longer-term expectations range up to
   mainly focussing on analog front-end                  100 million lines for 2005, be it ADSL or
   driver issues.                                        VDSL.

   Introduction                                          New hardware requirements

    The DSL product is justified by today’s              ADSL uses 1 MHz on the copper twisted
   high-speed internet access for every home.            pair today to allow up to 8 Mbit/s data rate
   The internet and its related service is part          in a DMT code signal. In the next few
   of each citizen’s life, not to mention the            years the DSL roadmap is showing us
   economical     and      industrial  impact.           ADSL+ and ADSL++ up to VDSL (see
   Affordable high-speed networking is of                figure 1) with more down and upstream
   major concern for every community.                    bitrate tailored to different user profiles.

      The internet surfer wants more downstream         Going to any next generation of wireline
      for downloading data. The home worker             communication (ADSL+, VDSL…) requires
      wants a link for symmetrical up and down          CMOS data converters with an increasing
      stream data from and to the system in the         sampling rate that stretches from several
      company. Multi-channel video is mainly            MHz up to 17.6 MHz or even 35.2 MHz or
      downstream bandwidth (25 – 50 Mbit/s              70.4 MHz, with resolutions of 12 to 14 bit
      over copper twisted pair) but a camera in         (see figure 1 as well). For this range of
      the living room will enable virtual family        applications, pipelined converters (with or
      visits on the home TV like we have                without calibration) are typically used for
      conference calls replacing professional           the A/D conversion and current-steering
      meetings today. The next-generation ADSL          D/A converters are used for the D/A
      chip set should anticipate this for the reuse     conversion. For every new generation of
      of hardware on the physical layer. All these      xDSL the specifications are slightly different
      applications and user profiles demand a           (mostly     higher    bandwidths,      similar
      reconfigurable flexible interface in the last     resolution), but the same converter
      mile of the network to avoid operational          architecture can typically still be used after
      cost adders to reconfigure the network on         proper new sizing, thanks to the progress
      the user side each time a user changes his        in the CMOS technology. However, this
      mind      about    his    connection.      Soft   fast progress in technology also requires
      reconfigurability from the central office         the regular porting of designs, even within
      location will allow to give the right             the same xDSL generation, to more
      bandwidth to the right user at the right time     advanced CMOS processes, as this reduces
      and the right cost. In the digital data pump      the cost (because of the smaller digital
      the move from dedicated hardware to               part). The large effort to create the analog
      reconfigurable processors is already              converter designs and layouts for all these
      established. For the analog front-end,            different applications and technology
      reconfigurabillity is as important for a          processes is a huge effort for analog
      future-safe product. One advantage of             designers, not to speak of the shortage in
      xDSL (ADSL, VDSL, …) versus e.g. cable            good analog designers.
      modems is the twisted-pair copperline
      exclusive for each customer up to the CO,         New design tool requirements
      but the upgrade cost involved with every
      future version of xDSL (e.g. ADSL, ADSL+,         All this therefore calls for the reuse of
      ADSL++, VDSL…) (see figure 1) may                 analog design knowledge as soft IP. Note
      prevent the operators from following these        that analog hard IP reuse is very unlikely
      upgrades. We have to allow telecom                due to the strong technology dependence
      companies to leverage on infrastructure           of analog circuit performance. Fortunately,
      investments. So, it is crucial to come to a       universities have demonstrated in the
      soft-reconfigurable future-safe front-end,        recent past that a tool-box approach can
      implying compatibillity for different versions    be developed to systematically generate for
      of xDSL (e.g. ADSL, ADSL+, ADSL++,                instance current-steering D/A converters
      VDSL) through reconfiguration by software,        with a factor up to 3x gain in design time
      all with the same flexible hardware.              and effort [1].

         ADSL                                           This experience in university labs provides
                     ADSL+                              the baseline to believe that similar gain in
                                 ADSL++                 design time and cost can be achieved in an
                                            VDSL        industrial design environment, as soon as
                                                        the analog soft IP generation and reuse
        1.1 MHz 2.2 MHz 4.4 MHz 8.8MHz                  methodology will be extended to A/D
                                                        converters and incluced in the design flow
      Figure 1 DSL product roadmap                      and design kits for foundry technologies.

Low-power line driver requirements

The discrete multi-tone (DMT) code is a         Vin                             Vout
golden gate on copper cable but leaves the
system with a power bottleneck in the line
drivers because of the high crest factor.                                    High & Low
Class A/B drivers are still used in ADSL                                     supply
products but will soon be replaced with
Class G, Class H, Class K and other high-
efficiency power amp concepts. We re-
invent the future driver architectures as we
go back and remember the audio low-             Low to high supply switch control
power, high-efficiency concepts. But the
boundary conditions for DSL are more            Figure 2 : 4-supply Class G line driver
complicated.      The extras are : line         architecture
termination, echo canceling and duplex
signaling. These additional functional
issues make the difference and prevent us
from just copying the audio low-power
topologies. But especially the high peak to      Vin                              Vout
average ratio (PAR) and the high linearity
requirements of the quadrature amplitude
modulation in the DMT signal code make it
hard to implement all these well known
                                                                               Low supply
low-power concepts. We can divide these
topologies in 3 categories: linear, switching
mode and combined architectures using a
switching mode for the high power
efficiency in the signal and a linear            Low to high supply switch control and
correction amplifier to achieve the high         capacitive voltage doubler
linearity requirement [2].

Linear low-power driver design starts           Figure 3 : 2-supply Class G/Class H line
with minimum quiescent current class A/B.       driver with capacitive voltage doubler
This may look obvious, but not evident if
you observe the class A/B drivers on the        In Class H, not switches but linear circuits
market today. They consume 1.5 to 2 W           push the supply up to follow the ouput
for a 100mW signal on the line. ADSL            signal shape gradually.
class A/B drivers with 700mW dissipation
on a 100mW CO line were first published         One reason why class G , H and A/B line
at ISSCC2002 [3-5]. A class H (figure 3)        drivers reported are now all in the 600 to
solution from the same brand in the same        700mW range is because of the passive
session is at about the same power              line termination resistors. The dissipation
although you expect better efficiency from      in these resistors can be reduced by using
a class H or G (figure 2) running at half       impedance synthesis. It was applied in
supply and only switching to a higher           subscriber line circuits (SLICS) for plain old
(double or triple, depending on the circuit)    telephone (POTS) for decades, using the
voltage because a peak in the DMT signal        “Herter” bridge and the RX sense amplifier
takes only a few microseconds, only once        in a loop over the line drivers (see figure
in a millisecond. So the voltage doubling       4). In ADSL the “Herter” bridge is reduced
takes only 2 caps and 2 switches in a class     to 4 resistors, cleverly sized to eliminate the
G driver.                                       sense amplifier, a novel idea, widely used.

                                                                 The choice between the class G and class
                                                        A-wire   H     is   mainly     driven   by   design
              Line Driver                                        considerations, the efficiency of the two
                                                                 architectures being identical.

                                                                 For the next ADSL generation, we need at
RX Sense Amplifier                                               least 80 dB for the MTPR (Missing Tone
                                                                 Power Ratio). So for a class G the output
                                                                 stage requires very high PSRR (Power
                                                                 Supply Rejection Ratio), due to the abrupt
                                                                 supply changes, but the design of the
              Line Driver
                                                                 supply switch is easier.
                                                                 For a class H amplifier, we can reduce the
                                                                 PSRR by a good strategy on the power
                                                                 supply switching. The transition of the
       Figure 4 Impedance synthesis loop using
                                                                 power supply is more progressive.
       the resistive “Herter” bridge in POTS
                                                                 So the two architectures are equally
                                                                 efficient, but the challenge for the designer
                                                                 is not situated on the same part of the
       Line Driver                                      A-wire
                                                                 For further improving the efficiency in
                                     Line Transformer

                                                                 linear line driver amps, we can think about
                                                                 the class BAB and Class GAB circuits. In
                                                                 these configurations (see figure 6) the low-
                                                                 voltage power amplifier (the “beast” as our
                                                                 designers call it) is clipping on the DMT
                                                                 crest peaks but drives the 100mW power to
       Line Driver                                               the line with 78.5% (π/4) maximum class B
                                                                 power effiency. This (π/4)       is    for a
                                                                 sinewave signal without passive line
                                                                 termination. In addition a double- supply-
       Figure 5 Active Back Termination (ABT) of a               voltage,     low-current    signal-correction
       differential line driver topology                         peak-amplifier (the “beauty”) in class A/B is
                                                                 correcting the clipping and the crossover
       The circuit in figure 5 is called ABT or                  errors of the class B low-voltage, high-
       “active back termination”.                                efficiency rms-amplifier.
       Using both ABT and Class G or H drivers                   The high-supply class A/B drivers do the
       reduces the dissipation in a 100mW ADSL                   impedance synthesis on the line in the ABT
       CO line driver to about 500mW for a 6.4x                  topology of figure 6 and in the mean time
       crest factor or peak to average ratio (PAR)               correct the clipping of the crest peaks and
       of the DMT line signal.                                   the crossover according to equation 1 :
       Linear circuits can achieve 20% power                     Vwire /N = Vdac- Iline x Zco   (equation 1)
       efficiency in the near future for ADSL CO
       lines delivering 100mW to the 100Ω line.                  where Zco is the central office impedance
       This is already a factor of 4 better than                 (100Ω), Iline the signal current in the line,
       what we see in the products today with                    Vdac the transmit signal to the line and Vwire
       class A/B amplifiers.                                     the voltage on the line.

                                                                             Audio amplifiers have used switching
                                                                            techniques,     switching-mode     voltage
                                                                            regulators also, but again the extras (line
       RMS-driver                                                           termination, echo cancelling and duplex
                              Zpower                                        signaling) are giving analog designers a
  Peak-driver                                                               new challenge to extend the use of “power
                                                                            DAC” and “Σ∆” to ADSL line drivers.

                                            Line Transformer 1:N
                High                                                        The     SOPA      concept    published     by
                supply                                                      K.U.Leuven [6] is a promising concept, but
                                                                            for the Σ∆ SLD the power figure needs to
                                                                            be considered differently : the SOPA still

                                                                            needs a linear digital to analog converter
                                                                            (DAC) and in the Σ∆ SLD the DAC function
                High                                                        is included in the SLD. But the SOPA allows
                supply                                                      for analog feedback impedance synthesis.
                                                                   B-wire   To achieve in the Σ∆ SLD the high linearity
                                                                            figures of 80 dB MTPR (Missing Tone Power
                                                                            Ratio, a measure for the spectral regrowth
                             Zpower                                         in a suppressed carrier bandwidth), the
       RMS-driver                                                           order of the Σ∆ SLD must go up to 5th or 6th
                                                                            for single bit. Multi-bit Σ∆ SLD is not as
                                                                            convenient here. To reduce the order of
                                                                            the Σ∆ SLD, the switching driver can be
                                                                            combined with a linear stage to correct the
         Figure 6 Class BAB high-efficiency linear                          quantisation errors of the Σ∆ , just like the
         line driver ( the “beauty” and the “beast”)                        correction of the class B distortion in the
                                                                            schematic of figure 6. The rough power
         Equation 1 says : 1) the line impedance is
                                                                            source, SOPA or SLD or class B as shown
         synthesised for 100Ω, and 2) the signal on                         in figure 7 delivers the RMS power to the
         the wires of the line is compared with the                         line via the series impedance Zpower. The
         Vdac input signal and the clipping and                             correction amplifier with open-loop gain A
         crossover errors of the high-efficiency class                      provides the accuracy to the signal on the
         B/G power amp are suppressed by the                                line and it is the loop gain of the active
         loop gain of the high-voltage low-current                          back termination        (ABT)    loop    that
         class A/B driver. This is explicitly shown in                      suppresses the quantisation noise of the
         figure 7 for a simplified single-ended
                                                                            Σ∆ SLD or the distortion of the Class B or
         model. The low-supply class B drivers
                                                                            SOPA line driver.
         deliver the 20 dBm power with high
         efficiency via a resistor feeding into the                         We also find in the audio applications, the
         “Herter” or “ABT” bridge on the output                             class K [5] linear driver with switching
         node of the high-voltage low-power class                           current boosting (figure 8). The difference
         A/B amplifier who delivers only the –20dB                          is : in the class DAB system of figure 7, the
         or lower correction of the crossover and the                       Σ∆ SLD section operates on its fixed pulse
         clipping with a low class A/B efficiency. To                       density (PDM) switching pattern and the
         further reduce the power in the class                              peak driver only adds the quantisation or
         BAB/GAB amplifier, a second ABT loop can                           error signal while in Class K the switching
         be organised over the low supply driver to                         Class D section operates asynchronously to
         divide down the loss in the resistor Zpower.                       keep the linear driver current low . The
                                                                            hysteresis in the comparator on the series
         Switching line drivers          (SLD) are
                                                                            resistor Rs in figure 8 is setting the
         tempting for the well known high efficiency
                                                                            maximum linear current contribution.
         of switching-mode systems in general.

                                                                                                                              Vdd          Vss

             Sopa or SLD                                                                2.Vdac
             or Class B

                                                                 Zpower + Zabt = Zco

                                            +                                                                                        Σ
                                    VLine       -                Vcor


                                       k.ZZco             k.Zabt
              + -                                         ILine x ZABT                           Figure 8 : Class K driver, high efficiency
                                                -                                                combined linear and switching mode.
                VSense = Iline x ZCO                                                   Zabt
                                                                                                 Lines per             24    48     72      96   120
                                       k.ZZco             k.Zabt                                 500cm2 board

                                                                                                 line   (mW)         1230   615     410    307   246
           2VRX                             -             K.Zabt
                                                                                                 driver (mW)         1080   465     260    157   96
         Active Hybrid LNA
                                                    VTX+ VRX                                     Table 1 NEBS maximum power
      VTX = Vdac – Iline . Zco
                                                                                                 The major power consumer in the ADSL
      Vcor = VRX . (Zpower/(Zpower+Zabt)                                                         modem is the line driver (> 80% of the
                                                                                                 power per line in current ADSL). In the
                          +2Vdac - Zpower. ILine                                                 future the part of the line excluding the
                                                                                                 driver but including the ATM processing
      Figure 7 : Switching driver with linear                                                    hardware will dissipate 150 mW. On the
      correction (SDLC), single-ended schematic                                                  other hand we are interested to satisfy the
                                                                                                 NEBS power requirements to allow us to
      Each of the discussed line driver                                                          fill the full DSLAM in all cases. Then we
      architectures will gradually find its way                                                  get at a requirement of 30 W for the
      from design and research to production.                                                    board. This is shown in table 1. In table 2
      In the next coming years of this decade in                                                 we rank the driver concepts of the open
      the continued ADSL product life cycle,                                                     literature for efficiency and for NEBS
      depending on the power efficiency we can                                                   compliance.
      put more ADSL lines on a line card.
                                                                                                 Another question: “Are these high densities
      The ADSL product proceeds in the                                                           realistic ?”. There are physical constraints
      roadmap from 24 to 48 and 72 to 96 lines                                                   popping up, like the minimum space for
      per board. To limit cost, we integrate as                                                  the transformer and protection distances or
      many lines on a board as possible. The                                                     minimum component dimensions required
      affordable total dissipation of the board is                                               for layout.
      constant. So the allowed power per line
      decreases as we integrate more lines per                                                   The receiver (RX) trade-off is also
      PCB.                                                                                       impacting the circuit topology options and
                                                                                                 the chip partitioning in high- and low-
                                                                                                 voltage analog front-end split up.

Lines per                                         The same factor of N is lost on the receive




500cm2 board                                      level. So in 5V CMOS it was obvious to
                                                  filter down the signal in the POTS-splitter
Class AB *                                        and further in the downstream echo filter to
PAR=6.4                            NOT            allow the use of only CMOS for the ADSL
740mW                                             receiver circuitry and a 1:2 transformer
                                   NEBS           ratio was convenient for both RX and TX
 Class AB *                                       circuitry. But in deep submicron CMOS the
                                   COM            supply voltage goes down towards 1V and
 PAR =4.7
 500mW                                            clearly ADSL ASIC design is facing a new
                                                  challenge : build extreme low-noise CMOS
                                   ANT            receivers and use a 1/10 line transformer
 Class G *
 400mW                                            or integrate the receiver, for a much easier
                                                  noise figure, in the high-voltage technology
 SLD                                              with the line driver and go towards a 1:1
 200mW                                            transformer or transformerless …. Active
                       NEBS                       back termination also reduces the RX
 SOPA                                             sensitivity, so forcing us to abandon the 4-
                        COMPLIANT                 resistor hybrid (figure 9) for the active RX
                                                  echo-cancelling low-noise amplifier as
              * = Proven in ADSL                  shown in figure 7.       ABT to reduce the
                                                  power in the line drivers is reducing the
Tabel 2 NEBS Compliance is hard to get            receiver sensitivity : each dB of power
for different line driver concepts                saving is costing a dB on the RX noise. So
                                                  we must move the RX front-end to the high-
The pitfall is that 100mW on a 100Ω line is       voltage chip to join the drivers. And for
3Vrms and with a crest factor or PAR of           multi-channel per chip integration we
6.4x this results in 40V peak to peak on the      benefit from the BCD on SOI techno
line. But on a short line you get 8Vpeak RX       becoming available from a multitude of
signal summed up with the TX signal on the        suppliers. BCD on SOI will help us to meet
duplex line. The hybrid splits the RX signal.     the interchannel isolation specs .     Using
                                                  BCD technology for both ADSL RX and TX
                                                  circuitry allows us to move the transformer
             Vd        ZCO/2
                                                  compromis        back to 1:1 and maybr
                                         VTX      suppress the transformer completely if the
                  2R          R
        =2VTX                                     BCD technology meets the max. ratings of
        RX-signal                                 the line voltage. This brings the TX supply
                                                  requirement up to 20V … 25V depending
          Vd                                      on the PAR spec. and depending on the
                  2R          R          VTX      DSLAM manufacturer the latter can vary
          =2VTX        ZCO/2                      from 4.7x to 6.4x. But the active hybrid of
                                                  figure 7 has by definition a fixed gain of 2
Figure 9: Traditional 4-resistor hybrid           on the RX signal which is beneficial on the
                                                  noise figure but requires a supply range of
But in the 4-resistor hybrid (see figure 9)
                                                  16V to 25V for the 1:1 active receiver,
the line never matches the Zco , and the
                                                  again in direct relation to the PAR. But
R/2R in the hybrid requires Zco=Zline to get
                                                  one trend is clear: deep submicron CMOS
VTX/R = Vd/2R in order to cancel VTX in the
                                                  is pushing the ADSL front-end designers to
RX-signal to relax the range of the ADC.
                                                  move the integration of the RX interface
The near-end echo or the transhybrid loss
                                                  (LNA, filters, ADC…) from the low-voltage
gives +/- 10V on the RX input unless you
                                                  CMOS to the BCD high-voltage chip that
use a 1:N transformer multipliyng the TX
                                                  contains already the line driver.
signal by N from the line driver to the line.

      Passive echo filters are gradually replaced         The DSL product is still young and growing
      by integrated low-pass filters on the              to boom soon as the market recovers. A
      upstream ADSL receivers.            This leaves    roadmap of new generations of ADSL and
      us with the issue of vertical or horizontal        VDSL chip sets is challenging the ASIC
      integration. Horizontal from the line to the       design and technology communities for the
      digital interface or vertical with multi-          deepest submicron multi-channel data
      channel      separate      high-voltage     line   pump integration with the lowest power
      interface     chips      and     multi-channel     multi-channel     analog      line   interface
      ADC/DAC functions with digital channel             integration for minimum cost and
      multiplexer and demultiplexer to keep the          maximum density in the race from 24 lines
      bit rate acceptable on the multi-channel           on a board today towards 72…96 in the
      serial link. 35 to 70 MHz are still easy           coming years. Two things are clear: the
      without requiring link synchronisation and         progress in BCD technology will determine
      phase alignment on this bi-directional link.       the success of the different options that are
      Few companies have integrated the                  open     today,    and      eliminating    the
      complete ADSL analog line function                 transformer (the biggest component in the
      because you need a 30V BCD technology              ADSL line circuit) is also in the wishlist of
      for the line driver and the active hybrid          every ADSL system designer.
      receiver in combination with a deep
      submicron analog CMOS for the digital              Acknowledgement : The authors thank
      interface and DAC/ADC functions. There is          the speakers of the “Analogue Telecom
      also the push towards 0.13µm…0.10µm                Acces Circuits & Concepts” Workshop at
      CMOS to benefit from the 300mm wafer               ISSCC2002 for the inspiring talks on DSL
      discontinuous cost benefit as a result of the      circuits.
      step in wafer size. For this reason we see
      now the BCD transceivers appearing with a          References
      deep submicron multi-channel ADC/DAC
                                                         [1] J. Vandenbussche, G. Van der Plas, W. Daems,
      chip in a tandem chip set for 8, 12 or 16          A. Van Den Bosch, G. Gielen, M. Steyaert, W.
      multi-channel analog front-ends on the 24-         Sansen, “Systematic design of high-accuracy current-
      lines and the 48-lines per PCB product             steering D/A converter macrocells for integrated VLSI
      generations. After that we can reconsider          systems,” IEEE Transactions on Circuits and Systems,
                                                         part II: Analog and Digital Signal Processing, Vol.
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                                                         48, No. 3, pp. 300-309, March 2001.
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      as soon as we have 0.13µm 30V low-cost             linear techniques,” IEEE JSSC July 1999, p. 985-989.
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                                                         Adaptive Supply Full Rate CO Driver,” proc. ISSCC
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                                                         ISSCC 2002, pp. 322.
      Conclusion                                         [5] N.-S. Jung et al., “A new high efficiency and
                                                         super fidelity Analog Audio Amplifier with the aid of
                                                         digital switching amplifier : Class K amplifier,” IEEE ,
      Telecom pushes the silicon techno again            pp. 457 to 46.
      with the ADSL chip sets. This time it is the       [6] T. Piessens , M. Steyaert, “SOPA : A high-
      high-voltage BCD-CMOS, 10 years ago it             efficiency line driver in 0.35mm CMOS using a self-
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      RF-CMOS technology and design for GSM              [7] M. Cresi et al., “An ADSL Central office Analog
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      silicon industry is now making more money          [8] D. Rossi, “Scalable ‘High voltage’ integrated
                                                         circuit design for XDSL type of applications,” proc.
      in telecom applications than in chips for          AACD workshop 2001.
      personal computers. The crossover point
      was in 2001.


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