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SiP Technology and Testing
Presentation to GDR SoC/SiP Testing
Name: Philippe Cauvet
Date: 2006, December 19
Outline
• Definition
• Market / Applications
• Design and technology
• Packaging Technologies
• Test Challenges
• Conclusion
CONFIDENTIAL 2
GDR, PhC, Dec 19, 2006
What is a SiP?
CONFIDENTIAL 3
GDR, PhC, Dec 19, 2006
SiP (System-in-Package) is a functional system or
subsystem assembled into a single package
– Contains one or more die
– Typically combined with other components such as passives, filters,
antennas, and/or mechanical parts
– Components are mounted together on a substrate to create a
customized, highly integrated product for a specific application
– Die may be stacked, but stacking is not required
SiPs may utilize a combination of advanced
packaging including
– Bare die (wire bond or flip chip)
– Wafer level packages
– Pre-packaged die such as CSP
– Stacked packages
– Stacked die
CONFIDENTIAL 4
GDR, PhC, Dec 19, 2006
Outline
• Definition
• Market / Applications
• Design Perspectives
• Packaging Technologies
• Test Challenges
• Conclusion
CONFIDENTIAL 5
GDR, PhC, Dec 19, 2006
Market Trends
Why a slowdown ?
Industry moves to SiP Missing CAD tools certainly an obstacle
Source: Gartner 1Q06
SiP Market Projection
12 000 12 000
10 000 10 000
CAGR 04-10
8 000
10% 8 000
Automotive
Mu Shipment
Communications
6 000 6 000 Consumer
Data Processing
Industrial
4 000 4 000
2 000 2 000
0 0
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
Gartner updates every quarter its SiP Market Projection
Gartner view slightly increased since 3Q04 with 10% CAGR 04-09
compared to 5% CAGR 04-09 for Semiconductors: SiP and SoC grow in parallel!
Gartner sees as much SiP in Consumer as Communication
CONFIDENTIAL 6
GDR, PhC, Dec 19, 2006
Applications
Leading Applications for SiPs
• Applications include portable consumer products such as
digital camcorders and cameras
• Mobile phone is the volume driver
– Logic and memory combo
– Digital baseband section
– Transceiver section
– RF section
CONFIDENTIAL 7
GDR, PhC, Dec 19, 2006
Applications
MCPs show up in other portable devices
CONFIDENTIAL 8
GDR, PhC, Dec 19, 2006
Applications
Motorola E1000 UMTS (3G)
CONFIDENTIAL 9
GDR, PhC, Dec 19, 2006
Applications (NXP)
CONFIDENTIAL 10
GDR, PhC, Dec 19, 2006
Applications (NXP)
CONFIDENTIAL 11
GDR, PhC, Dec 19, 2006
Applications (NXP)
Bluetooth
Radio
CONFIDENTIAL 12
GDR, PhC, Dec 19, 2006
Outline
• Definition
• Market / Applications
• Design Perspectives
• Packaging Technologies
• Test Challenges
• Conclusion
CONFIDENTIAL 13
GDR, PhC, Dec 19, 2006
SiP vs SoC (1)
Single piece of silicon
SoC Single technology
Single level of interconnection
Multiple chips
Multiple technologies
Multiple levels of SiP
interconnection…
…and 3D
CONFIDENTIAL 14
GDR, PhC, Dec 19, 2006
SiP vs SoC (2)
Low High
Production Volume
Simple High
Factors to Consider:
Favor the use
of SoC. Production Volume
Consider Factors Design Environment
Carefully. Dev Cost (Incl. IP Cost)
Reliability
Die Maturity
Technologies (RF, Memories…)
Technical Performance /
Mix Speed
Favor the use
+
of SiP.
Consider Factors
Carefully. Market Environment
Complex Low
Source: Gartner 2006
Time to Market Contibutor: JM Yannou, NXP SiP
Short Long
Innovation Manager
CONFIDENTIAL 15
GDR, PhC, Dec 19, 2006
Focus on EMC (and SiP): new challenges
non SiP system SiP
Components placement is done Components placement is done at the
empirically after circuits design same time as circuits design:
predictability needed!
?
system goes 3D! + components are
closer to each other!
3D EM CAD of SiP required for speed to market and performance!
?
CONFIDENTIAL 16
GDR, PhC, Dec 19, 2006
Example of an inter-system (inter SiP in susceptibility) EMC challenge
TV:
up to 862MHz
GSM:
from 890MHz on
The GSM antenna emits signals considered as noise by the close-by low-amplitude
large-bandwidth TV RF receiving subsystem
CONFIDENTIAL 17
GDR, PhC, Dec 19, 2006
intra-SiP EM emissivity: simultaneous switching noise (SSN)
Disruptive digital
circuit
Hindered
Decoupling capacitors analogue circuit
integrated in silicon (Philips (EMI by SSN
PICS technology), flip-chip inductively
bumped on digital: -16dB coupled to the
noise reduction measured! analogue power
supply)
New opportunity to make robust systems with high power integrity thanks to the
integration of decoupling capacitors.
Associated (new) requirement: guarantee power integrity and optimize power routing
and decoupling components values and placement by simulation (new w.r.t. SoC)
CONFIDENTIAL 18
GDR, PhC, Dec 19, 2006
Outline
• Definition
• Market / Applications
• Design Perspectives
• Packaging Technologies
• Test Challenges
• Conclusion
CONFIDENTIAL 19
GDR, PhC, Dec 19, 2006
SiP vs SoC
CONFIDENTIAL 20
GDR, PhC, Dec 19, 2006
Packaging challenges
• Higher integration requires smaller chips, with smaller pad
pitch and size
• More chips = thinner chips (how to handle <100µm
wafers?)
• More functionalities = more power
• Cost of materials
CONFIDENTIAL 21
GDR, PhC, Dec 19, 2006
Packaging
Source: STATSChippac
CONFIDENTIAL 22
GDR, PhC, Dec 19, 2006
Packaging
Source: DPC
CONFIDENTIAL 23
GDR, PhC, Dec 19, 2006
Packaging
CONFIDENTIAL 24
GDR, PhC, Dec 19, 2006
Packaging
MMM6000 Module
Freescale
Single package transceiver for quad
band EGPRS (GSM/GPRS/EDGE)
– 11.2x9mm
– 9 SMDs 0402
– 18 SMDs 0201
– 2.8x2.6mm 0.13µm CMOS
– 2.7x2.9mm 0.18µm RFCMOS
– 1.1x1.1mm IPD device
CONFIDENTIAL 25
GDR, PhC, Dec 19, 2006
Sychip Packaging
Silicon substrate with integrated passives
Size (mm) 9x9
I/O 12x12
Availability Sampling?
Known Partnerships ?
Source : Sychip
CONFIDENTIAL 26
GDR, PhC, Dec 19, 2006
Packaging
RF Micro Devices
Power Amplifier Module
7x10mm with 12I/O
GaAs for power amplification and silicon
for power control circuitry
Some passive components are integrated
Power Amplifier module
into GaAs
Transceiver module
Transceiver module
CONFIDENTIAL 27
GDR, PhC, Dec 19, 2006
Packaging
Intel
WLAN Transceiver
– 90nm CMOS technology
– designed as a system-in-package (SiP)
– FCBGA-packaged IC, die area 12.25mm²
Package-on-Package construction (folded flex
circuit from Tessera)
– Processor, flash & SDRAM
Prototype of 8-dies stack with no interposer
(50µm die thickness)
Intel is now using copper pillar bumping for its
processors
CONFIDENTIAL 28
GDR, PhC, Dec 19, 2006 15
Tessera Packaging
Carrier R L (Q) C Interconnectivity
Flex no 60 no 14 lines/mm
Si/GaAs no ? 0,11nF/mm² ?
Package-on-Package (folded carrier)
– 2 metal-layer polymide providing electrical and mechanical properties
for interconnect
Processor with associated memory
Tessera/Intel folded stacked CSP package
Configuration examples
Folded Stacked CSP assembly process
Sources : Prismark wireless technology report – March 2005
CONFIDENTIAL 29
GDR, PhC, Dec 19, 2006
Packaging
NXP Silicon-based SiP Standard
concept HVQFN
package
Flip chip
Passive die
Molding compound
Passive die
tip Active die tip
lead lead
Key benefits Flip chip
• Performance (flip chip interconnects) Active die
• Size (3D stacking, passive integration)
CONFIDENTIAL 30
GDR, PhC, Dec 19, 2006
Advantages of Double Flip Chip
Low interconnect parasitics
– Bump is 35-50pH
– Lead is 0,25nH
Low thermal resistance
– Active die can be attached to the die pad
– Large PICS die on top of the active die acts as heat spreader
Better RF performance
CONFIDENTIAL 31
GDR, PhC, Dec 19, 2006
MEMS vacuum packaging
MEMS devices packaged under vacuum environment or hermetic
operation
Increase Q-factor of MEMS resonator
Moisture and other gases are killers
Getter required in vacuum packaging
– Outgassing from package materials
– Leaks in package
– Getters absorbing moisture and gas molecules and capturing particles
– Maintaining package cavity for device operation
CONFIDENTIAL 32
GDR, PhC, Dec 19, 2006
Assembly of a SAW filter on silicon substrate
LiTaO3
PICS
Si
Gold stud - bumps Polymer seal ring
CONFIDENTIAL 33
GDR, PhC, Dec 19, 2006
Getter
CONFIDENTIAL 34
GDR, PhC, Dec 19, 2006
MEMS Acceloremeter stacked die package
STMicroelectronics
Targeted applications
– Toys, medicals, phones, anti-theft
4.3x4.0x0.4mm MEMS die
3.9x4.0x0.4mm cap die
3x2.8x0.2mm logic die
QFN 28 I/O, 2 stacked die
Die to die and die-leadframe wirebonds
CONFIDENTIAL 35
GDR, PhC, Dec 19, 2006 26
Outline
• Definition
• Market / Applications
• Design Perspectives
• Packaging Technologies
• Test Challenges
• Conclusion
CONFIDENTIAL 36
GDR, PhC, Dec 19, 2006
SiP vs SoC
Compared to a SoC, a SiP may have more…
Circuit Supply
Functions Voltages
Process Signal
Tuner
Techno. Source
Frequencies
Decoder Channel
Decoder
Signal
Suppliers Levels
Quality Failure
Levels mod./mech.
CONFIDENTIAL 37
GDR, PhC, Dec 19, 2006
NXP SiP Test Vision
Test Today:
Chip A
Test
+ Test of PCB
Chip B + Interconnects
Test + Passives
+ Functional
Chip C
Test cost = 3U Test cost = 4U
Future (w SiP):
- Test of PCB
With a Higher
- Interconnects
Coverage!
- Passives (almost 0!)
= Functional
Test cost < 3U Test cost << 4U
CONFIDENTIAL 38
GDR, PhC, Dec 19, 2006
A Complex Test Flow…
Wafer Test Final Test
D
Fab of X
E
& Known
Die X
Wafer Test
L
PCM Test SiP I
Fab of B
Good
Die B
SiP
Packaging. Final Test
V
Fab of A
&
Dies! A
Die E
PCM Test
Wafer Test R
Y
System-level Test:
• Quality level
DfT
Digital or Mixed-mode
Passive Substrate
• YieldDiagnosis
Fast
at a reasonable
and…
Analog/RF
• Test cost!
Known-Good-Dies!
CONFIDENTIAL 39
GDR, PhC, Dec 19, 2006
Known-Good-Die
KGD Definition:
(from a test perspective)
• Good enough to meet, at die level, at least the same
quality level as a packaged IC
• Implies that :
• KGD test = WT + FT of a packaged die!!
CONFIDENTIAL 40
GDR, PhC, Dec 19, 2006
Cantilever RF probing concept
Package: Die under probes:
Wire bonding length Needle length
Bonding: 1-3mm Probe tips: 3-5mm
Leadframe: mm size
Rule of thumb:
10mm represent 10nH serial inductance
impossible to test a PA @freq, for example!
Total Probe length: 10-15mm
CONFIDENTIAL 41
GDR, PhC, Dec 19, 2006
Thin film technologies
for RF probing
Standard thin film technologies can provide
shorter connections between die pad and
grounding or matched tracks
Thin film, Μr 25um
40um-60um
Rule of thumb:
0.05mm represents less than 0.5nH serial
inductance (typical 0.2nH specified)
CONFIDENTIAL 42
GDR, PhC, Dec 19, 2006
Die On Die RF Wafer Test: the probe card
CONFIDENTIAL 43
GDR, PhC, Dec 19, 2006
Full Test at Wafer
Alternative Test Methods
• Power supply sweep
Signature-based Testing • I-V Signatures
• Multiple observation points
• Simple method
(VDD Test Pattern) • “black-box” methodology
• No functional testing
IDD R
• Short test time
Package
(Reference L=1n
Clock Signal) H
CLKI VOS
N C
DUT RLP
F
CLKOU
T
VCLK
CLPF
CONFIDENTIAL 44
GDR, PhC, Dec 19, 2006
Management of diversity
Which leads SiP package test to:
Require greater diversity of ATE resources than SoC
Require greater diversity of test & reliability screen methods than SoC
Have large disparities in test times and resource utilization among die
Solutions:
Insert in multiple testers
Better scheduling of test resources to allow independent, simultaneous test
of each accessible chip in SiP
BIST / DfT / DSP
CONFIDENTIAL 45
GDR, PhC, Dec 19, 2006
System Testing Issues
Intermediate Test Points may affect signal
integrity and leads to longer test times
Data
bits
TX
PA Buf D DSP
core
Philips:
Philips:
A
DigRF interface
DigRF interface
advantage vs disadvantage
LNA D
advantage vs disadvantage
A
AGC
RX
TX-FEM Transceiver Baseband
So, what to do?
CONFIDENTIAL 46
GDR, PhC, Dec 19, 2006
1. Test Rx and Tx paths independently
Ref: “Seamless test of Digital Components in M/S paths”, S. Ozev et al
Data
bits
TX
PA Buf
Modulated D DSP
RF
Philips:
Philips:
A core
DSP
DigRF interface
DigRF interface
advantage vs disadvantage
LNA D
advantage vs disadvantage
A
Modulated
AGC
RF
DSP
RX
TX-FEM Transceiver Baseband
Pro: Contra:
- close to the application conditions - expensive ATE
- two-pass test = reduced test time - quality of contacts critical
- reduced risk of signal degradation - diagnosis??
CONFIDENTIAL 47
GDR, PhC, Dec 19, 2006
2. Test Rx and Tx paths together (loop-back)
Ref: “Wafer level RF Test and DfT for VCO Modulating Transceiver Architectures”, S. Ozev et al
Data
bits
TX
DSP
PA Buf D DSP
core
Philips:
Philips:
A
DigRF interface
DigRF interface
advantage vs disadvantage
LNA D
advantage vs disadvantage
AGC
A DSP
RX
TX-FEM Transceiver Baseband
Pro: Contra:
- low-cost (no?) ATE - need DfT (not a simple short-circuit!)
- benefit from PICS capabilities - correlation with lab measurements
- test simulation - mgt of yield / test escapes
- easier BIST implementation - diagnosis??
CONFIDENTIAL 48
GDR, PhC, Dec 19, 2006
Loop-back starts at the beginning
Auxiliary function ADC N
Biggest advantage: Auxiliary function
LNA
ADC N
ADC1
Full digital test BPF BPF LO BPF VGA
LNA HPA DAC1
ADC1
Transceiver : RF Die
BPF BPF LO BPF VGA ADC M
Auxiliary function
Mixed Signal Die
Challenges:
HPA DAC1
Transceiver : RF Die
Loop-back: Analog Design For Test issue ADC M
Auxiliary function
Test methods: digital post processing Mixed Signal Die
ADCs DACs test
Compensate data converters errors improve their performances
similar to measurement instruments
Test each block through other blocks
CONFIDENTIAL 49
GDR, PhC, Dec 19, 2006
Loop-back starts at the beginning
DAC1
Analog Part 2
Digital
ADC2
part 1
ADC3
ADC3
ADC1
RF Part Digital
part 2
Analog DAC4 Analog
Part 1 Part 1 ADC4
ANC
Digital
DAC3
part 3 Digital
part 4
Strategy:
1. Find DSP-based methods / algorithms to re-use the analog/ms blocks as instruments
2. Implement hardware that supports the methods
CONFIDENTIAL 50
GDR, PhC, Dec 19, 2006
Tests of Data Converters
Dynamic Parameters:
THD (Total Harmonic Distortion) 160
140
SINAD (Signal to Noise And Distortion 120
spectrum values
ratio) 100
SFDR (Spurious Free Dynamic Range) 80
60
ENOB (Effective Number of Bits) 40
Harmonics enter in the calculation of
20
these parameters
0
1 6 11 16 21 26 31 36 41
Static Parameter:
Spectrum of a sine wave affected by errors
INL (Integrated Non-Linearities)
Values linked to the harmonics
Harmonics
CONFIDENTIAL 51
GDR, PhC, Dec 19, 2006
Analog Network of Converters
Test Procedure
(LIRMM + NXP)
01101 01101
10010 ADC1 10010
10101 DAC1 10101
11100 11100
01101 01101
10010
DAC2 ADC2 10010
10101 10101
11100 11100
Σ
01101
10010 01101
10101 DAC3 ADC3 10010
11100 10101
11100
01101 01101
10010 ADC4 10010 # Tested Equi. test
10101
DAC4 10101 Step
11100 11100 convert. time
01101 01101 #1 3 5
10010 ADCm 10010
10101
DACn 10101
11100 11100 #2 3 1
#3 6 1
Dynamic Process #4 12 1
CONFIDENTIAL 52
GDR, PhC, Dec 19, 2006
SiP Testing
• Diagnosis capabilities using signatures (1)
Data
TX
PA Buf D DSP DSP
core
Philips:
Philips:
A
DigRF interface
DigRF interface Faults
Faults Faults
advantage vs disadvantage
LNA D
advantage vs disadvantage
AGC
A
DSP
RX
TX-FEM Transceiver Baseband
CONFIDENTIAL 53
GDR, PhC, Dec 19, 2006
• Diagnosis capabilities using signatures (2)
Objective: Obtain maximum diagnostic resolution
– Minimize the number of test set-ups
– Minimize the number of sampling points
Identify location dependent parameters
– Examine undesired characteristics (NF, IIP3, gain compression)
– Enhance the location dependency of the undesired response components
Determine significant measurement set-ups
Create a diagnosis dictionary
CONFIDENTIAL 54
GDR, PhC, Dec 19, 2006
• Diagnosis capabilities using signatures (3)
CONFIDENTIAL 55
GDR, PhC, Dec 19, 2006
SiP Testing
• Wireless Wafer / SiP Test
CONFIDENTIAL 56
GDR, PhC, Dec 19, 2006
Testing Wirelessly (LIRMM+NXP)
Transmitter/
Receiver
ATE Test Die 1
Control
Block
Die 2
Die 3
SIP
Architecture for testing a SiP wirelessly
CONFIDENTIAL 57
GDR, PhC, Dec 19, 2006
Outline
• Definition
• Market / Applications
• Design Perspectives
• Packaging Technologies
• Test Challenges
• Conclusion
CONFIDENTIAL 58
GDR, PhC, Dec 19, 2006
Summary
• SiP is:
• significantly growing
• not a SoC
• represents many challenges in:
• design (tools, EMC,…)
• packaging (stacked, planar, PiP, PoP, …)
• test (KGD, System Testing,…)
thus, SiP technologies offer
many perspectives /
opportunities
to students, researchers
and engineers
CONFIDENTIAL 59
GDR, PhC, Dec 19, 2006
CONFIDENTIAL 60
GDR, PhC, Dec 19, 2006
GLOSSARY
• SiP: System-in-Package
• SoC: System-on-Chip
• PICS: Passive Integration Connecting Substrate
• MCM: Multi-Chip-Module
• MEMS: Micro-Electro-Mechanical-Systems
• ATE: Automatic Test Equipment
• DUT: Device Under Test
• KGD: Known-Good-Die
• DfT: Design-for-Test
• BIST: Built-In-Self-Test
• DOT: Defect-Oriented-test
• DSP: Digital Signal Processing
• CTAG: Core-Test-Action-Group
• JTAG: Joint-Test-Action-Group
• ELFR: Early-Life-Failure-Rate
• LTFR: Long-Term-Failure-Rate
•
CONFIDENTIAL 61
GDR, PhC, Dec 19, 2006
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