electronics by lakshmidhar


									         Measurement of Crosstalk in Integrated Circuits

K.RAMYA                                           N.NIRUPAMA
B.Tech (IV/IV )E.C.E ,                            B.Tech (IV/IV )E.C.E ,
Syed Hashim College of Science -                    Raghu Engg.College,
and Technology,                                   Visakhapatnam,
Gajwel(m), Medak(dt), A.P. ,                        A.P.
Mail to: khvramya@yahoo.com                          niru_deepthi@yahoo.co.in
                          Gayatri Vidya Parishad (J.K.C)

Abstract —This paper describes a specific technique for measuring and characterizing the
time-domain aspect of the crosstalk effect based on a sampling technique. It includes the
description of the circuit implementation in 0.7- m technology and the measurements of
the crosstalk between metallization tracks within the chip, with a 10-ps resolution and 10-
mV precision. A comparison between the measurements and analog simulations based on
a distributed RC model is also included. The key advantages of this technique are that it
is totally integrated, fully static, and adaptable to any CMOS technology.








    I.         INTRODUCTION:

         Considering the improvements in integrated circuit technology together with the increased level of
integration in VLSI, the handling of interconnect-related problems has changed dramatically. This is due
mainly to the increasing role of RC delays but also to the presence of crosstalk glitches [1]. These parasitic
effects may eventually prevent full advantage being taken of the advance in modern semiconductor
manufacturing techniques. The multiplication of metallization layers constitutes the first reason why such
difficulties arise. While five layers are used in 0.35- m technology, the 0.07- m technology uses an
estimated eight layers. The second reason resides in the fact that increased coupled surfaces generate
larger parasitic capacitance, while the reduction of the interconnect cross section significantly increases the
line resistance.Therefore, the electrical model of the metallization lines has moved from simple capacitance
to a more realistic one that takes into account fringing capacitance, crosstalk capacitance,and parasitic
resistance effects [2].
                           Although studies concerning the modeling of crosstalk effects are numerous, few
experimental approaches of the crosstalk phenomenon have been proposed in the literature [3]. In a
previous paper [4], we investigated an approach based on an indirect measurement method of a parasitic
commutation of a RS latch due to crosstalk. This technique only gives the noise voltage amplitude while
the time domain remains unknown. The electron-beam sampling and testing technique may be used to
observe the time-domain aspect of voltage transitions in interconnects without any direct contact with the
chip. The disadvantages of this method include in particularly the four following parameters: the very high
cost of the test equipment required, the limitation of the bandwidth to around 500 MHz, the inadequacy
of the technique when measuring very low energy spikes, and the screening effect of the upper
metallization combined with the passivation oxide. Consequently, the e-beam technique does
not provide any visualization or characterization of the crosstalk effect. The technique proposed in [5] is
based on a sampling technique similar to the measurement method used in sampling oscilloscopes. It
consists of a MOS device to introduce the sampling delay. This technique is applied in a similar manner to
the delay cell of Fig. 1 with improved linearity. The advantage of the method is to give the possibility of
reconstructing the time-domain aspect of the signal by taking a single sample at each period and slightly
delaying the measurement at each cycle.
                                                 This paper proposes the use of an on-chip measurement
circuit featuring an on-chip resolution approaching 10 ps in 0.7- mCMOStechnology, with a precision of
10mVin order to measure the crosstalk waveform, thanks to a totally integrated delay system and complete
static control of the measurement. Details on the sampling structure and the calibration patterns are
Provided in Section II, while Section III presents the experimental results concerning the characterization
of the crosstalk noise in two-metal-layer 0.7- m CMOS technology. Section IV shows a comparison with
the usual RC line model and is followed by a general conclusion.
In Fig. 1, the schematic diagram of the coupled lines configuration and the associated measurement circuit
are presented. An external synchronization (Synchro) is used to trigger off a buffer whose output switches
and induces a noise by proximity coupling to a victim line. The noise obtained is sampled by a transmission
gate, then stored in a capacitance, “Cstorage,” which plays the role of an analog memory, and is
subsequently amplified by a follower before being exported out of the chip. This capacitance is the sum of
the input capacitance of the follower amplifier and the parasitic capacitance of the transmission gate
junctions. Its value is high enough to keep the sampled voltage intact while the external measurement are
being taken, but small enough to avoid degrading the system bandwidth. The way the crosstalk waveform
is reconstructed is detailed in Fig. 2.
                             Every time the “Synchro” signal rises, the buffer switches and the crosstalk effect
appears. Concurrently, the sampling signal is delayed by depending on an externally controlled Vanalog.
At the rising edge of this sampling signal, the transmission gate switches off and the value of the sampled
fluctuation is stored in the capacitance, “Cstorage,” used as an analog memory for some microseconds. The
captured analog value is then copied by the follower and exported out by an external analog-to-digital
converter. Repeating this procedure for a “Vanalog” ranging from zero to some volts enables the crosstalk
wave form to be accurately reconstructed as described in Fig. 2. The bandwidth of the measurement
systems is around 4 GHz in a 0.7- m technology with an average time resolution of 15 ps and a precision
of 10 mV.

                                              Fig. 1. Schematic diagram of the sampling sensor.
                                    Fig. 2. Waveform description of sampling sensor behavior

                                         Fig. 3. Schematic diagram of the calibration device.

The most critical part of the measurement circuit is the delay system, controlled by “Vanalog,” which is the
most frequent cause of timing errors during the measurement and perhaps the greatest source of inaccuracy.
The delay circuit is based on a combination of a p-type pass mode device and a pulldown resistance,
featuring a quasi-linear time dependence versus the voltage control of the gate from 1 to 4 V
approximately. The determination of the dependency between Vanalog and the delay is
confirmed by a specific calibration pattern based on a ring oscillator made from 12 inverters, a NAND gate
that allows a natural oscillation, and the delay system used in the sampling circuit as shown in Fig. 3. The
change in Vanalog leads to a change in the oscillation frequency. The resulting oscillation is divided by
64 using six stages of divide-by-two circuits before the signal is buffered and exported out of the chip. The
delay cell contribution, and consequently the dependency between Vanalog and the sampling delay, can be
deduced from the observed frequency variation.

The sensor probe has a very small capacitance that can be neglected compared to the total interconnect
capacitance if the interconnect length is longer than approximately hundred micrometers. The parasitic
probe capacitance (around 10 pF) is mainly made up of the drain/bulk junction of the transmission
gate. A small transistor width is therefore preferred to reduce the parasitic capacitance of the probe.
For measurement purposes, the gate voltage control of transistor N1, “Vcontrol” (Fig. 1), is set to , and is
externally fixed at a preestablished voltage. This procedure provides the opportunity of investigating the
effect of precharging the victim line from zero to on the crosstalk amplitude. This mode corresponds to an
analog signal line coupled to a logic signal line. Notice that the victim line’s “precharging” to various
voltages comes about with significant changes in the on-resistance of the NMOS pass transistor.

Two coupled-lines patterns have been implemented in a twometal-layer 0.7- m CMOS technology. Each of
the patterns uses a different layer. The first pattern uses the lower metal layer, and the second uses the
upper metal layer. The victim line is confined between two affecting lines (Fig. 4) in order to increase the
role of the crosstalk. This configuration also corresponds to a bus inside, which the two external
interconnects are switching. As for the cross section, it details the vertical and horizontal sizing of the case
studies. The length of the victim line is 6000 m. The measurement circuit size in its 0.7- m implementation
is approximately the size of a pad, that is, 100 100 m, which is essentially due to the follower amplifier and
its internal compensation capacitance. The microphotograph of Fig. 5 shows the measurement system and
the coupled lines in the lower metal configuration layer.

                                     Fig. 4. Coupled line details for lower and upper metal configurations

                               Fig. 5. Microphotograph with details on the coupled lines in lower metal and
                                                 the crosstalk measurement circuit .
                                  Fig. 6. Delay versus Vanalog dependency extracted from the measurements of

                                                the ring oscillator.

    A.. Calibration Circuit Measurement:
The frequency measurement issued from the calibration circuit oscillation provides the value of the
dependency between the voltage Vanalog and the delay response, as shown in Fig. 6. The measurement is
consistent with the SPICE simulation. The stability of the frequency measurement leads to an estimated
error lower than 1%, corresponding to a delay error around 10 ps. The delay dependence with Vanalog can
be approximated in two linear regions: the first one ranges from 0 to 1 V and corresponds to a delay of 1 ns,
mainly due to the P-channel MOS (P1) resistance modulation. The second one ranges from 1 to 3 V,
corresponding to 25 ns due to the linear discharge of the node A (Fig. 6) through resistance R1. A
polynomial expression fitting the measurements with an accuracy greater than 0.1% has been used to
transform the voltage Vanalog into its corresponding effective delay.

                                   Fig. 7. Measured offset of the follower alone and of the complete system.

                                                           TABLE I
To characterize the transmission gate and follower offset, a voltage ramp is generated at the probe input,
with the transmission gate acting as a sampler. The measured output gives the correspondence between the
voltage appearing at the probe and the real measured output voltage. When the transmission gate is on, the
follower response is linear, with an expected lower bound around 50 mV (Fig. 7). When the gate is turned
off, the circuit exhibits a good linear behavior from 0 to 2.5 V. From voltage input higher than 2.5 V, a
300-mV offset appears, due to the nonlinear parasitic coupling between the gate P1 and node A.

B. Crosstalk Measurements:
In Fig. 8, the crosstalk measurements are shown and repeated for metal 1 and metal 2 configurations. The
recurrence of the measured voltage leads to an estimated error of around 10 ps for axis and 10 mV for axis.
The parasitic commutation is a rise edge in the case of metal 1, and a fall edge in the case of metal 2. The
precharge voltage varies from 1 to 3 V for metal 1 configuration and from 2 to 4 V for metal 2
configuration. A maximum 0.5-V crosstalk noise with a duration of 10 ns is observe for metal 1 with a
victim line precharged to 3.0 V. For the metal 2 configuration, an almost constant 0.9-V noise is observed
whatever the precharge values. The crosstalk noise for the upper metal layer is higher than for the lower
metal due to a greater distance from the ground, leading to a smaller line-toground capacitance while the
lateral crosstalk capacitance remains constant, thus increasing the crosstalk versus ground capacitance ratio.
Table I provides a detailed outline of the measured crosstalk. The crosstalk duration has been computed at
half of the maximum crosstalk amplitude. Concerning metal 1, both the crosstalk noise amplitude and
duration are sensitive to the precharge value. In the case of metal 2, the duration is almost constant while
the amplitude varies. The amplitude sensitivity to the precharge can be explained by the nonlinear
resistance of the pass transistor. With a high precharge value, the equivalent resistance is much higher, and
thus the tie to the external voltage is weaker.

                                          Fig. 8. Measured crosstalk effect for metal 1 and metal 2 configurations.
                                             Fig. 9. Comparison between simulation and measurements

A set of stand-alone devices has been implemented on the same chip for the measurement of the versus and
versus of MOS devices with several sizes covering the ranges used in the measurement circuits. An
accurate SPICE level 3 model has been extracted and optimized from those measurements with a fit
between measurements and simulations better than 5%. A set of analog simulations has been conducted to
compare the predicted crosstalk noise with our measurements. The model used here is a distributed RC
line, with the capacitance computed by a commercially available finite-element capacitance solver with
foundry parameters. Fig. 9 gives a comparison of the curves obtained by simulations and measurements for
a polarization of 3 V of the victim line in metal 1 configuration. Near-end, middle, and far-end crosstalk are
reported. A good agreement is observed for the peak amplitude and duration between simulated and
measured crosstalk appearing at the middle of the line. Most of the waveforms show some ringing after the
main pulse. This ringing is probably the consequence of package fluctuation (DIL28 technology). This
phenomenon was almost totally suppressed using high-performance packaging (QFP) featuring
low parasitic inductance.

This paper presents the results for precise measurements of the crosstalk noise inside a CMOS specific
integrated circuit using a simple sampling technique. The amplitude and duration of the noise were
measured with an amplitude on the order of 1 V, which shows the importance of crosstalk effect even in a
conventional 0.7- m CMOS technology. The measurement circuit features significant advantages over
direct probing techniques or electron beam testing such as: a very high time resolution (better than 20 ps in
0.7- m technology), a good voltage precision (20 mV), or again a very simple measurement procedure.
Furthermore, circuit performances keep pace with the scaling down of the technology, which improves the
time resolution and allows the measurement of any parasitic signal within the chip. In future work, we will
tackle issues such as the reduction of the sampling offset and crosstalk delay characterization of intermetal
crosstalk (metal 1/metal 2).
[1] T. Hameenanttila, J. D. Carothers, and D. Li, “Fast coupled noise estimationfor crosstalk avoidance in
the MCG multichip module autorouter,”      IEEE Trans. VLSI Syst. , vol. 4, pp. 365 –368, Sept. 1996.
[2] K. Joardar, “A simple approach to modeling cross     -talk in integrated circuits,” IEEE J. Solid State
Circuits , vol. 29, pp. 1212 –1219, Oct. 1994.
[3] K. Soumyanath, “Accurate on -chip interconnect evaluation: A time domain technique,”         IEEE J. Solid
State Circuits , vol. 34, pp. 623 –631, May 1999.
[4]IEEE Journals & Magazines

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