Modeling and simulation of core switching noise on a by zqw77719

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									                 Modeling and Simulation of Core Switching Noise on a Package and Board

                          Nanju Na*, Madhavan Swaminathan*, James Libous** and Daniel O'Connor**
                                              * Georgia Institute of Technology
                                             777 Atlantic Dr, Atlanta, GA 30332
                          madhavan.swaminathan@ee.gatech.edu, Ph: 404 894-3340, FAX: 404 894-9959
                                                  ** IBM Microelectronics
                                                    Technology Campus
                                                    Endicott, NY 13760

Abstract                                                                                                      (9mmX9mm)
   This paper presents simulation and analysis of core
switching noise on a CMOS test vehicle. The test vehicle
consists of a ceramic ball grid array (CBGA) package on a
printed circuit board (PCB). The entire test vehicle has been
modeled by accounting for all the plane resonances using the
cavity resonator method. The models included both the on-
chip and off-chip decoupling capacitors. Using both time
domain and frequency domain simulations, the role of plane                 Voltage
resonances on power supply noise for fast current edge rates               Regulator
has been discussed. The models have been constructed to                    Module
amplify certain parts of the test vehicle during simulations.

I. Introduction
    There has been much speculation in the design community
about the role of plane resonances on core switching noise. In
the past, partial element equivalent circuit (PEEC) based                        Fig. 1 Core Switching Noise Test Vehicle
approaches have been used as illustrated in [1] and [2]. These
approaches used an inductive network to model the via                  Signal, voltage, and ground C4's were six rows deep on the
inductances and the partial lateral inductances of the planes.      chip periphery. Each voltage-ground pair serviced seven
However, as packages and boards become thinner with enough          signal I/O cells. An array of voltage and ground C4's provided
vias to reduce the vertical inductance, it is expected that plane   power to the core logic. The core voltage C4's were placed on
effects will start dominating the core switching noise. In [3], a   a 921.6 um pitch with ground C4's interstitially placed
method was presented for modeling planes. Though this paper         between the voltage C4's on the same pitch. The test chip and
provides insight into the cause and effect of plane resonances,     four 32nF decoupling capacitors were mounted on a 32mm
it does not provide much detail on its importance for a             CBGA package. The CBGA package had six power and
complex system. In this paper an entire CMOS test vehicle has       ground mesh planes, three signal distribution layers, and two
been modeled using the cavity resonator method [4] where            pad layers. The module was mounted in the center of a 9x11
both the vias and planes have been modeled. The primary goal        inch test card. The card had eight signal layers, and six voltage
of this paper is to demonstrate the frequency beyond which the      and ground layers. Decoupling capacitors were mounted on
plane effects need to be considered. In addition, the amount of     the card, as shown in Fig. 1. The test vehicle was powered
noise generated by the planes (in the absence of via                with a 3.3V supply on one corner of the PCB.
inductance) has been quantified for multi-gigahertz packages.
Finally, a modeling method is presented that preserves the          III. Modeling Plane Layers
passivity of the circuit during core switching noise simulations        In the past, the inductance of the package power
and enables the simulation of large networks.                       distribution has been the major contributor to core logic
                                                                    switching noise. Hence, the test structure in Fig. 1 was
II. Test Vehicle Description                                        previously modeled based on three dimensional package
    The test structure that was modeled consists of a multi-        inductance models using the PEEC method discussed in [1].
layered CBGA package and PCB. Fig. 1 shows the details of           Reduction techniques were then used to create an equivalent
the plane layers and the decoupling capacitors in the test set-     lumped inductance model. This modeling approach captured
up. A CMOS ASIC test chip was mounted on the CBGA                   the peak inductive noise, and the resonant noise due to the LC
package through controlled collapse chip connections (C4)           tank circuit formed by the package inductance and the chip
and the CBGA package was attached to the board through              capacitance. Hence, the edge effects from planes were not
solder balls. The CMOS ASIC test chip measured 9 mm on a            modeled since it was not considered to be dominant due to the
side and was fabricated with IBM's CMOS5L process                   relatively slow speed of the ASIC test chip.
technology. The test chip contained 766 C4 flip-chip pads;              In [3], the importance of modeling radial waves between
468 signal, and 298 divided between voltage and ground. The         plane pairs has been discussed. It has been speculated that the
pads were arranged on a 230.4 um pitch.


0-7803-7038-4/01/$10.00 (C)2001 IEEE                                     2001 Electronic Components and Technology Conference
plane resonances can dominate the core noise for fast chips on                  where   Lmn = d/(ωmnabε),
packages/boards with negligible vertical via inductance. To
verify the speculation, the test vehicle in Fig. 1 was re-
                                                                                        Cmn = abε/d,
modeled to account for the plane resonances. In [3],[4], a                              Gmn = ( abε/d ) ωmn (tanδ+( 2 / ω mnµσ )/d),
method has been presented for modeling planes. This method
                                                                                                                      nπyi      nπtyi
uses a cavity resonator model to represent a plane pair as an                   and Nmni= n m cos mπxi sinc mπtxi cos
                                                                                          εε                               sinc       .
electromagnetic system. The method was then extended to                                             a        2a        b         2b
multiple plane pairs under the skin effect approximations. The                     The conductance Gmn can be approximated as
cavity resonator model has been used in this paper, which has
been briefly described in this section.
                                                                                Gmn =( abε/d2 ) 2ωmn / µσ             for low dielectric loss
    Consider a plane pair, as shown in Fig. 2. The structure can                (tanδ<<r/d) substrates. In equation (2), each propagating
be modeled as an electromagnetic system by assigning ports to                   mode is represented as a parallel resonant circuit. The port
the structure. Ports represent positions on the plane pair where                response is, therefore, represented as the summation of infinite
either a current source exists or a voltage is to be measured.                  modes. In equations (1) and (2), the ground plane in Fig. 2 is
                                                                                assumed to be an equipotential surface. To account for the
                                                                                potential variation across the ground plane, the circuit as
                                                                                shown in Fig. 3 was constructed with the component values
                                                                                [4]:
                                                                                                        Gmn' = 4 ∗ Gmn
                                                                                                       Cmn' = 2 ∗ Cmn
                                                                                and                    Lmn' = Lmn /2                         (3)
                                                                                    The circuit in Fig. 3 is a passive circuit and meets all the
                              Fig. 2 Plane pair                                 passivity conditions. Since the CBGA package and board in
                                                                                the test set-up consist of multiple plane layers, each plane pair
    The impedance matrix between the ports can be computed                      in the structure was first modeled seperately using the above
as [3]:                                                                         method and combined together in SPICE using the skin effect
                                      2   2

Zij(ω) =jωµd ∑
                    ∞     ∞
                                   ε nε m                                       approximation described in [3]. This enabled the construction
                          ∑      2
                                      − k 2 )ab
                                                  f ( xi , yi , xj , yj ) (1)   of a multi-layered stack-up for the test vehicle described in
                   n =0 m =0 ( k mn                                             Fig. 1.

where
         f ( xi , yi , xj , yj ) = (cos mπxi sinc mπtxi ) ·
                                           a           2a
                nπyi      nπtyi          mπ x j      mπtxj
         (cos        sinc       ) · (cos        sinc       )
                 b         2b             a           2a
                nπyj       nπtyj
        · (cos        sinc       )
                 b          2b
        k = k '− jk " with k ' = ω        εµ and
      k " = ω εµ (tan δ + r d )/ 2 ,
                       2          2
        k mn = (m π a ) + (n π b ) ,
          2


        r = 1/     πfµσ the skin depth,
      δ is the dielectric loss angle,
      εm, εn =1 for m,n=0 and             2 ,otherwise,
       m, n are the propagating modes,                                                      Fig.3 Equivalent circuit for a plane pair
      (xi,yi), (xj,yj) are the co-ordinates of the port
      locations, and (txi, tyi), (txj, tyj) are the dimensions of the              With the resonator model that included the cavity
      ports.                                                                    resonances of the planes, the following test cases were
    The impedance matrix in equation (1) can be rewritten as                    simulated: i) core noise with only the package model, ii) core
[4]:                                                                            noise with the package model and on-chip capacitance, iii)
            ∞       ∞                                                           core noise with the package and PCB models integrated,
                                  NmniNmnj
Zij(ω) =   ∑ ∑ 1 / jωL
           n =0    m =0          mn + jωCmn + Gmn
                                                                   (2)          where the PCB model included decoupling capacitors, iv) core
                                                                                noise using the model in iii) containing decoupling capacitors



0-7803-7038-4/01/$10.00 (C)2001 IEEE                                                 2001 Electronic Components and Technology Conference
mounted on the package and v) core noise using the model in
iv) with the on-chip capacitance included. Using this
approach, the importance of each part can be assessed.
IV. Core Switching Noise using the Package Model
   The CBGA package alone was modeled and simulated to
understand the effect of the package planes on core noise. The
ports on the chip area of the package were defined as shown in
Fig. 4.
                                                                                       Fig. 5 Current Source 1

                                                                      The simulation result for the voltage fluctuation between
                                                                   ports 18 and 19 is shown in Fig. 6. In Fig. 6, the oscillatory
                                                                   waveform was produced by the package plane resonances and
                                                                   the deep valleys in the waveform were caused by the
                                                                   inductances of vias, C4s and solder balls. It can be clearly
                                                                   seen that the noise due to the plane resonance is trivial
                                                                   compared to the noise due to the inductances in this
                                                                   simulation.



1-5: Ports for the ground connections between the chip C4s
and ground planes of the package
6-9: Ports for the Vdd connections between the chip C4s and
Vdd planes of the package
10-13: Ports for the ground connections using solder balls
between the bottom ground layer of the package and the board
grounds
14-17: Ports for the Vdd connections using solder balls
between the bottom Vdd layer of the package and the board
Vdds
              Fig. 4 Port locations on the package
    Five ports for ground and four ports for Vdd were defined            Fig. 6 Core noise due to Package: tr = 1ns, tf = 9ns.
for the C4 locations in the core area of the chip, as shown in
Fig. 4. The same number of grounds and Vdds were defined               The same simulations were repeated with faster current
for the vias connecting from the planes to the solder balls. The   sources. The results with a current source of 0.5ns rise time
ground planes and Vdd planes were connected together using         and 4.5ns fall time and a current source of 0.1ns rise time and
through vias at the C4 locations. The chip was powered at the      0.9ns fall time are shown in Figs 7 and 8, respectively. The
bottom of the package by connecting an ideal voltage source        simulation results show that the noise contribution due to the
to the solder ball locations between Vdd and ground. A             planes increases with faster current sources, suggesting that
current source as shown in Fig.5 was connected between ports       the source excites the plane resonances. The plane
5 and 9 in Fig. 4 to emulate the on-chip switching activity of     contribution is almost equal to the inductive contribution in
the circuit. The fluctuation on the ASIC power supply was          Fig. 7 and the main contribution to the noise is from the plane
observed between ports 18 and 19 in Fig. 4. Vias, C4s and          in Fig. 8. In Figs 7 and 8, the sharp peaks are due to high
solder balls were modeled with lumped inductors of 15pH,           frequency noise. From Fig. 8, clearly the CMOS5L Test
10pH and 10pH, respectively. The inductances for the C4s           Vehicle cannot support a 100 ps edge rate (without on-chip
and solder balls were based on the number of these structures      capacitance) since the noise is almost equal to the logic swing.
in parallel at each port location. Similarly, the via inductance   This, however, can be a very myopic view since only a small
was derived using the PEEC method for a group of vias in           part of the entire system, namely the package, has been
parallel per layer, at each port location. No decoupling           considered.
capacitors were included in the simulation model. The model        V. Core Noise with Package and On-chip capacitance
was first simulated using the current source in Fig. 5 with 1ns    Using a current source with 0.1ns rise time and 0.9ns fall time,
rise time (tr) and 9ns fall time (tf).                             the package model was simulated using an on-chip capacitor
                                                                   of 32nF with a series resistance of 6.3mΩ. Fig. 9 shows the
                                                                   result. The on-chip capacitance decreases the noise
                                                                   substantially. However, around + 25 mV of residual noise
                                                                   exists in the package in the steady state due to the plane



0-7803-7038-4/01/$10.00 (C)2001 IEEE                                    2001 Electronic Components and Technology Conference
resonances. This noise can increase with larger current
sources.




                                                                     Fig. 9 Core noise due to package with on-chip capacitance

 Fig. 7 Core noise due to package only: tr = 0.5ns, tf = 4.5ns




                                                                   1: Port for the ideal power supply
                                                                   2-17: Ports for decoupling capacitors of types C1 and C2
                                                                   18-21: Ports for decoupling capacitors of type C3
                                                                                 Fig. 10 Port locations on the PCB
                                                                          Table 1 Decoupling capacitors used on the PCB

 Fig. 8 Core noise due to package only: tr = 0.1ns, tf = 0.9ns                          C                RE                LE
                                                                        C1             47nF             0.1Ω              1nH
    From Figs 7,8,9, it is apparent that for fast current edges,        C2             10nF             0.1Ω              1nH
the cavity modes in the package planes need to be modeled, if           C3             20µF              1Ω              10nH
the package alone is considered. Clearly, the on-chip
capacitance has a dominant effect on the noise.                        In Fig. 10, the Vdd planes and ground planes were shorted
                                                                   together using ideal vias at the decoupling capacitor locations.
VI. Core Noise with Package and PCB                                Inductances for the vias and solder balls were not included in
The test vehicle in Fig. 1 including the CBGA package and
                                                                   this simulation to amplify the plane resonances. The current
board layers was modeled and the simulations were repeated
                                                                   source shown in Fig. 11 was used for the switching activity.
by observing the voltage variation between ports 18 and 19.
                                                                   The current source had the same rise time of 1ns as before.
Fig. 10 shows the test board and the port locations for the
                                                                   However, the fall time and period were changed to 1ns and
ideal power supply, decoupling capacitors and solder balls.
                                                                   50ns, respectively. The goal of the longer period was to enable
The position of the CBGA package is also shown in the figure.
                                                                   sufficient time for all the oscillation to die down prior to the
Three kinds of decoupling capacitors as shown in Table 1
                                                                   next switching event. Three test cases were simulated. In the
were used on the PCB. In Table 1, RE and LE indicate parasitic
                                                                   first test case, no capacitors were included on the PCB. In the
resistance and parasitic inductance of a decoupling capacitor,
                                                                   second test case, all the capacitors were assumed to be ideal
respectively.
                                                                   and included on the PCB. In the final test case, all the PCB
                                                                   capacitors with parasitics were included in the simulation.
                                                                   These test cases were used to understand the effectiveness of
                                                                   the PCB capacitors in suppressing core switching noise. The
                                                                   simulation results for the differential voltage between ports 18


0-7803-7038-4/01/$10.00 (C)2001 IEEE                                    2001 Electronic Components and Technology Conference
and 19 on the top surface mount layer of the CBGA package             oscillations after the switching activity still exist at a
are shown in Fig. 12. Since ideal vias and solder bumps with          frequency of ~100MHz which are produced by the PCB
no inductance were used in the simulation model, the noise            planes.
contribution in Fig. 12 was produced by the planes.
                                                                      VIII Core Noise with Package, PCB, On-chip Capacitance
                                                                      and Package Capacitance
                                                                           Four module capacitors of 32nF each with RE=0.1Ω and
                                                                      LE=50pH were next included into the package models. They
                                                                      were connected to the package planes outside the die area at a
                                                                      distance of 5mm from the die edge, one on each side of the
                                                                      die. The via inductance from the capacitors to the package
                                                                      planes were assumed to be negligible. The simulated result is
            Fig. 11 Current source 2: tr=1ns, tf=1ns                  shown in Fig. 13. The inclusion of the module capacitors had
                                                                      little effect on the noise in Fig. 13 which can be attributed to
     In Fig. 12, the oscillatory waveform is caused by the radial     the large lateral inductance of the planes from the capacitor to
waves between planes. The oscillation consists of a high              the ASIC.
frequency component modulated on a low frequency
component. From the period of the low frequency oscillations,
it is clear that they are caused by the PCB planes. In Fig. 12,
as expected, the parasitics of the capacitors increase the noise
as compared to ideal decoupling capacitors. However, the
capacitor parasitics help in attenuating the steady state noise
as compared to a bare PCB, as shown in Fig. 12. Comparing
Figs 6 and 12, it is clear that for a 1ns rise time current source,
the PCB planes have a significant effect on the core switching
noise. Hence for this current source, modeling the PCB planes
is far more critical than modeling the package planes. It can be
seen that the parasitics of the capacitors degrade the
performance of the decoupling capacitors. It can also be seen
that the steady state noise attenuates faster compared to the
case with no decoupling capacitors.


                                                                                   Fig.13 Core noise for the test vehicle
                                                                          From Figs 12 and 13, it is clear that both the on-chip
                                                                      capacitance and the PCB planes have a significant impact on
                                                                      the core noise. This is for the current sources in Figs 5 and 11.
                                                                      With faster current sources, it has been speculated from Figs 7
                                                                      and 8 that the package planes can have a significant impact on
                                                                      core noise. To answer this question, the models have been
                                                                      analyzed in the frequency domain in the next section.
                                                                      IX. Importance of on-chip capacitors
                                                                          The frequency response of the entire system was computed
                                                                      using the transient simulation models in Figs 12 and 13. The
                                                                      results are shown in Fig. 14. The model included the CBGA
                                                                      package and board plane layers and the board decoupling
         Fig. 12 Core noise with the package and PCB                  capacitors. No inductances for vias, C4s and solder balls were
                                                                      included in the model. The simulations were conducted with
VII. Core Noise with Package, PCB and On-chip                         an on-chip capacitance of 32nF and series resistance of
Capacitance                                                           6.3mΩ. The simulation was next repeated without any on-chip
    An on-chip capacitance of 32 nF with a series resistance of       capacitor. The self-impedance between ports 18 and 19 is
6.3mΩ was included into the integrated package and PCB                shown in Fig. 14. The figure shows three curves namely, i) the
models as discussed in the previous section. The PCB model            response of only the on-chip capacitor, ii) the response
included the parasitics of the decoupling capacitors. The             without the on-chip capacitor and iii) the response of the
model was simulated by monitoring the voltage between ports           entire system. In Fig. 14, the second peak for the entire system
18 and 19, the results of which are shown in Fig. 13. The             is caused by the chip-package resonance caused by the on-
inclusion of the on-chip capacitance decreased the 140mV              chip capacitance resonating with the package planes. The
peak noise in Fig. 12 to 80 mV in Fig. 13. In addition, the high
frequency oscillations have been smoothened. However, the


0-7803-7038-4/01/$10.00 (C)2001 IEEE                                       2001 Electronic Components and Technology Conference
frequency at which this occurs is the intersection point         described in Fig.1. From Fig. 15, it is clear that since the
between curves i) and ii) as shown in Fig. 14.                   package planes have resonances above 1GHz, they are
                                                                 completely suppressed by the on-chip capacitance, if the on-
                                                                 chip capacitance exceeds 30nF. The current ASIC trend of
                                                                 large on-chip intrinsic and added thin-oxide decoupling
                                                                 capacitance will continue into the future. This being the case,
                                                                 the package can be modeled as an inductance network by
                                                                 accounting for only the vertical via inductances and can be
                                                                 connected to a PCB network containing all the plane
                                                                 resonances, as described in this paper. This model approach is
                                                                 valid for future ASICs, as illustrated in Fig. 17.




       Fig. 14 Chip-package resonance

   From Fig. 14, beyond 500 MHz, the on-chip capacitance
dominates the frequency response and hence completely
suppresses all the plane resonances caused by the package.
Hence, it can be concluded that the bandwidth to be supported
by the package and board is from DC – 500MHz for the test
vehicle in Fig. 1.
   Assuming the same cross section, the self-impedance
frequency response between ports 18 and 19 for various on-          Fig. 16 On-chip capacitance vs. chip-package resonance
chip capacitors is shown in Fig. 15.



                                                                                                 High performance ASICs
                                                                                                       Package
                                                                                                       Modeled using PEEC


                                                                                                              Board Modeled using
                                                                                                              cavity resonators &
                                                                                                              PEEC (for vias)



                                                                     Fig. 17 Modeling of the package and board for future
                                                                                         generations
  Fig. 15 Chip-package resonance shifts with larger on-chip
                    capacitance values                           X. Conclusion
                                                                    In this paper a CBGA package on a test board was
   The chip-package resonance can be clearly seen in all the     simulated for computing the core switching noise. Initially, the
cases where the resonance shifts to a lower frequency as the     core noise produced by the CBGA package alone was
on-chip capacitance is increased. For an on-chip capacitance     investigated. It was observed that the inductance of vias, C4s
of 500nF, the chip-package resonance occurs at a very low        and solder balls contributed the maximum towards core noise
frequency indicating that the bandwidth to be supported in the   and the effect of the package planes was insignificant for the
package and board is < 190MHz. This is shown in Fig. 16,         0.5µm CMOS process used in this paper. However, it was also
where the chip-package resonance frequency has been plotted      observed that the effect of the plane resonances in the package
for various on-chip capacitance using the test vehicle


0-7803-7038-4/01/$10.00 (C)2001 IEEE                                  2001 Electronic Components and Technology Conference
dominated the response as the technology moved towards
higher performance. Next, the entire test vehicle including the
CBGA package and board was modeled and the effect of
decoupling capacitors on the noise was investigated. It was
seen that the parasitics of on-board decoupling capacitors
degraded the performance of the system. Finally, the
frequency response of the test vehicle was analyzed with
various on-chip capacitors. The simulation results showed that
on-chip capacitors completely dominated the response beyond
190MHz (for on-chip capacitance of 500nF), suggesting that
the package planes have little contribution towards core
switching noise. Based on this observation, a method that
simplified the models was suggested that accounted for the
package vertical inductances and the PCB lateral resonances
and vertical inductances.

XI. Acknowledgements
   This work was supported by the Semiconductor Research
Corporation under contract number 99 – NJ – 735.

XII. References
[1] J.P.Libous and D.P.O'Connor, "Measurement, Modeling,
and Simulation of Flip-Chip CMOS ASIC Simultaneous
Switching Noise on a Multilayer Ceramic BGA", IEEE Trans.
on Components, Packaging, and Manufacturing Technology,
Part B, Vol. 20, No. 3, pp.266-271, Aug. 1997.
[2] W.D.Becker, J.Eckhardt, R.W.Frech, G.A.Katopis,
E.Klink, M.F.McAllister, T.G "Measurement of Mid-
Frequency Simultaneous Switching Noise in Computer
Systems", IEEE Trans. on Components, Packaging, and
Manufacturing Technology, Part B, Vol. 21, No. 2, pp.157-
163, May 1998.
[3] Nanju Na, Jinseong Choi, Sungjun Chun, Madhavan
Swaminathan and Jeganathan Srinivasan, "Modeling and
Transient Simulation of Planes in Electronic Packages", IEEE
Trans. on Advanced Packaging, Vol. 23, No. 3, pp. 340-352,
August 2000.
[4] S.Chun, M.Swaminathan, L.Smith, Z,Iyer, "Physics-based
Modeling of Simultaneous Switching Noise in High Speed
Systems", IEEE 50th Electronic Components and Technology
Conference, pp. 760-768, May 2000.




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