FPGA-based Current Control of PWM Voltage-Source Inverters by arz13651

VIEWS: 52 PAGES: 10

									FPGA-based Current Control of PWM Voltage-Source Inverters                                   BELMANS Ronnie




             FPGA-based Current Control of PWM Voltage Source Inverters

                  K. De Brabandere, J. Van den Keybus, B. Bolsens, J. Driesen, R. Belmans
                                       K.U.Leuven ESAT / ELECTA
                                          Kasteelpark Arenberg 10
                                      3001 Leuven Heverlee, Belgium
                                tel: +32/16 32 10 20, fax: +32/16 31 19 85
                                Karel.DeBrabandere@esat.kuleuven.ac.be
                                   http://www.esat.kuleuven.ac.be/electa

Acknowledgements
The authors are grateful to the Belgian “Fonds voor Wetenschappelijk Onderzoek - Vlaanderen” for
its financial support of this work, to the Research Council of the K.U.Leuven for granting a concerted
research action supporting this research, and to Texas Instruments for its hardware support via the
ELITE university program. J. Van den Keybus holds a research scholarship of the Belgian “Instituut
voor de aanmoediging van Innovatie door Wetenschap en Technologie in Vlaanderen (IWT)”. B.
Bolsens holds a research scholarship and J. Driesen a postdoctoral research fellowship, both of the
Belgian “Fonds voor Wetenschappelijk Onderzoek - Vlaanderen”. The authors would also like to
thank R. Reeckmans for his valuable work in supporting the experimental work.

Keywords
Converter Control, Voltage Source Inverters, DSP, Sensorless Control, Real Time Processing.

Abstract
In this paper, a single-phase deadbeat digital current control algorithm using voltage source inverters
for grid-connected applications is presented. The controller is designed directly in the digital domain
using the method of Ragazzini. The line voltage is estimated by bandpass filtering the current error.
The development of a robust fast prototyping platform, consisting of a Field Programmable Gate
Array (FPGA) and a Digital Signal Processor (DSP), is discussed. The current control algorithm is
implemented on a Digital Signal Processer, while the Pulse Width Modulation (PWM) algorithm and
additional protection blocks are implemented in the FPGA. Both the simulations and the experimental
results validate the results of the theoretical analysis. Specific advantages of the proposed current
control algorithm include the fast and accurate deadbeat response, the robust operation and the
avoidance of the use of a line voltage sensor.

Introduction
Current controlled Pulse Width Modulated Voltage source Inverters have a wide range of applications
in variable speed drives, distributed generation and power conditioning systems, such as active power
filters. Various modulation strategies and control algorithms have been developed [1]-[3]. The various
techniques to control the current in a voltage source inverter can be roughly classified as hysteresis,
ramp comparison and predictive current controllers. While hysteresis control is traditionally
implemented using analog components, enabling fast response and high bandwidths, predictive
controllers have mostly been implemented digitally. Microprocessors and Digital Signal Processors
(DSPs) have been widely adopted for the design of digital current controllers.
Field-Programmable Gate Arrays (FPGAs) allow rapid prototyping of digital systems. The FPGA
realization of PWM current control strategies provides advantages such as fast prototyping, simple
hardware and software design, higher switching frequency and reduction of the computational load of
the DSP. Recently, it has been shown that through increasing the sampling frequency it is even
possible to implement Hysteresis Current Control digitally, by using a FPGA [4].




                                                                                                       1

EPE 2003 - Toulouse                                          ISBN : 90-75815-07-7                       P.1
FPGA-based Current Control of PWM Voltage-Source Inverters                                                        BELMANS Ronnie




This paper desribes a single phase deadbeat predictive current control algorithm. Applications include
active power filters and distributed generation. Advantages of the presented current control algorithm
include very fast deadbeat response, and the ‘sensorless’ estimation of the line voltage, which makes
an accurate line voltage measurement redundant. The line voltage is estimated relying solely on the
difference between estimated and measured current.

Methods
Basic circuit description
The basic circuit of a voltage source-inverter supplying a single-phase load is shown in figure 1. The
load is modelled as a series of a back-EMF e, an inductance L and a resistance R:
                                                 di
                              u = Ri + L            +e.                                                                   (1)
                                                 dt
where u and i are the output voltage and the output current of the inverter, respectively. Depending on
the state of the inverter switches, the inverter output voltage u equals uDC, -uDC or 0.

The current error is defined as
                                     ie = i * −i.                                                                         (2)

where i* is the reference current. Neglecting the small product R ie, substitution of (2) into (1) yields
                                    die
                                L       = u * −u ,                                                                        (3)
                                    dt
where
                                             di *
                           u* = e + L             + Ri*                                                                   (4)
                                              dt
is the desired inverter output voltage.

The purpose of the current controller is to regulate ie to zero. In general, u differs from u*. According
to (3), this means that the derivative of ie differs from zero and thus ie can not be kept constant. Using
Pulse Width Modulation (PWM), u is modulated so that on average it equals u*, such that also the
average of ie can be controlled to equal zero.




                                    Figure 1: Basic circuit of a voltage source inverter with single-phase load




                                                                                                                            2

EPE 2003 - Toulouse                                              ISBN : 90-75815-07-7                                        P.2
FPGA-based Current Control of PWM Voltage-Source Inverters                                                                       BELMANS Ronnie




Deadbeat digital current control
Zero-order hold equivalent
In digital current control, current is measured and the control input is updated at discrete time instants.
The transfer function of the controller is directly computed in the discrete domain. Therefore, the
continuous model of the load (1), must first be transformed to the discrete domain. There are many
approaches for finding a discrete transfer function with approximately the same characteristics as the
continuous function. As the control input is updated only once during every sample time and remains
constant during that sample time, the best approach is the zero-order hold equivalent. Moreover, it can
be shown that, for a sampled data system, if the output value is measured and the control input is
updated at the same discrete instants, the zero-order hold (ZOH) equivalent is an exact representation
of the continuous system. The ZOH equivalent HZOH(z) of H(s) is given by

                                            z − 1  H ( s) 
                      H ZOH ( z ) =              Ζ        .                                                                            (7)
                                              z  s 
Using this formula, the ZOH equivalent of the system described by (1) is found as
                                                         − RTs
                                       1 1− e L
                         H ZOH ( z ) =       − RTs
                                                   .                                                                                     (8)
                                       R
                                         z −e L
Measurement and calculation delay
In figure 2, three possible systems are considered. The first system, figure 2 (a), is valid if
measurement and calculation require an infinitely short time. In practice, the applicability of this
representation is limited to those systems where measurement and calculation time is much shorter
than the sampling time of the system. The second system, represented in figure 2 (b), considers a
calculation time equal to the sample time T. This corresponds to the majority of the digital systems.
The calculation delay incorporates the measurement delay, as long as the sum of measurement and
calculation time is smaller than the sample time. In some systems, this is not the case and
measurement delay approaches one sample time. Such a system is modeled by figure 2 (c).

                                                                                                   (1-exp(-R*Ts/L))/R
                                                                 K(z)
                               ref erence                                                           z-exp(-R*Ts/L)      output




                                                                                             (a)


                                                                                        1          (1-exp(-R*Ts/L))/R
                                                                 K'(z)
                               ref erence                                                z          z-exp(-R*Ts/L)      output




                                                                                          (b)


                                                                                        1          (1-exp(-R*Ts/L))/R
                                                                 K''(z)
                               ref erence                                                z          z-exp(-R*Ts/L)      output


                                                                                        1
                                                                                         z

                                                                                             (c)



  Figure 2: digital current control system: (a) without delay, (b) with calculation delay, (c) with measurement and calculation
                                                               delay.




                                                                                                                                           3

EPE 2003 - Toulouse                                                       ISBN : 90-75815-07-7                                              P.3
FPGA-based Current Control of PWM Voltage-Source Inverters                                                     BELMANS Ronnie




Deadbeat control
A deadbeat current control algorithm [5],[6] calculates the voltage to be generated by the inverter so
as to make the current reach its reference by the end of the following sample time period. The system
settles to its reference value in the shortest time possible. For deadbeat control, all poles of the closed
loop transfer function are placed at z = 0. In that case, the system will settle in a finite number of
sample periods, equal to the order of the denominator. This way, K(z), K’(z) and K’’(z) can be
calculated, by equating the closed loop transfer function to 1/z, 1/z2 and 1/z2 respectively (direct
design method of Ragazzini [7]). This results in:
                                      − RTs 
                           R z − e            
                                          L              R          R                   K
               K ( z) =                             =       − RTs
                                                                   +          = Kp + i ;                              (9)
                                − RTs
                                                                    z −1                z −1
                          1 − e L (z − 1)             1− e L
                                        
                                        
                                           − RTs 
                                R z − e          z
                                             L                  z
               K '( z) =                                  =          K ( z) ;                                        (10)
                                  − RTs
                                                              z +1
                           1 − e L ( z − 1)( z + 1)
                                         
                                         
                                             − RTs  2
                                  R z − e           z
                                                L                        z2
               K ''( z) =                                         =               K ( z)                             (11)
                                   − RTs
                                                                      z 2 + z +1
                            1 − e L ( z − 1)( z + z + 1)
                                                     2
                                          
                                          
The first system will settle within one sample time period in response to a step input, while the second
and third system will settle after two sample time periods. K(z) is in fact a Proportional Integral (PI)
regulator with proportional gain Kp and integral gain Ki defined as in (9). For RTs/2L much smaller
than 1, Kp approximates L/Ts.

K’(z) is the product of K(z) with z/(z+1), which compensates for a delay of one sample period in the
feedback loop. K’’(z) incorporates the factor z2/(z2+z+1) which compensates for a delay of two
sample periods in the feedback loop. For further analysis we will only consider the system of figure 1
(b), as this corresponds to the system used during the experiments.
Rearrangement of the controller
K’(z)(iref-imeas) can be rewritten in a feedforward path and a feedback path as follows
               K ' ( z )(iref − imeas ) =                   K ( z )(iref − imeas )
                                                         z
                                                       z +1
                                                                                                           .         (12)
                                                       z −1                  z           1              
                                               =            K ( z ) iref +       K ( z ) 2 iref − imeas 
                                                         z                 z +1         z               
The feed forward path incorporates the regulator effort due to a change in the reference value, while
the feedback path will correct the error due to imperfect parameter modeling, due to noise on the input
value and due to noise on the measured current.
Back-emf compensation
In grid-connected applications, there is a large noise on the input value due to the line voltage e (1).
This noise is not gaussian, but periodic with a fixed frequency and amplitude, and thus it can be
compensated for, if the exact value is known. One way to obtain the exact value, is by measuring the
voltage. An alternative solution is estimating the back-emf through observing and bandpass filtering
the current error. This approach eliminates eventual voltage measurement problems (e.g. limited
accuracy, spikes), or a phase shift due to the use of a low pass filter for the voltage measurement. As



                                                                                                                         4

EPE 2003 - Toulouse                                                  ISBN : 90-75815-07-7                                 P.4
FPGA-based Current Control of PWM Voltage-Source Inverters                                                                           BELMANS Ronnie




such, the observer-based approach can be considered as a ‘sensorless control’. The system with the
sinusoidal noise on the input of the plant and compensation Kw(z) is shown in figure 3.
                                                                           z-1
             ref erence                                                     z
                                        1
                                        z2
                                                                            z                                  1              1
                                                         Kw(z)                                    K(z)
                                                                         z+1                                   z             L.s+R    output




                  Figure 3: System with Kw(z), which compensates for the sinusoidal noise on the input of the plant.

K’(z) is as calculated in previous section. Kw(z) compensates for the 50 Hz sinusoidal noise on the
input of the plant by isolating and amplifying the 50 Hz component in the measured current error:
                                            β ( z − 1)       z2
               Kw( z ) =                                                  .                                                                (13)
                                             z + β z 2 − 2 cos(ωT ) z + 1
Kw(z) contains an undamped bandpass filter with center frequency f = ω/2π = 50 Hz, working as an
integrator for the 50 Hz component. Kw(z) has two complex poles in the z-plane at z = ejωT and
z = e-jωT. The two zeros at z = 0 compensate for the poles of the inner loop transfer function (see
previous section). To prevent instabilities, the total closed loop transfer function may not contain any
poles outside the unit circle. It can be shown that for β between 0 and 1, the system presented by
figure 3 has no closed loop poles outside the unit circle, and thus the system is stable. The value uest =
Kw(z)K’(z) is an estimate of the sinusoidal noise on the input of the plant.

In figure 4.a, the performance of the back-emf estimator with measurement noise (gaussian, σ = 100
mA) is shown for β = 1, while in figure 4 (b), the performance is shown for β = 0.05. By choosing β
= 1, the sinusoidal noise will be compensated for very fast, but measurement noise will degrade the
system performance. By choosing β close to zero, measurement noise has negligible influence, while,
on the other hand, it takes some time before the estimator tracks the sinusoidal noise. In most
applications , the amplitude of the sinusoidal noise input varies only slowly and a small β is preferred.

                                        400


                                        200
                          voltage (V)




                                             0


                                        -200


                                        -400
                                                 0   5     10    15   20           25        30      35   40       45   50
                                                                             (a) time (ms)


                                        400


                                        200
                          voltage (V)




                                             0


                                        -200


                                        -400
                                                 0   5     10    15   20           25        30      35   40       45   50
                                                                             (b) time (ms)



                      Figure 4: back-emf estimator uest = Kw(z)K’(z) with measurement noise: (a) β = 1, (b) β = 0.05.




                                                                                                                                               5

EPE 2003 - Toulouse                                                   ISBN : 90-75815-07-7                                                      P.5
FPGA-based Current Control of PWM Voltage-Source Inverters                                            BELMANS Ronnie




Results
Experimental platform setup
The experimental platform consists of an FPGA (Altera EP1K100) in combination with a DSP (Texas
Instruments TMS320C6711) [8]. Communication between the DSP and the FPGA occurs through a
32-bit data bus. The FPGA drives three half bridges, so that as well a one-phase as a multi-phase
voltage source inverter can be composed. Current measurements take place through 12-bit AD-
converters (ADCs) at a sample time frequency of up to 500 kHz (figure 5).
The platform is conceived so that the FPGA executes the high frequency, low latency tasks, which
relieves the DSP for more complex, less interrupt-intensive tasks. The FPGA plays an important role,
being the interface between DSP, ADCs and the voltage source inverter. The modular approach
makes it possible to implement many additional features, such as additional protection blocks to
safeguard the voltage source inverter. The use of the VHDL programming language fully supports the
modular approach of the FPGA blocks. Additional protection blocks with maximum switching
frequency limitation, dead-time generation and overcurrent and DC-bus overvoltage detection are
implemented in the FPGA. Thanks to the combination of this protection blocks, the voltage source
inverter is completely protected. Any experimental, even preliminar, current control algorithm can be
tested in practice without any danger for destruction of the voltage source inverter.




                                                             Figure 5: Experimental platform setup.

Carrier-based pulsewidth modulation
The current control algorithm is implemented in the DSP, while the pulsewidth modulation (PWM) is
implemented in the FPGA. Up to three half bridges can be driven, using one carrier modulator.
Hereto, up to three compare signals are needed from the DSP. A fifth signal controls the period time
of the carrier modulator and thus the switching frequency. Every half carrier modulator period, both
the period time signal and the compare signals, as received from the DSP, are updated inside the
FPGA. This approach allows to control the half bridge switches at a frequency twice the switching
frequency. Moreover, also the switching frequency of the half bridges can be dynamically changed
during operation. In figure 6, carrier based pulsewidth modulation is shown for a three phase system.
The three compare values, are cmp0, cmp1 and cmp2, while the period time is determined by lmt. As
can be seen from the figure, these values are updated every half PWM carrier time period. At t3, also
lmt is changed, which results in a modified switching frequency.




                                                                                                                6

EPE 2003 - Toulouse                                                     ISBN : 90-75815-07-7                     P.6
FPGA-based Current Control of PWM Voltage-Source Inverters                                                          BELMANS Ronnie




     Figure 6: Carrier based pulsewidth modulation for a three phase system: (a) carrier with compare and limit signals, (b)
                                   reference and real current through one of the three phases.

Current measurement is synchronised with the carrier modulator. Every half PWM carrier time
period, whenever the compare signals of the PWM are updated, also the current is sampled through
the ADCs. As the current is sampled in synchronism with the PWM carrier, no aliasing occures [3].
As can be seen from figure 6 (b), at the sample instants the measured current is constant, even though
a large current ripple exists between the sample instants. Moreover, the measured current represents
the average of the real current. Whenever the current measurement data has been received by the
FPGA from the ADC, the FPGA sends an interrupt to the DSP indicating that a new current sample is
available. Inside the DSP, the current control loop is synchronised to and initiated by this interrupt.
Subsequently, the measured current data is read from the DSP and compared with the reference value,
the output of the digital current controller is calculated, and the output is send as a compare signal to
the FPGA. When a new half PWM carrier time period starts, this compare signal is reloaded into the
Pulse Width Modulator, while a new current value is sampled through the ADCs. If the current
control loop is fast enough to update the compare signals in the FPGA before a new half carrier period
has been started, the delay of the digital current controller is limited to one sample time period
(equalling half a switching time period). If the current control loop requires more time, the delay is
doubled and equals two sample time periods or one switching time period. By this approach the
current control bandwidth is maximised.

The strategy is tested using a one-phase application, consisting of an inductor and a resistor in series
with the line voltage (figure 1). Only two of the inverter half bridges are used. This topology is typical
for e.g. a single phase active filter or a distributed generation unit. The current control loop is based
on the deadbeat digital current control loop, as described before. The FPGA receives two signals from
the DSP, namely cmp0 and cmp1. For minimal current ripple, both signals have at all instants same
magnitude but opposite sign. A constant frequency is used, and the lmt signal is send only once at
startup.

For high bandwidth current control, the current control loop must be executed at high sample rate.
Although the program code is relatively simple for the DSP, the DSP is highly burdened because
overhead increases linearly with sample frequency. It would be better to relieve the DSP from the



                                                                                                                               7

EPE 2003 - Toulouse                                          ISBN : 90-75815-07-7                                              P.7
FPGA-based Current Control of PWM Voltage-Source Inverters                                                          BELMANS Ronnie




current control task, so that the DSP can be used for the task it is meant for: complex computations at
relatively low execution frequency. As the current control loop should have the highest possible
bandwidth, the current controller is a perfect candidate for implementation in the FPGA. However,
during the prototyping phase, the best option is to implement the current controller in the DSP, as
control algorithms can be much easier programmed, adapted and debugged with C or Matlab in the
DSP, than with VHDL in the FPGA. Because of this reason, the current control algorithm as
presented in this paper has first been implemented in the DSP. Future work involves the
implementation of the deadbeat current control algorithm in the FPGA instead of the DSP.
Simulation and experimental results
The system shown in figure 3 has been simulated using Matlab/Simulink. Measurement noise is
assumed to be gaussian with standard deviation of 50 mA. L equals 4.25 mH while R = 9 Ω. The
back-emf has a frequency of 50 Hz and rms value of 230 V. Sample frequency is 10 kHz. The
reference signal is a square wave signal with amplitude 1 A and a frequency of 100 Hz. β equals 0.5.
In figure 7, the results of the controller are shown. During the first period a relative large current error
exists due to the imperfect estimation of the back-emf voltage. Gradually, this error reduces as the
back-emf is estimated more accurately, and after about one period time, the estimation error is
negligible.

                                   2


                                   1
                     current (A)




                                   0


                                   -1


                                   -2
                                        0   5   10           15   20         25          30   35   40    45        50
                                                                       (a) time (ms)


                              400


                              200
           voltage (V)




                                   0


                           -200


                           -400
                                        0   5   10           15   20         25          30   35   40    45        50
                                                                       (b) time (ms)



  Figure 7: Simulation result of the deadbeat digital current controller with back-emf estimation (a) reference current (blue),
           and measured current (green), (b) real back-emf voltage (blue) and estimated back-emf voltage (green).

Figure 8 shows the experimental results of the current control as implemented in the DSP in
combination with the carrier-based modulator in the FPGA. The inverter feeds the 100 Hz block
signal into the grid through a coil in series with a resistance. Sampling frequency is again 10 kHz and
switching frequency is 5 kHz. The dc-bus voltage during the experiment is 500 V. The rms value of
the line voltage is 208 V. Figure 8 (a) shows the reference current, the measured current and the
current as seen through the DSP. The real current shows a large 10 kHz component due to the
switching frequency. The measured current does not exhibit this 10 kHz component as sampling


                                                                                                                                  8

EPE 2003 - Toulouse                                               ISBN : 90-75815-07-7                                            P.8
FPGA-based Current Control of PWM Voltage-Source Inverters                                                           BELMANS Ronnie




occures at 10 kHz in synchronism with the switching frequency (see previous section). There is
however a small difference between the average of the real current and the measured current. This is
explained by a small time offset between the carrier modulator and the switching time instants. Except
for this small offset, the average current is regulated very accurately, despite the very large ripple, due
to the very high dc-bus voltage, a relatively low switching frequency and a relatively small inductor.
This result confirms the high performance of the presented current control technique.

                                   5
                     current (A)




                                   0




                                   -5
                                        0   2   4            6   8         10           12   14   16     18        20
                                                                     (a) time (ms)


                              400


                              200
           voltage (V)




                                   0


                           -200


                           -400
                                        0   2   4            6   8         10           12   14   16     18        20
                                                                     (b) time (ms)



      Figure 8: Experimental result of the deadbeat digital controller with back-emf estimation (a) reference current (blue),
      measured current (green, dotted), and current as seen through the oscilloscope (magenta), (b) estimated line voltage.

As can be seen from simulation and experimental results, the reaction time of the controller to a
current reference change is very short. In theory (perfect modelling, no measurement noise), it takes
two sample time periods to reach the reference setpoint (deadbeat response). In the experimental
results a small deviation at a frequency of 250 Hz can be observed. This is due to the existence of a
fifth harmonic in the line voltage, which is not compensated for. If necessary, this component could
also be estimated and compensated for in the same way as is done for the 50 Hz component. In figure
8 (b) the estimated line voltage is shown.

Conclusions
A digital deadbeat current controller for grid-connected applications using a voltage source inverter,
has been presented. The current control algorithm has been implemented in a DSP. A FPGA
constitutes the link between the DSP and the voltage source inverter. By the combination of the DSP
and FPGA an extremely flexible fast prototyping platform is realised. The use of the FPGA enables
the implementation of a combination of protection blocks in software, such as to make the inverter
full-proof against destruction of the half bridge switches. Furthermore, the carrier-based PWM
scheme is implemented in the FPGA. The proposed digital deadbeat current controller exhibits a very
fast accurate deadbeat response at severe conditions, obtained by a high dc-bus voltage, a low
switching frequency and a small inductor. Moreover, measurement of the line voltage is not needed,



                                                                                                                                9

EPE 2003 - Toulouse                                              ISBN : 90-75815-07-7                                           P.9
FPGA-based Current Control of PWM Voltage-Source Inverters                                        BELMANS Ronnie




as the back-emf voltage is estimated inside the controller. This current controller is primarily intended
for grid-connected applications, such as active power filters or distributed generation units.

References
[1]        D. M. Brod and D. W. Novotny, “Current control of vsi-pwm inverters,” IEEE Transactions on
           Industry Applications, vol. 21, no. 4, pp. 562-569, May/June 1985.
[2]        M. P. Kazmierkowski and L. Malesani, “Current Control Techniques for Three-Phase Voltage
           source PWM Converters: A Survey,” IEEE Transactions on Industry Applications, vol. 45, no.
           5, pp. 691-703, October 1998.
[3]        J. Holtz, “Pulsewidth Modulation for Electronic Power Conversion,” Proceedings of the IEEE,
           vol. 82, no. 8, pp. 1194-1214, August 1994.
[4]        K. De Brabandere, J. Van den Keybus, B. Bolsens, J. Driesen, R. Belmans, “Sampled-data
           dual-band hysteresis current control of three-phase voltage source inverters,” 15th international
           conference of electrical machines (ICEM), Brugge, Belgium, nr 386, August 25-28, 2002.
[5]        T. Kawabata, T. Miyashita, Y. Yamamoto, “Dead Beat Control of Three Phase PWM
           Inverters,” IEEE Transactions on Power Electronics, vol. 5, no. 1, pp. 21-28, January 1990.
[6]        L. Malesani, P. Mattavelli, S. Buso, “Robust Dead-beat Current Control for PWM Rectifiers
           and Active Filters,” IEEE Transactions on Industry Applications, vol. 35, no. 3, pp. 613-620,
           May/June 1999.
[7]        G. F. Franklin, D. J. Powell, M. L. Workman, D. Powell, Digital Control of Dynamic Systems,
           3rd ed., Addison-Wesly Pub, Reading, MA, USA, 1997.
[8]        J. Van den Keybus, B. Bolsens, K. De Brabandere, J. Driesen, R. Belmans, “DSP and FPGA
           based platform for rapid prototyping of power electronic converters and its application to a
           sampled-data three-phase dual-band hysteresis current controller,” 33rd Power Electronics
           specialists conference (PESC), Cairns, Queensland, Australia, June 23-27, 2002.




                                                                                                          10

EPE 2003 - Toulouse                                          ISBN : 90-75815-07-7                            P.10

								
To top