ESD protection in deep submicron CMOS technology -- Does the transient matter? Kin P. Cheung and Avid Kamgar Bell Laboratories, Lucent Technologies, Murray Hill, NJ, 07974 USA email@example.com Abstract more traps in the gate-oxide than the entire ESD event clamped at the holding voltage. Common ESD protection devices have a This prediction has serious consequences in snap-back characteristic similar to a silicon- ESD protection design because majority of the control-rectifier. The transient voltage existing designs will have to be abandoned. required to trigger these devices usually is not However, Cheung's prediction is based on data an important design criterion as long as it is collected at long term stress experiments. not too high. We show that when gate-oxide is Whether or not the trap generation process thin, this voltage transient creates far more remains the same when the stress is in sub- defects in the gate-oxide than the main ESD nanosecond time scale is still an open event clamped at the holding voltage. Due to question. In this work, we experimentally difficulty in measurement, this oxide reliability demonstrate that the trap generation rate as a degradation can lead to chip failure but not function of stress voltage remains unchanged show up in simulated ESD test. at very short time scale. 1. Introduction 2. Experimental ESD damages are mostly high current related. Voltage related damage modes such as 0.5ns/div Gate-oxide breakdown are less often encountered. As gate-oxide gets thinner, however, gate-oxide degradation and breakdown becomes increasingly important. To guard against such failure, ESD design 1V/div must limit the voltage experienced by the affected circuits during an ESD event. In a recent paper, Ameraseka et al  argued that the critical voltage level that must be controlled in a snap-back protection device is holding voltage, not trigger voltage. Their Fig. 1. Oscilloscope trace of the 500ps (full explanation was that the trigger voltage, width at half maximum) stress pulse. Scope although higher by several volts or more, is rise time is 300ps and pulse rise time is <=200ps. The convoluted rise time is 360ps. not important because the time spent at the trigger voltage is very short (<0.5ns). More recently, Cheung , using reported 10x0.252 NMOS transistors were used in  stress voltage-dependent trap-generation the experiment. Gate-oxide thickness was 15Å (physical, 23Å electrical). 5V, 500ps (FWHM) rate, showed that the short transient, even pulses were applied to the gate through a when it is only 3 volts higher than the holding transmission line arrangement to ensure (and voltage, will generate orders of magnitude to verify) that the pulse height and shape 1.0 0.5 Bias: negative remain unaltered at the gate. Fig. 1 shows the 0.0 Pulses: positive 5V scope-limited trace of the stress pulse. The ln[-ln(1-F)] -0.5 actual rise and fall time of the pulses are -1.0 <=200ps. The experiment is constant voltage -1.5 TDDB with pulsed pre-stress. The pre-stresses -2.0 0Vbias/1kp were 1 pulse with -2.5V bias on -2.5 1Vbias/1kp 1.5Vbias/1kp source/drain/well, 1000 pulses with -1.5V, -1V -3.0 base line and 0V bias on source/drain/well. So the actual -3.5 2.5Vbias/1p voltages across the gate-oxide are 7.5, 6.5V, -4.0 0.5 1 1.5 2 2.5 3 6V and 5V. For each pulse, the log(t) [seconds] source/drain/well bias is on for only 2ms. It is assumed that the negative stress due to the bias Fig. 3. TDDB distribution at 3.6V after various during the pulse-off time has negligible effect pre-stress conditions. The 0V bias data is on the TDDB lifetime. As a base line, TDDB indistinguishable from base line except the for 100 devices were performed at 3.6V abrupt deviation at low percentile range. All without pulsed pre-stress. All post-pulsing other pre-stresses cause gradual increases in deviation from base line as we move to lower stresses are also performed at 3.6V. Fig. 2 percentile. shows the various stress conditions. 100ps From the base line distribution, we determined that the Weibull slope for the particular oxide is 1.11 and that the median time to breakdown is 300s. We estimated, from data in reference 4, that the critical trap 5.5V density at 50% breakdown probability of our devices is 2.24E16/cm3. With these quantities, 3.6V we constructed the time to breakdown distributions for various levels of pre-existing traps. 500ps 2 No latent traps 1 1E13.4 latent traps 0 1E15.3 latent traps ln(-ln(1-F)) Fig. 2. Various pulse pre-stress conditions. 1E15.9 latent traps The pulses are shifted higher by biasing the -1 source/drain/well of the transistor negatively. -2 3.6V is the post-pulse TDDB stress voltage. -3 5.5V is where the voltage acceleration factor changes value according to . -4 Ncrit (F=0.5)=1E16.35 -5 3. Results and discussions 0.5 1 1.5 2 2.5 3 log(t) [seconds] Fig. 3 shows the results of all the Fig. 4. Simulated TDDB distribution with measurements. It is clear that all pre-stresses various latent (pre-existing) traps. The no latent trap distribution uses parameters degraded the gate-oxide breakdown appropriate for the oxide sample in the distribution, particularly at the low percentile experiment. region. To analyze the results more quantitatively, we compare it to simulations as Fig. 4 shows the simulated breakdown described below. distributions with pre-existing trap densities of 2.5E13, 2.0E15 and 7.94E15. These values are chosen to simulate the observed breakdown devices, using scaling relations (fig. 5) and the distributions. As we can see, if significant base line data, to be 8.8s. Since an ESD amount of pre-existing trap exist, the event typically lasts less than 0.3s, a holding breakdown distribution will deviate from the voltage of 3.6V is more than adequate to virgin distribution at the low percentile range. protect the circuit from being damaged, if no This deviation increases gradually. transient exist. In fig. 3, breakdown distribution of the 0V On the other hand, a single 7.5V, 500ps bias pre-stress case follows closely the base pulse causes about 5% of the 2.52 devices to line distribution. The abrupt deviation at the fail. Scaling to the 10,0002 devices, the low end is not consistent with simulation and failure rate would be close to 100%. We have may be just noise due to limited samples. The thus demonstrated, experimentally, that a distribution for all other cases show gradual trigger voltage of 2.9V over the 3.6V holding increase in deviation, consistent with high voltage will seriously damage the circuit with level of pre-existing traps. 15Å thick gate-oxide under protection. It has been reported  that the voltage If we assume that the trigger transient is acceleration factor is about 4.7dec/V at 1000 times shorter than the ESD event, we can between 3 to 5.5V and about 2dec/V at 6V and estimate that the maximum trigger voltage above. We expect, therefore, that for our 500ps excursion to be 0.67V (based on the 4.5dec/V pulses, most of the traps are generated within acceleration factor). Above that, the trigger the ~100ps around the peak. Thus, 1000 pulses transient will be the dominant trap generation is equivalent to 100ns of stress. When we use process. In other words, we determined, for this value and the simulation to calculate the 15Å thick gate-oxide, the holding voltage acceleration factors that will fit our data, we could be slightly more than 3.6V while the come away with acceleration factors of trigger voltage could be 4.4V. Such low ~4.5dec/V at between 3 to 5V, ~2.1dec/V at trigger voltage is difficult to achieve in most between 5 to 6V and 1.3dec/V at between 6 designs. and 7.5V. We therefore conclude that the trap Interestingly, similar estimation suggest that generation mechanism remains unchanged at even when the oxide is not so thin, a trigger sub-nanosecond stress. excursion of more than 1.5V (based on 2dec/V acceleration factor) will dominate the trap b ln (1 - F1 ) æ t1 ö generation. Note that the voltage acceleration Failure fraction: =ç ÷ ln (1 - F2 ) ç t 2 ÷ factor levels off at voltages beyond 6V. The è ø 1.5V maximum excursion thus applies to a 1 t: time to breakdown large range of oxide thickness. æ ö Area: t1 = ç A2 ÷ b F: failure fraction It is important to recognize that the t2 ç A1 ÷ è ø A: area requirement for gate-oxide reliability is b: Weibull slope 100ppm failure in 10 years of operation. This requirement can be translated to a well-defined Fig. 5. Scaling relationships of Weibull critical trap density, which normally builds up statistics. slowly over the oxide lifetime. If the voltage stress during an ESD event creates a trap During an ESD event, a voltage pulse is density in the oxide equal to a significant presented to all devices connected to the I/O fraction of the critical trap density, the time to pad where the event occurs. The total active build up the critical trap density during area affected can be rather large. If a large operation will be less than 10 years. The circuit with 0.1cm2 total active area has 1000 circuits will no longer meet reliability I/O pads, then it is reasonable to think that specification. each I/O pad may affect about 10,0002 of To determine if the ESD event has degraded active area. At 3.6V stress, we calculated the the oxide to such an extent or not, the common time to 100ppm failure for the 10,0002 method of using simulated ESD events to test ESD design would not work. To assure that the failure rate is below 100ppm, the number of tests must be more than 10,000. In addition, most device-under-test (DUT) has too small an active area. When area scaling is taken into account, the number of tests required will be much higher. The problem is worse when the oxide is thin. When the Weibull slope is small, the area scaling effect is larger. Using our 15Å oxide as an example, if the DUT has an active area of 102, one must test over 10 million DUTs before there is enough statistic to experimentally demonstrate that the 10,0002 devices has a failure rate of less than 100ppm. Since normal ESD test is done only on limited samples with relatively small size, the oxide degradation is not normally detectable. As a result, one may wrongly conclude that the ESD design is adequately protecting the gate- oxide. To get around this test difficulty, one can measure the voltage waveform and rely on the known voltage acceleration factor to calculate the level of damage created in the oxide. Our experiment reported here demonstrated the soundness of this approach. 4. Conclusions We demonstrated that the physics of gate- oxide degradation under stress remains valid at sub-nanosecond time scale. The prediction that the trigger transient dominates trap generation during an ESD event is experimentally proven. For ultra-thin oxide, the normal ESD test method is inadequate to determine if the gate- oxide is degraded beyond acceptable level or not. The actual damage can be calculated from measured ESD waveform on the DUT. 5. References  A. Amerasekera et al, IRPS-99, p159.  K. P. Cheung, EOS/ESD Symp.-99, p38.  J. H. Stathis et al, IEDM-98, p167.  R. Degraeve et al, TED-45(4), 904(1998).