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System Interconnection Design Trade-offs in
Three-Dimensional (3-D) Integrated Circuits
Roshan Weerasekera
roshan@kth.se
Department of Electronics, Computer, and Software Systems
School of Information and Communication Technologies
The Royal Institute of Technology (KTH)
164 40 Kista, Stockholm, Sweden.
Presentation Outline
3-D Integration: what, why and when ?
Thesis Focus and Contributions
− Electrical Modelling and Analysis of 3-D IC interconnects
− Signalling techniques for on-chip global interconnects
− Cost, Performance and Technological Tradeoffs for 3-D Integration
Conclusions
RW, December, 2008 2
3-D Integration: What, Why and When ?
Stacking two or more planar modules/chips/dies and electrically connecting them
Wiring Around Packages Wiring Around dies Wiring through dies
(Package in/on Package) (Multi Die Packages) (Silicon Stacking)
Chip 2
Chip 1
Source: http://imec.be/wwwinter/mediacenter/en/SR2006/681542.html
http://www.solid-state.com/display_article/257485/5/none/none/Dept/Mapping-progress-in-3D-IC-integration
RW, December, 2008 3
3-D Integration: What, Why and When ?
• Interconnect Delay
• More Transistors • Power Consumption
• Increase device density • Increased Die Size • Noise
• Improve Functionality • Mixed Technologies • Temperature
• Complexity
• Disparate Technologies
System-on-Chip
Cost per function
Time to market
System in Package
And 3-D packaging
System Complexity
SiP and 3-D packaging allows incorporation
of other circuit elements such as MEMS,
optoelectronics and bio-electronics into the
package reducing system cost and improving
performance…..
RW, December, 2008 4
3-D Integration: What, Why and When ?
Higher Integration Density Shorter Interconnects
• Direct Vertical Communication
• Integration in horizontal and vertical
directions – Shorter Global/Chip-to-Chip
interconnects
• Smaller footprint
– Reduced number of global interconnects
• Less Resistance and Capacitance
– Less power consumption
– Higher performance
Heterogeneous Integration Short Time to Market
• Exploits the best process technologies for • Can use optimized standard already
fabrication of different functional blocks available products from different vendors
– No yield compromise
– Greater functionality
RW, December, 2008 5
Challenges for 3-D Integration
• Interconnections
Manufacturing • Alignment and bonding
• Signal, Power and Clock Interconnect design
Design • Thermal Management
• CAD Tool
Testing • Pre/post-bond testing
RW, December, 2008 6
Ramifications of 3-D Stacking
Basically two categories:
− Folding
− Stacking (Package and Wafer Level)
Source: http://www.rpi.edu/~luj/
RW, December, 2008 singh,”3D Packaging Developments and Trends”, 2005
Source: Inderjit 7
Major 3-D bonding methods ...
3D Die Stacking (System in Package)
3D Wafer-Level-Processing
− 3D-W2W bonding
− 3D-D2W bonding
Source: Eric Bayne, ” 3D Interconnection and Packaging”, 2006
RW, December, 2008 8
Layer-to-Layer Interconnection technologies
Wire bonding
Through-hole Via
Contactless
Lower Cost Short path length (in m range)
Higher Reliability Many connections
Suitable for stacking identical chips
Interconnects at any point
Long Chip-to-Chip connection
Limited in Numbers High cost
Unsuitable for stacking different size chips Test is more difficult
High frequency operation
Source: http://techon.nikkeibp.co.jp/article/HONSHI/20061122/124183/
RW, December, 2008 9
Thesis Focus and Contributions
Primary focus of this dissertation is the design, modelling and analysis of
system interconnection and their effects in massively integrated 3-D ICs.
Technical Contributions
1. Electrical modelling of Interconnects in 3-D ICs
2. Signalling techniques for global on-chip interconnects
3. Cost, performance and technological trade-offs for 2-D and 3-D ICs
RW, December, 2008 10
1. Electrical modelling of Interconnects in 3-D ICs
RW, December, 2008 11
Interconnect Modelling
The parasitic parameters of interconnects in ICs have complex field dependence
predicated on the physical geometry, and the material constants.
Parasitic information will allow circuit simulations for SI and delay from package
pins to internal circuit pins for a wide variety of physical configurations
Interconnect
Structure
Specifications
Structure Model in a
Accurate, Time and Field Solver Models for Parasitics
memory consuming, (eg: Table-Based, formulae)
Inefficient for full chip
extraction
Efficient, but not
Parasitic Extraction 100% accurate
SI, Delay and PI
Analysis
RW, December, 2008 12
Interconnects in 3-D ICs
Multilevel Wiring Structures
- Models already proposed in literature
(discussed in Chapter 2)
R, L,C Models for Coupled TSVs
-Not available so far in literature.
(Discussed Chapter 3)
Models for interconnects in a 3-D IC
RW, December, 2008 13
Nature of Coupling in a TSV Bundle
The capacitive coupling terms to
nearest neighbors dominate
Inductive coupling is significant within
Coupling terms to nonadjacent lines the entire bundle
are mostly insignificant
Within nearest neighbors the lateral
terms are more significant than the
diagonal terms.
RW, December, 2008 14
Electrical Modelling of TSVs
Model TSV electrical parameters in terms of Physical Dimensions
physical dimensions and material constants & material properties
− Various TSV structures have been
simulated in a field solver and their
Field solver
electrical parameters extracted R,L,C
− Using curve fitting techniques and
analytical insight, semi empirical formulae
for capacitance and inductance with Database No
varying geometrical and physical Enough ?
parameters are being finalised
Yes
Curve Fitting
Empirical formula:
R,Cs,Cc, Ls,Lm ~f(w,d,h,t)
RW, December, 2008 Representative Unit of a TSV bundle 15
TSV Parasitic Models
Capacitance Inductance
Self-Capacitance model is of the form: Self-Inductance model is of the form:
k 2 v k3 v
p p
l
k5
p
k7
lv
C s Ctsv 1 k1e rv
k 4 v
k6 v
r k8 l
rv Ls 0.16lv ln 1 0.9 v
v rv
where Ctsv is the capacitance of an isolated TSV
63.34lv Mutual-Inductance model is of the form:
Ctsv
l lv
log 1 5.26 v
Lm 0.199lv ln 1 0.438
rv dv
Coupling-Capacitance model is of the form:
k1 0 lv pv
k4
l
k6
pv
k8
Cc 1 k 3
r k5 v
r
l
k7
p v v v
ln k 2 v
rv
Max. % Averag
Error e %
Error
k1 k2 k3 k4 k5 k6 k7 k8
Cs _ M 0.1505 -0.0071 -0.091 0.1849 -1.9371 6.9577 -0.0131 -0.0354 48.0 7.8
0.6876 -0.0390 -0.0583 1.8076 -0.2229 11.3537 0.0402 -13.1813 10.2 1.9
Cs _ N
0.3406 -0.0345 -0.0686 5.0708 -0.1530 -5.6346 -0.3859 -0.7643 13.3 2.0
C s _ NE
10.191 0.5490 -0.014 0.796 0.054 -1.157 -0.018 -0.600 8.7 1.9
Cc _ l
Cc _ p 3.180 0.5440 -0.199 0.586 0.122 0.540 2.176 0.110 10.9 1.8
18.117 28.457 -1.734 -2.178 0.600 -0.518 -0.470 0.188 8.0 1.4
Cc _ d
RW, December, 2008 16
Global Interconnect in a 3-D IC
RLC or LC or RC or C ?
Inductive coupling is
vanishingly small. t d _ tsv 0.69 Rdrv (Cs Clat Cdiag )
Capacitive coupling when 8 Switching Pattern
aggressors switch Victim Lateral Diagonal
simultaneously on a silent UP UP UP 0 0
victim net about 15% of UP - - 3.4 5.2
Vdd.
DOWN DOWN DOWN 9.0 10.6
RW, December, 2008 17
Capacitive Crosstalk in TSV Bundle…
S G S
High
Capacitive
coupling G
(Clat)
G S
Low
Capacitive
S G S coupling Victim Eye 10 GBPS
(Cdiag)
counteract capacitive crosstalk at high
signalling speeds with shielding
Shield N, E, W, S TSVs (Marked as G)
Victim Eye 10 GBPS with Lateral TSVs Shielded
RW, December, 2008 18
Results Summary - Key Publications
Roshan Weerasekera, Dinesh Pamunuwa, Matt Grange, Hannu Tenhunen, and Li-Rong
Zheng, ” Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated
Circuits (ICs)” , 3D Integration Workshop, The Design, Automation, and Test in Europe
(DATE) conference, 2009. Accepted
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, and Hannu Tenhunen “Examination
of Delay and Signal Integrity Metrics in Through Silicon Vias”, 3D Integration Workshop, The
Design, Automation, and Test in Europe (DATE) conference, 2009. Accepted
Roshan Weerasekera, Dinesh Pamunuwa, Hannu Tenhunen, and Li-Rong Zheng, ”Modelling
Through-Silicon-Vias in 3D-ICs,” IET Electronic Letters, September, 2008, Under Review.
Roshan Weerasekera, Dinesh Pamunuwa, Matt Grange, Hannu Tenhunen, and Li-Rong
Zheng, ”Parasitic Parameter Estimation and Electrical Modelling of Through-Silicon Vias in 3-D
ICs,” IEEE International Symposium on Circuits and Systems 2009, Under Review.
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa and Hannu Tenhunen, ”Exploration of
Through Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits” IEEE
International Symposium on Circuits and Systems 2009, Under Review.
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, and Li-Rong Zheng
”Modelling and Analysis of Through Silicon Via Interconnects in 3-Dimensional Integrated
Circuits” In submission to IEEE Transactions on Very Large Scale Integration, to be
submitted
2. Signalling techniques for global on-chip
interconnects
RW, December, 2008 20
Design Methodologies for on-chip Interconnects
Already proposed methods can be discussed under several hierarchy
levels:
Layout and Architectural
Technological Circuit
Routing & System
Repeater Insertion, the widely used method for delay reduction …
l
Repeaters increase the total
capacitance by 0.73Cwire,
td = (tdrv+ 0.4rcl2) which Increases power
consumption
repeaters
50% of dynamic power
ls ls consumption in a
microprocessor is due to
interconnects
td = (l/ls)(tb+ 0.4rcls2)
RW, December, 2008 21
Adaptive Smart Repeater Concept
With switching pattern effective
Static load capacitance is varying…
driver With a traditional repeater, the
Ceff C s drive strength is static and hence
there is a variation of delay
With adaptive driver
• For worst-case switching
pattern drive strength is high,
• For best-case switching
Ceff Cs 2Cc pattern drive strength is low.
driver is slower for the switching
Assistant Driver (Ha) combinations that give rise to a
lower capacitive load, and hence
reduces Jitter.
Advantage of the repeater circuit
proposed in this work:
− Energy Saving
− Delay Equalization
Main Driver (Hm)
RW, December, 2008 22
Design Methodology
Delay expression when
Assistant Driver (Ha)
both drivers Switching
(TMA)
Estimate optimum Ht
(=Hm+Ha)
and number of sections
Main Driver (Hm)
Delay expression when
Main Driver (Hm)
Assistant is Quiet
(TM)
Evaluate Ha such
Ht is a function of wire length that TMA-TM=0
Ha depends on coupling capacitance
RW, December, 2008 23
Circuit Realization of Smart Driver
RW, December, 2008 24
Simulation Results
Higher the Ha, the higher the Energy saving, with a higher delay variation.
With a higher Ha, delay is increased due to lack of drive strength for some switching
patterns.
RW, December, 2008 25
Energy Saving for Each Pattern
Group 1 : Both wires switch in the same direction
Group 3/4: One wire switches, other one is quiet
Group 5 : Both switches in opposite direction
Energy Dissipation (fJ)
Eavg
Driver
Group 1 Group 3/4 Group 5 (fF)
Trad. 1530 1735 1997 893
Smart 994 1248 2065 753
Simulation
Selector 57 102 215 71
E 31% 22% -14% 8%
Trad. 1507 1888 2195 939
Smart 934 1274 2195 789
Model
Selector 77 77 77 77
E 33% 28% -4% 7.8%
Energy Dissipation for each switching group (Ha=104)
RW, December, 2008 26
Smart Repeater...
A clear design methodology – as simple as that of repeater insertion
− The abstract delay model allows the repeater to be easily modeled in a CAD
interconnect planning tool.
Low complex driver circuit
A comprehensive delay and energy analysis.
12% reduction of Dynamic Delay
Energy saving that can be achieved by the SMART driver in future nanometer
technologies is found to be in the range of 20% - 25%.
Tech. Node
130 90 65 45 32
(nm)
K 14 24 36 54 84
Ht 325 268 277 278 282
Ha 202 162 163 158 154
Esmrt/Etrad 0.74 0.75 0.77 0.80 0.83
RW, December, 2008 27
Results Summary – Key Publications
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa and Hannu Tenhunen,
”Switching Sensitive Interconnect Driver to Combat Dynamic Delay in on-Chip
Buses,” in Lecture Notes in Computer Science (Proceedings of PATMOS), vol. 3728,
pp. 277-285, 2005.
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng and Hannu Tenhunen,
”Minimum-Power, Delay-Balanced Drivers for interconnects in the Nanometer
Regime,” in Proceedings of the international workshop on system-level interconnect
prediction, Germany, March, 2006, pp. 113-120.
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng and Hannu Tenhunen,
”Delay-Balanced Smart-Repeaters for on-chip Global Signaling”, in Proceedings of
the 20th International Conference on VLSI Design held jointly with 6th
International Conference on Embedded Systems, 2007, pp. 308-313.
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng and Hannu Tenhunen,
”Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the
Nanometer Regime”, IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 16, no. 5, pp. 589-593, May, 2008.
3. Cost, Performance and Technological trade-offs
for 2-D and 3-D ICs
RW, December, 2008 29
SoC vs SoP vs SiP vs 3-D ?
SoC SoP
SiP 3D
RW, December, 2008 30
Trade-off Parameters
Chip Area, Area
Technology Fusion, Temperature
Mixed-Signal Integration (Footprint)
Worst-Case
Source: http://www.ziptronix.com
Delay
Yield
Wafer, Packaging,
Testing, Rework and Repair Cost
RW, December, 2008 31
Chip/Module Cost Model Flow
Substrate Cost
Gate Count
Technology Die Area
Parameters Assemble
(Cost, yield)
Test, Package
Bare Die Cost
Cost
Test
(Cost, Yield)
Chip Cost
Repair
Detailed models and flow is described in Chapter 5. (Cost, Yield)
RW, December, 2008 32
Performance – Latency ?
L=0.12µm
Wires in
• SoC: small and resistive
• SoP: fat and low resistive (LC transmission lines)
• 3D : shorter in length, direct vertical communication
Performance of SoC is not necessarily better ?
RW, December, 2008 33
Chip/Package Temperature Model
Thermal integrity is a critical issue for
even conventional chips because the
system reliability is strongly dependent
on the temperature.
Assuming the heat dissipates through
the Silicon substrate, the average die
temperature can be usually described Source: Mahajan et al. Cooling a Microprocessor Chip,
Proceedings of the IEEE
t
Tdie Tambient Pchip
kA
If the same assumption is made that yes
T3D>Tmax ? Insert T-vias
the die size is much larger than its
thickness, the maximum temperature in
no
a 3D-IC m m
T3 D Tambient R( i 1),i Pj Done!
i 1 j i
RW, December, 2008 34
Case Studies
Mobile Terminal
128Mb DRAM, 300K logic and 500K ASIC 2mm2 analog/RF, and
CMOS image sensor (8 Megapixel, and pixel size 1.75 m X 1.75 m)
Areas in mm2:
ASIC uP DRAM Image Analog/RF
Sensor
0.750 0.644 5.44 24.5 2
Wireless Sensor
2Mbit DRAM, 300K logic, and 500K ASIC, 2mm2 analog/RF, and
Sensor 1mm2
Areas in mm2:
ASIC uP DRAM Sensor Analog/RF
0.750 0.644 0.084 1 2
RW, December, 2008 35
Case Study 1: Mobile Terminal
Stacking Reduces footprint
3
Norm. Area
2 Chips
2
4 Chips
Single Chip 1
SoC yield is very low..
0
2D-SoP 3D-SiP 3D-W2W 3D-D2W
100
1
Norm. Cost
%Yield
50 0.5
SoC is
0
2D-SoP 3D-SiP 3D-W2W 3D-D2W
0
2D-SoP 3D-SiP 3D-W2W 3D-D2W Expensive!
400
120
Temperature/oC
Delay/ps
100
200 80
60
0 40
2D-SoP 3D-SiP 3D-W2W 3D-D2W 2D-SoP 3D-SiP 3D-W2W 3D-D2W
Lower operating Stacking increases
SoC performance is low temperature operating Temperature
RW, December, 2008 36
Case Study 2: Wireless Sensor
Footprint of SoC is
SoP has a larger area… Much closer to that of 3-D
6
Norm. Area
2 Chips
Yield doesn’t improve 4 Chips
4
as much Single Chip 2
0
2D-SoP 3D-SiP 3D-W2W 3D-D2W
100 SoC is
4 cheaper….!
Norm. Cost
So as 3D W2W
%Yield
50
2
0 0
2D-SoP 3D-SiP 3D-W2W 3D-D2W 2D-SoP 3D-SiP 3D-W2W 3D-D2W
200
120
Temperature/oC
Delay/ps
100
100 80
60
0 40
2D-SoP 3D-SiP 3D-W2W 3D-D2W 2D-SoP 3D-SiP 3D-W2W 3D-D2W
Stacking doesn’t improve Stacking increases
Lower operating
performance… operating Temperature
temperature 37
RW, December, 2008
2D vs. 3D Integration
3-D Integration is cost effective for large designs, but not for smaller
designs.
RW, December, 2008 38
Results Summary – Key Publications
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa and Hannu Tenhunen,
”Early selection of system implementation choice among SoC, SoP and 3-D
Integration,” in IEEE International System-on-Chip Conference, September, 2007,
pp.187-190.
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa and Hannu Tenhunen, ”
Extending Systems-on-Chip to the Third Dimension: Performance, Cost and
Technological Tradeoffs,” in Proceedings of the IEEE/ACM international conference
on Computer-aided design, IEEE Press, November, 2007, pp. 212-219.
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng and Hannu Tenhunen, ”2-
D and 3-D Integration of Heterogeneous Electronic Systems under Cost,
Performance and Technological Constraints,” in IEEE Transactions on Computer
Aided Design of Integrated Circuits and Systems, September, 2008, Under Review
(Third Round Revision)
Conclusions
Continuous scaling of feature size has been challenging 2-D planar IC design
− Power consumption and heat removal
− Interconnect woes
− Disparate technologies
Three-dimensional integration is a promising solution to expected limits of scaling
Discussed major three aspects of 3-D integration:
− Through Silicon Via modelling and subsequent analysis of Signal Integrity
Provide close form models for TSV parasitics
Given guidelines for SI issued in a TSV bundle
− Low power signalling techniques for global on-chip interconnects
Smart repeater circuit is proposed which can save 10% energy and 12%
delay variation
− 3-D IC design in cost and performance of perspectives
A methodology to analysis cost and performance a-priori.
RW, December, 2008 40
Thank you !
RW, December, 2008 41
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