PROCEEDINGS OF THEIEEE, VOL. 70, NO. 1 , JANUARY 1982 35
High Speed GaAs Integrated Circuits
A6muct-Much interest n
has been expressed i the use of GaAs While density was not of importanceforthe discreteFET,
MESFET’s for high speed digital integrated CiTCuits (IC‘s). Ropagdtion which generally was rather large inareaand used relatively
delays i the 6@ to 9O-ps/gate range have been demonstrated by several
n high pinchoff voltage active channel layers, it is of importance
laboratories on SSI and MSI logic circuita Recently, large scale digital
IC’s with over lo00 gates have been demonstrated in GpAg In this re- in an IC because of the desire to maximize yield of functional
view paper, thedevice, cc i and processingapproachespresently circuitsand to press circuit complexity beyond the small
being explored for high speed GPAS digital circuits are presented. The scale region (20 gates). Therefore, planar fabrication methods,
present performance status of high speed circuits and L S I circuits is similar in concept and apperance to well-established silicon IC
approaches, have been developed. The planar approach employs
selective ion implantation to localize active devices in the semi-
insulating GaAs substrate, and gate densities over 100 000/cm2
I. INTRODUCTION have been reported on very dense circuit structures [ 5 I .
VER THE PAST DECADE, GaAs Metal-Semiconductor The development of planar fabricationmethods and high
FET’s (MESFET’s) have been developed and extensively speed logic gate structures with modest power dissipation (<1
utilized for high-frequency low-noise amplification. The mW/gate) and h g h density has created interest in the extension
maximum available gain, noise figure, and bandwidth capabil- of GaAs digital IC’s into the large or very large scale of integra-
ities of analog microwave FET amplifiers have been unequaled tion range. The achievement of LSI or VLSI is important if
by any other semiconductor device in the 2- to 18GHz range. very high speed components for signal processors, computers,
These amplifiers have been widely utilized in commercial and and memory are to be feasible in GaAs IC’s. The high com-
governmentsystems.Reliability studieson low-noise FET’s plexity of such systems makes it very desirable t o include large
have proven that these devices aresutiable for mostsystem numbers of components on a single chip to reduce the large
applications. These discrete GaAs devices have also been shown quantity of high speed interconnections. Trends in this direc-
to be readily manufacturable in large quantities despite their tion are also quite evident in silicon IC implemented signal
0.5- and 1.0-pm gate lengths. processing and computational hardware 61, [ 71.
More recently, application of GaAs MESFET’s for high speed Very recent demonstration of high speed LSI parallel multi-
digital circuits has also been emphasized in several laboratories plier chipsin GaAs MESFET logic [81 has proven that such
because of the high switching speed and transconductance of chip complexities (over 1000 gates) are feasible in a well-con-
these devices. Propagation delays as low as 30 ps/gate at room trolled IC process. While further development and optimization
temperature and 17.5 ps/gate at 77 K have been reported on will certainly provide improved results, the initial observation
minimum-area lightly loaded GaAs ring oscillator circuits [ 11. of 1SO-ps/gate propagation delays in the 1000 gate 8 bit multi-
Even on morecomplexcircuits,such as MSI binary divider plier structure is quite encouraging. Also, even thoughthe
circuits,delays in the 60- to 90-ps/gate range have beenob- 1000 gate complexity level (about 3000 transistors and 3000
tained in several laboratories using various circuit implementa- diodes) permits a wide variety of “random” logic circuits or
tions and processing approaches. As a consequence, frequency sequential circuits t o be developed, memory requirements
dividers have been built in GaAs MESFET logic which function (fast access RAM) will mandate even greater complexity if
at input frequencies of 5.5 GHz . memory chips are to be large enough to permit fast processor
These promising high speed results have placed emphasis on integration in small volumes (needed to minimize the effect of
achieving fabrication methodswhich result in high density FET interconnect delay on system clock speeds).
logic gate structures with highly uniform device characteristics. Inthis paper,avariety of device, circuit,andfabrication
approaches currently being employedfor high speed GaAs
digital IC’s arepresentedand discussed. The performance of
Manuscript received July 8, 1981;revised October 1, 1981.
B. M. Welch, R. Zucca, P. M. Asbeck, C. P. Lee, C. Kirkpatrick, F. S. both ring oscillation and frequency divider “benchmark”-type
Lee, and G . R. Kaelin are with Rockwell International Microelectronic IC’s is compared followed by a brief summary of the LSI status
Research and Development Center, Thousand Oaks, CA 91360. of GaAs IC’s.
S. I. Long was with Rockwell International Microelectronics Research
and Development Center, Thousand Oaks, CA 91360. He is now with
the University of California, Santa Barbara, CA. 11. GAAS DIGITAL DEVICE
IC AND CIRCUIT APPROACHES
R. C. Eden waswith RockwellInternational Microelectronics Research
and Development Center, Thousand Oaks, CA. He is now with Gigabit The Schottky barrier gate field effect transistor (MESFET)
Logic, Culver City, CA. is the main active device used in GaAs IC’s. Fig. l ( a ) shows a
0018-9219/82/0100-0035$00.75 O 1982 IEEE
36 PROCEEDINGS OF THEIEEE, VOL. 7 0 , NO. 1, JANUARY 1982
lwn 3 x 1017
IMPLANTATION ~ H R O U G H Z S A
400 KcV. 2.2 x 10l2 an-2
IMPLANT SOFL IC DEVICE
- 1 x 1018
- 1 x10l6 n-GA 4mA
- 6 ~ 1 0 n-Aln&+-rA.
~ ~ 260A
1015 I0.02 I I I , , , ,
I I 1 I , , ,
S.I. GaAs SUBSTRATE
Fig. 2. Activelayerdopantprofdes for the n-FET channelSelenium
Fig. 1. Device cross-sectional view of (a) MESFET, (b) JFET [ 11 1, and implant and then+ high-speed switchingdiode sulfur implant.
(c) rnodulation-doped [ 161 device structures. silicon implant can also be used for both the n-and n+ regions.
cross-sectional diagram of a typical planar ion-implanted stricted to a narrower range (generally 0 V to 0.7 V, the for-
MESFET fabricated by localized implantationinto a semi- ward gate conduction voltage for a MESFET) than was the
insulating GaAs substrate. The channel implant species, energy, depletion-mode FET device. This restriction results in smaller
and dose are chosen so that the peak position and depth of the I& for a given device area of an enhancement-mode FET than
doping profile (as shown in Fig. 2) result in a device with the a depletion-mode FET, and therefore, the propagation delay is
desired pinchoff ( 5 ) voltage. If the device channel is conduc- generally higher and powerdissipationlower for GaAs IC’s
tive at Vgs= 0, the pinchoff voltage is negative and a depletion- implemented with normally OFF transistors.
mode (normally ON) device is obtained.The logic voltage JFET devices, using a p+ gate stripe formed by selective ion
swing can extend from below - Vp to the onset of gate conduc- implantation, have also been successfully employed in GaAs
tionduetothe forward-biasedgate-source junction. Larger digital IC’s [ 111. A diagram of a GaAs JFET is illustrated in
logic swings will produce higher speed circuitsfor agiven device Fig. l(b). The JFET is somewhat more difficult to fabricate
type since Ids (Y ( vgs V p ) 2 when vgs vp< 1.2 V for GaAs
- - than a MESFET because of the additional p+ implant process
FET’s. Therefore, higher Ids per device area will be available steps and the precise control of the p+ junction depth neces-
with increasing gate bias for charging load capacitances. Fur- sary to control the pinchoff voltage of the device. However,
ther increase of logic voltage will result in velocity saturation sufficient control has been obtained, at least for SSI circuits.
limited currents (Ids (Y (vgs V,)) and no further improvement
- Gate lengths in the 1- to 2-pm range are readily achievable with
in speed shouldbeobserved. The speed-power product will, optical lithography. The greater built-in potential of the p+-n
however, be greatly increased by the higher logic voltage swing junction provides a higher forward-bias gate conduction limit
[ 91. Thus a superior approach for higher speed circuit perfor- (approximately 1.1 V) which should provide a significant speed
mance would be to increase gm/Cin (or the currentgain-band- advantage for enhancement-mode JFET’s over MESFET’s,
width product) of the switching transistor. This can be done assuming that source and gate resistances are minimized on
by reducing source resistance and gate length through process this structure [ 121. However, the speed performance reported
improvements(or by substitution of a higher performance t o date on thesedevices has not yet equaled the MESFET. The
device type as discussed in [ l o ] ). larger available logic voltage swing will also be beneficial in
If the built-in potential of the Schottky gate metal capable
is increasing noise margins for normally OFF JFET logic over
of preventing current flow in the channel & = 0, an enhance-
at normally OFF MESFET logic.
ment-mode (normally OFF) device results. This device requires The choice of a particular type of FET device is associated
forward gate bias (v,, > 0) to enable flow of I d s . Therefore, a
with choice fabrication
of circuit and The
the logic voltage swing of an enhancement-mode FET is r e depletion-modemetal-semiconductor (Schottky barrier) FET
LONG et al.: HIGH SPEED GaAs IC’s 31
(D-MESFET) is the most widely used device, and also is the
one that has given the highest performance to date. Circuits
employing depletion-mode MESFET’s pose the least fabrication
problems (see Section 111) because Schottky barriers on GaAs
are easier to fabricate than p-n junctions, and the larger (typ-
ically 1-V) logic swings associated with D-MESFET circuits
avoid excessively stringent requirements for FET pinchoff volt-
age uniformity. Because any regions of the source-drain chan-
nel not under the gate are conductive in D-MESFET’s, precise
gatealignments are notrequired,nor are special gate recess
etch processes or other means to avoid parasitic source and
drain resistances necessary. The MESFET fabrication simplicity
makes it considerably easier to achieve high yields than with
more complex device structures. On the other hand, however,
logic gates employing depletion-mode active devices necessarily F=X
require some form of voltage level shifting between FET drains
and gates to meet turnoff requirements, and usually require
two power supplies, imposing some penalty in terms of wafer
area utilization. An exception to the two power supply require-
mentsfor D-MESFET circuits is the enhancement-depletion
logic approach [ 131 which uses 0.4-V < Vp < 0.1-V MES-
FET’s with diode level shiftingin single power supply logic
Enhancement-mode MESFET’s (E-MESFET’s) offer circuit
simplicity because the logic gates :require only one power
supply, but the permissible voltage swing is rather low because
Schottky barrier gates on GaAs cannot be forward biased above
0.6 t o 0.8 V without drawing excessive currents. A 0.5-V swing
is a desirable goal for the operating range of ultra low power
circuits, but very tight control is required in order to fabricate
Fig. 3. Enhancement-mode JFET or MESFET circuits [ 111, [ 121,
uniform, very thin active layers, so that they are totally de- Simpledirect-coupled
[ 1 8 ] . (a) FET logic (DCFL) NOR gatewith
pleted at zero gate bias voltage and yet give good device trans- resrstor load.(b)Pseudocomplementarybuffered inverter gate.(c)
conductance when the device is turnedon.For reasonable combination of source-follower logic with the circuit of (b) to give a
buffered NOR gate. This type of approach has been extended to two-
noise margins and good dynamic performance, standard devia- level gates as well.
tions of FET pinchoff voltage of the order of 25 mV could be
required-a very difficult goal for GaAs FET’s.
Implementation of a MOSFET or MISFET (Metal Insulating swings of only 100 mV or so. This would result in extremely
Semiconductor FET) technology in GaAs would eliminate the low speed-power products. To utilizethese devices for LSI
logic swing limitation completely, but attaining such devices GaAs circuits,however, an effective means of fabrication of
has provendifficult. Some simple ring oscillators have been large numbers of these transistors with nearly identical device
fabricated using directly coupled FET logic implemented with characteristicsmust be developed. At the presenttime, only
buried channel GaAs MOSFET’s and resistor loads [ 141. How- discrete transistors have been demonstrated.
ever, at this point, stable oxides have not been‘achieved insuch
circuits, so that gate threshold voltages shiftwithrespect to Enhancement-Mode Circuit Designs
the prior input signal history. This limitation has constrained A number of circuit designs for basic logic gate structures
the demonstration of GaAs MOSFET’s to ring oscillators and have been proposed or demonstrated utilizing normally OFF
other simple circuits in which the input waveform has a sym- FET’s in conjunctionwith resistor ordepletion loads and
metric(50-percentduty cycle) nature,buttheperformance Schottky-barrier level shifting diodes. These have mainly been
observed to date does not supportMOSFET’s in general digital orientedtoward use of the MESFET or JFET as the active
circuit applications. Efforts to improve the stateof GaAs oxide switching devices. The following subsection will summarize
technology are continuing, however. The use of InP for and review several of these circuit approaches.
MISFET devices may be more promising than GaAs [ 151. The simplest circuit approach, direct-coupled FET logic
High mobility FET devices are also being developed for use (DCFL), is illustrated for a 3-input (positive) NOR gate in Fig.
in GaAs IC’s. These devices take advantage of the greatly re- 3(a). Inthisapproach, a logic “0” corresponds to a voltage
duced ionized impurity scattering possible at 77 K in a lightly near zero. A logic “1” correspondsto a positivevoltage capable
doped n-GaAs channel when free carriers are introduced through of fully turning on the normally OFF FET’s, a value usually
a wide-gap n+-A1,Gal -,As heterojunction as shownin Fig. limited by the onset of gate conduction in the FET; typically
l(c). These structures have beenreferred t o as modulation- on the order of 0.6 V to 1.4 V depending on what technology
doped FET’s [ 16 ]or high electron mobilitytransistors (HEMT) is used (MESFET, JFET, or HJFET). It has been proposed to
[ 171, and electronmobilities of 80 000 cm*/V * s at 77 K have place input FET’s in series, generating the NAND function [ 181.
been reported [ 161. Such FET’s, fabricated with short gate However, theimplementation of such design wouldappear
lengths, should achieve high g, and fr with very small logic impractical because the on resistance of the conducting FET’s
38 PROCEEDINGS OF THE IEEE, VOL. 7 0 , NO. 1, JANUARY 1982
would cause larger threshold shiftsthan couldbe tolerated
with the very low logic swings of E-MESFET logic. (It would
probablywork with E-JFET’s or H-JFET’s, however, and
should represent no problem with MOSFET’s.)
A significant improvement to the DCFL gate shown in Fig.
3(a) would be to substitute forload resistor RL,an active load
current source made withanormally ON (depletion-mode)
FET, with its gate tied to the source. Such a nonlinear load
would sharpen the and
transfer characteristic significantly
improve the speed and speed-power products of the circuits
(by perhaps a factor of 2). The fabrication of the depletion-
mode active load requires a dopant concentrationprofiie differ-
entfromthat of theenhancement-mode devices. Although
enhancement-mode demonstration circuits have been fabricated
using a single active layer, the multiple localized implantation
fabrication technique used for the Schottky-diode FET logic
(SDFL)approach (discussed later in this section)could be
applied to such enhancement-mode circuits so that depletion-
mode active loads could be used. An additional nonlinear load
component which shows great promise for enhancement-mode
logic circuit is the saturated drift velocity resistor [ 121, [ 191 i.
F g 4. Single-supplyenhancement-mode MESFET NOR gate circuits
in which the current limiting action is enhanced by the use of [ 13 1. (a) Quasi-normally off >input NOR gate. (b) 3-input NOR gate
with pseudocomplementary buffer; note similarity to Fig. 3(c).
a shortchannel gateless FETstructure. Here, thecurrent is
limitedbyvelocity saturation of the channel electrons, and
very low saturation voltages should be possible withshort smaller than IL,while its “ON” current is well above ZL , This
sourcedrain gaps, thus reducing power dissipation. can be achieved in depletion-mode MESFET’s with reasonably
From a static point of view, the fanout capability of DCFL small pinchoff voltages (5w - 0.4 V) with zero or slightly
is excellent since it is determined by the very low gate leakage positive gate voltages, so that only a single power supply is
currents. However, from a dynamic point of view, the switch- required. For example, with Vp = - 0.4 V and %,(ON) = +0.7
ing speeds are reduced by the gate capacitance loadings by a v, Gs(OFF) = +0.1 v, We have &(ON) = 4.84 x &(OFF), an
ample margin for switching.
factor of approximately 1/N where N is the number of loading
gates, as in silicon MOS. In general, the current through the A number of circuit approaches for single supply E-D
MESFET logic have been proposedandanalyzed [ 131. Fig.
resistor RL, saturated resistor, or active load is kept fairly low
in DCFL in order to reduce static power and improve noise 4(a) shows the circuit diagram for an elemental 3-input NOR
margin byreducing theoutput “low” voltage of the FET. gate inthe most promising of these publishedapproaches.
Consequently, the output risetime under heavy fanout loading This uses source follower logic to obtain the positive OR func-
conditions is very poor. This canbegreatlyimproved with tion, with single diode level shifting and a resistor pulldown Rs
thepseudocomplementary outputbuffer configuration of to drive the output inverter FET. The analysis in [ 131 indicates
Fig. 3(b), at very little increase in static power dissipation, but proper gate operation for MESFET pinchoff voltages in the
this circuit performs only logic inversion [ 121. By combining - 0.4 < Vp < +O. 1-Vrange, which is several times the allowable
the inverting buffer with a source-follower positivwa input range width for E-MESFET logic and much more reasonable
structure as shown in Fig. 3(c), a general multiple-input NOR
gate can be achieved whichhasexcellent fan-in and fan-out - -
in terms of practical fabrication control. The supply voltage
(&a 3 v) and logic Voltage Swing ( Vout 0.2 v t o 2.4 v)
values used are even larger than those used in the SDFL D -
drive capabilities at very modest static power levels [ 181. Un-
this source-oR/pseudocomplementary inverter MESFET approach, so that very low PD7d products would not
gateconfiguration is also quite complex,requiring 7 FET’s be expected. The gate output of Fig. 4(a) has the same drive
and 2 resistors for a 4-input NOR gate, which can be expected problems as that of Fig. 3(a), but this should be improved for
to consumeconsiderablechiparea and have significant self- of
heavily loaded gates with the buffer structure Fig. 4(b). This
capacitance. is, of course, very similar (except for the two voltages shifting
diodes) to the enhancement circuit of Fig. 3(c).
At the present time, demonstration circuits containing up to
Enhancement-Depletion-Mode MESFET Logic 15 gates have been fabricated using enhancement-mode FET’s.
Because of the nonlinear, approximately square-law nature MESFET-implemented circuits have exceeded the performance
of the FET Ids versus V, relationship, it is not always neces- of JFET circuits in both speed and power even through the
sary to completely turn off theFET (i.e., make V, more higher JFET logic swing should provide greater speed as dis-
negative than Vp)in orderto obtain switching behavior. cussed above. Complexity of enhancement-mode circuits has
Drain dotting of many FET’s, as in Fig. 3(a), necessitates probably been limited by fabrication technology and threshold
turning all of the FET’s nearly off so that the s u m of all of uniformity. Comparisons of ring oscillators and frequency
their drain currents is substantially less than the load current divider demonstration circuits are made in SectionIV.
ZL through RL require to produce an output voltage near the
switching threshold of the next driven gate. However, if only Depletion-Mode Logic Approaches
a single FET switches the load, it is only necessary to reduce BufferedFET logic (BFL)  and Schottky Diode FET
its drain currentinthe OFF stateto a value significantly Logic (SDFL) [ 2 11 gate circuit approaches have been exten-
LONG et al.: HIGH SPEED GaAs IC’s 39
BASIC INVERTER +45V
INPUT PULSE OUTPUT PULSE
a1 SDFL NOR GATE
LOGIC SECTION OPTIONS
60 2-A.B z- A.B
bl SDFL OWNAND GATE
COMBINED N A N 0 + NOR
c i SDFL ORINANDNIIRED-AND GATE
Fig. 6. Comparison o f 1- , 2- , and 3-level SDFL gate configurations
[ 2 2 ] . All FET’s are depletion-mode, typically -1.5 ’
V < <
-0.5 V ;
Fig. 5. Basic circuit confiiurations for buffered FET logic [ 2 0 ] . (a) unshaded diodes are very small high speed switching Schottky diodes
Basic inverter circuit. (b)-(e) Options for the input section for NOR while shaded diodes are larger area, higher capacitance voltage shift-
SASD and combined NANDNOR functions. ing diodes.
sively employedfordepletion-mode GaAs IC’s. Circuit dia- applications requiring lower LSI complexity (200-500 gates).
grams for NOR gates formed by these two approaches are Demonstration circuits with about 20 gates complexity have
presentedin Figs. 5 and 6 . The BFL circuitemploys FET’s been reported in the literature using high pinchoff BFL gates
to perform a NOR (or 2-input NAND for a dual-gate FET) func-  ; however, larger BFL circuits ( a 2 0 0 gates) using low
tion at the input. The output is driven by a source follower, pinchoff FET’s are currently in development.
with level shifting diodes to restore the required logic levels to The SDFL circuit approach, shown in Fig. 6, permits high
the +0.7-V (high) to - Vp (low) voltages required by the input speed operation comparable to the BFL approach, but results
FET’s. The source-follower output driver yields a gate struc- in considerable savings in area/gate (600 to 2000 pm’) and in
ture which has relatively low sensitivity to fanout loading and lowerpowerdissipation (0.2to 2 mW/gate). SDFL utilizes
loadcapacitance. Also nodcoutputcurrent is required to clusters of small high-performance Schottky diodes to perform
drive subsequent BFL gate inputs. Fan-in is limited for practi- the logical positive-OR function on groups inputs which may
cal purposes to 3 for a NOR gate by the drain capacitances of then be further processed with the normal FET logic functions
the input transistors and thearea required by these devices and (series-NAND,wired-AND , etc.). Fig. 6 shows SDFL gate cir-
2 for the NAND gate because of voltage drop in the series FET’s circuits diagrams for single- , two- , and three-level logic gate
which results in threshold shift. configurations [ 221. Note that the SDFL gate structure allows
Nearly all BFL circuits reported to date utilized relatively
have virtually unlimited fan-in at the first (positive-OR) logic level
high pinchoff voltages (- 2.5 V) and three level-shift diodes for (SDFL circuits with up to 8-input NOR gates have been
convenience in fabrication (since epi/implant-mesa approaches described in publications) 1231, but it has the same practical
provide suitable threshold control for large logic voltage swings) restrictions to a fan-in of 2 at the second (series FET NAND)
and, therefore, have exhibited high power dissipation per gate and third (wired-AND) levels if dynamic performance is to be
(40 mW typical). However, since fabrication methods and maintained.
pinchoff voltage control have been improvedwith ion-implanted The SDFL circuit approach offers large savings, not only in
planar approaches, there is no reason why low pinchoff (- 1-V) power, but also in circuit area, over previous D-MESFET
MESFET’s and two level-shift diodes should not be employed approaches. The circuit area savings comes about because of
for advanced BFLgates designs. These modifications should the simplicity of the gate design and replacement of (large)
reduce power dissipation to -5 mW/gate by allowing operation FET’s with very small (typically 1 pm X 2 pm) Schottkydiodes
at lower voltage and current levels with relatively little sacrifice for most logic functions. The fact that thediodes are 2-terminal
in speed and could make BFL circuits a possible candidate for devices also significantly reduces the number of vias and over-
40 PROCEEDINGS OF THE IEEE, VOL. 70, NO. 1, JANUARY 1982
crossings required in most circuits as compared to the vias and as shown in Fig. 7(b) [ 25 I , [ 26 1 . Other similar processes not
overcrossingsneededwhen3-terminal FET’s areused as the illustrated ,  have used both and
logic elements. implanted layers. Precisethicknesscontrol has provenvery
The input logic diodes require a lower carrier concentration, IC’s
difficult for GaAs E-MESFET utilizing vapor phase epitaxy.
lower sheet resistance implant than the FET channel to opti- This has necessitated controlled thinning of the epitaxial layer
mize their reverse-bias capacitance and series resistance. Thus using self-limiting anodization and stripping techniques which
SDFL circuits require two separate implant steps using local- donot appear for Workers
practical LSI. employing ion-
ized implantation into selected areas of the substrate. implanted layers  appear t o omit this step. However, all
Fanout of the basic SDFL gate is limited 3 without buffer- of these E-MESFET approaches requirethe use of recessed gate
ing or using wider channel widths in the driving gate. However, structures. Recessed gates circumvent some of the difficulties
the propagation delay is not as sensitive to fanout loading as associated withthe high series resistance surface depletion
the direct coupled FET logic (or NMOS) approach, since the layers often observed on very thin FET channel layers. A deep
gate-source capacitance of the switching FET is discharged by implant or thicker epitaxial layer is initially provided (lower
the pulldown active load instead of the preceding FET drain sheetresistance),and the Schottky gate is recessed into the
current. GaAs surface by using a chemical etchant or chemical anodiza-
tion method. This process approach providesimproved FET
111. GAAS DIGITALIC FABRICATION APPR0ACHF.S to
characteristics by lowering source/drain gate series resistance,
Inthe followingsection,a reviewof fabricationmethods but the uniformity, control, and yield of the resulting devices
currently in use on GaAs digital IC’s will be presented. These for LSI applications are in serious question. For example, the
methods areschematicallyrepresented in Fig. 7.While the difficulties encountered in obtaining adequate uniformity using
selection of processingtechniques to be discussed is by no implanted layers and recessed gate structures for E-MESFET
means exhaustive,it is representative section
a cross of devices has led workers to explore innovative, less demanding
approachessuitableforfabrication of FET-based GaAs IC’s (in terms of device uniformity) circuit concepts such as quasi-
with gate lengths as short as 1 pm for optical lithography or normally OFF MESFET logic [ 13I .
3 pm for electronbeam or certaintypes of self-aligned Bothcontactphotolithography [ 271 and EBL  have
beenemployed in thefabrication of L = 1-pm circuits of
this type. The fabrication of these E-MESFET circuits is quite
Mesa-Implanted D-MESFET similar to that of the mesa D-MESFET approach except for the
InitialGaAs IC efforts werebased on the well-developed variationshown in Fig. 7(b)whichuses the ohmiccontact
depletion-modeGaAsMESFETmesafabricationtechnology metallization for thefirst-level interconnects, with the Schottky
used in the production of low-noise microwave FET’s. Isola- gate metallization also sewing for thesecond-level interconnects
tion between active devices is accomplished in this approach 1271.
Basically, as shown in Fig. 7(a), a discrete MESFET fabrication Self-Aligned Epitaxial D-MESFET
process is used with the addition of a second layer of metal The development of a planar technology in Si IC’s marked
and a dielectric layer for interconnecting the various circuit theturningpointwhich led to rapidprogresstowardLSI,
elements. First layer to second layer metal overcrossings have suggesting that planar development in GaAs will also have a
also fabricated using plated &-bridges ratherthana similar impact. Recent work toward the development of strua
dielectric. Initial work employing epitaxial techniques for the tures hasled to thefabrication of D-MESFETGaAs IC’s shown
(-2000-& active layers encountered difficulties in achieving in Fig. 7(c) . In this fabrication process, the structure can
the uniformityandreproducibilityrequiredfor IC’s. Subse- be made planar by replacing the mesa isolation step withselec-
quently, an implanted layerwas substituted for epitaxiallayer, tive proton, oxygen, or boron bombardmentwhich renders the
withtheimplantationmadeintoa high resistivity epitaxial underlying epitaxial material semi-insulating. This fabrication
buffer layer or directlyinto the semi-insulating substrate. Both method may use epitaxial or implanted layers. However, it is
techniques are currently being used in the mesa-implanted D- still limited t o a single active layer. The qualityof the electrical
MESFET fabrication of buffered FET logic (BFL) circuits [ 201 and long-term
isolation the reliability in high temperature
shown in Fig. 7(a). operation of this high resistivity ion bombarded layerneeds t o
While this mesa fabrication approach has the important ad- be investigated in greater detail.
vantage of process simplicity, it has been, atleast in its present Unique t o this fabrication approachis the use of a self-aligned
form, restricted to applications in which only a single active not
FET gate scheme which does require a Schottky gate mask-
layer (implanted or epitaxial) is required, i.e., circuits in which ing step. This process requiresthe use of A1 gates since alloyed
only a single type of device needs t o be optimized. The density ohmic contacts are fabricated after the formation of the gates
and yield limitations associated with mesa structures may in- I
and A provides a suitable Schottky barrier material capable of
hibit the extension of this technology to LSI/VLSI. Mostof withstanding the subsequent 45OoC alloying cycle. Since the
the work using this approach has been directed toward high ohmic contacts are composed to AuGe and the gates are made
speed MSI logic, withexcellent results achievedusingl-pm o
of Al, a M barrier layer is required t o separate the A1 and Au
contact photolithography [ 241. based metallization systems, adding some complexity t o the
process and raising some concern regardingthe long-term relia-
Mesa Epitaxialllmplanted E-MESFET bility of mixing A1 and Au metallizations. Circuits of this type
Enhancement-mode GaAs MESFET devices have also been have been fabricated using contact photolithography and have
fabricated on epitaxiallayersandisolatedbymesaetching. yielded promising results in the lower MSI level of complexity,
This technique has provided Direct Coupled FET Logic circuits to
with reasonable promise of extension larger circuits [ 21.
LONG er ai.: HIGH SPEED GaAs IC’s 41
S R K OF I W L A T I N G
Planar Implanted E-JFET 7(d). Thisapproach uses a junction FET (JFET) to provide
A planar enhancement-mode E-JFET fabrication technology and
DCFL circuits with resistor loads. The FET channel heavily
[ 4 ] , [ 1 1 1 currentlyunderdevelopment is illustrated in Fig. doped regions under the ohmic contacts are produced by using
PROCEEDINGS OF THE VOL. 70,NO. 1 , JANUARY 1982
multiple selective n-type implantation stepsand the gate region ing interconnects) intest IC’s. MSI/LSI circuitswith up to
is fabricated using ap-type implant. Sinceisolation through 1000 gatecomplexities have been successfully demonstrated
mesa is no longer needed, a planar structure is obtained. with this fabrication technology with gate densities as high as
The principal interest in the E-JFET is in its larger allowable 350 gateslmm’. A complete description of this particular
voltage swing before the onset of gate conduction, although planar approach has been previously reported [ 51.
the structure also offers potentially lower parasitic source and
drain channelresistances than the E-MESFET. The E-JFET Electron-Beam Lithography
might also offer better control over gate threshold voltage than Direct writing electron-beam lithography(EBL) has been
the E-MESFET in that V, can be controlled both by the n- utilized as an alternative to projection optical lithography when
implant and by controlling the depth of the pyn junction (ina submicrometer gate lengths are required. The performance of
manner similar to controlling the emitter depth of a Si bipolar the GaAs MESFET (current gain-bandwidth product) increases
transistor). This fabrication technology has been used to pro- as linewidths below 1 /m are used, and very high speed GaAs
duce E-JFET devices withgatelengths of 1 pm, using a Mg IC’s, which employ gate lengths in the 0.5- to 0.7-pm range
implantforthep+ gate.Thiswork is at an earlier stage of have been demonstrated [ 21. Ring oscillators using 0.6 pm X
development than the D-MESFET or E-MESFET efforts, but 20 pm normally OFF GaAs MESFET’s were fabricated by EBL
some inverter ring oscillator results have been published with [ 291, and propagation delays as low as30 ps/gate were observed
gate densities of 200 gateslmm’ with projected [ 4 ] , [ 11 ] gate ata power dissipation/gate of 1.9 mW. These same devices
densities of 800 gateslmm’. In principle this appears to be an
also were used in a divide-by-8 circuit with 66-ps/gate equiva-
attractive fabricationandcircuit approachforenhancement
logic. The main drawback for practical LSI results from the Another advantage provided by direct-write EBL is the ability
yield limiting additional processing required for JFET’s in to rapidly modify circuit and device designs to optimize circuit
comparison to D-MESFET’s. In particular theadditional p+ performance. Delays associated with photomask procurement
implant and subsequent self-aligned gate electrode pose diffi- are thereby eliminated. The writing rate of all but the most
cult fabricationproblemsat the I-pm level and below. Also, exotic EBL systems is, however, much too slow to be considered
it would appear that a depletion-mode active load would be an for LSI or VLSI circuit fabrication on large substates. Writing
attractive alternative to the currently used resistor load con- rates are also limited by the sensitivity of electron-beam resists.
figuration, leading to additional processing in theform of Application of direct-write EBL for LSI circuits will, for the
implants and Schottky barriers. Optimized development of most part, be conditional on the development of higher sensi-
planar JFET logic will possibly require one (or more) additional tivity electron resists or EBL systems with fasterbeam scanning
mask levels than D-MESFET fabrication approaches. and higher beam intensities.
Planar Implanted D-MESFET IV. PERFORMANCE GAAS IC’s
The planarimplanted D-MESFET GaAs IC fabrication a p In the following section, the high speed performance of
proach is illustrated in Fig. 7(e). Planar circuits are fabricated various GaAs digital IC approaches will be presented and con-
as in the planar E-JFET approach by using multiple localized trasted. This comparison will be based on reported speed and
ion implants directly into semi-insulating GaAs substrates [ 51. power dissipation of GaAs IC ring oscillators and binary fre-
Hence, individual devices can be optimized by using different quency dividers, demonstration circuits which nearly all of the
implants, and theunimplanted GaAs substrate directlypro- approaches discussed in Sections I1 and 111 have successfully
vides isolation between devices. Very uniform MESFET device fabricated andevaluated. Inaddition, a brief description of
parameters have been obtained over 1-in GaAs IC wafers using the statusof Large Scale Integration in GaAs will be presented,
the direct implant approach. Standard deviations of pinchoff along with adescription of the performance of a 1000 gate
voltage as low as 34 mV have been observed, while 50 to 80 parallel multiplier circuit implemented in SDFL.
mV is routinely obtained [ 38 J . This fabrication method con- Ring oscillators (RO)are a widely used, simple circuits con-
veniently complements the Schottky diode-FET logic (SDFL) sisting of chains of an odd number (N) of inverters or logic
circuit approach [ 2 11, which requires the use of at least two gates. If the loop gain exceeds 1 then an oscillation is obtained
different implantationsfor optimizing both D-MESFET and with frequency f. The propagationdelay TD of the inverters or
high speed Schottky barrier switching diodes. Also, planar gates is related to f by TD = 1/(2fn3,and the dynamicswitching
devices can generally be located closer togetherthan mesa energy PDTD is also provided by this measurement. The param-
devices, because space need not be allocated for mesa side eters extracted by the ring oscillator techniques represent
walls. nearly intrinsic speed and power since capacitive loading due
Thefabrication process outlined in Fig. 7(e) is much less to parasitics are generally minimized by a compact layout and
prone to surface related problems than other approaches be- fanout of 1 is usually employed. Since the propagation delay
cause the GaAs substrate is totallyprotectedby dielectric of all logic families increases by varying degrees with fanout
layers throughout the fabrication process; windows are opened and capacitive loading,ring oscillator results are notnecessarily
in the dielectric only where ohmic contacts, Schottky barriers, representative of the performance to be expected in larger,
or interconnect metallizationsarerequired. One micron fea- more realistic logic circuits. In spite of the above limitations,
tures are resolved using reduction projection photolithography the R O is still a useful evaluator of the intrinsic speed of a
inconjunctionwithliftoff, plasma etching,and ion milling circuitdevice combination,and at least provides a lower bound
techniques. The metallizations used in these IC’s are AuGe for on propagation delay and dynamic switching energy.
alloyed ohmic contacts and TiPtAu for gates, first- and second- Table I presents a summary of published ring oscillator data
level interconnections. At the present level of development both
from enhancement- and depletion-modeapproaches
this fabrication technology has demonstrated gate areas as low employed in several laboratories. Propagation delays as low as
as 600 pm’lgate or circuit densitiesof -800 gateslmm’ (includ- 30 ps/gate are shown on a submicron gate length RO (1 7.5 ps/
LONG e t d.:HIGH SPEED GaAs IC's 43
TABLE I TABLE I1
RINGOSCILLATORS SPEEDPOWER PERFORMANCE FOR SEVERAL GaAs I FREQUENCY
GaAs IC TECHNOLOGIES ~
6ak IC H e a c ul e d
T h e oi rseut r itta l Equivalent P0-r
T e c h a p po g y c h
nol roa k x . T o g g l e F. Pax. Toggle F. Dlssipatlon Pn7*
Gate L e n g t h ~~~~
6 Gaze Y l dPh o p a g a t i o n Speed-Power 1 y m D/SOFL D.F.F. i 2 115 T~ 1.9 WZ 105 PS 2. 5 M I g a t e 0.26 pJ
Saurce (vm = F a n l n t r oadnuocut t e l a y
"3) P F D R o c k r e l l  (HOR U T E )
Hughes [ 2 8 3 MESFET/BFL 0.5 50 34 1.d It1
0.7 v m o m t n.F.F. + z it5 T~ 3.0 67 40 2. 68
)I TCSF 
F.P. [201 D I E S F E T t E F L NOR 1 x 20 86 3.9 2/2 1 urn O I B F L D.F.F. t 2 1/5 T~ 2. 2 91 78 7.1
Rockwe11 WIESFET.'SDFL NO09 1 x 10 120 0.040 211
52 0.063 211 1 urn D/EFL NAANDiNOR i 2 It2 T~ 4.5 111 40 4.4
CSF 0.75 x 20 68 2 1/1 H.P.  CM. CLKK
FUJlTSU Dl1 EMESFETID-LOAD 1.2 I 20 170 0.12 It1 0.6 v m D/BFL NANDINOR + 2 112 lo 5. 5 91 40 3.6
FUJITSU  SELF P L I G N E t O C F L 1.5 I( 30 50 0.287 LEP 123 C . CLOCK
N.T.T.C2gl EHESFETI3CFL 0.6 x 20 30 0.057 It1 0.6 y m E/DCFL O.F.F. t 8 1/4 T~ 3.8 0.079 66 1.2
17.5. 0.616 111 N.T.T. [291 (NU7)
1.2 urn EIOCFL CMP. CLOCK 1/4 T~ 2.4 100 3.9 0.39
nco 321 EJFETIPreudo 1.0 x 13 150 0.06 It1 HEC 1341 t 2 NOR
CSF[131 1.0 X 35 105 0.23 111
'Measured a t 77-K.
h 1 \ \ \
; 1" 10 x PD'\\ \ \
(b) fmax = 115 r D PDWER DISSIPATIONPER GATE
Fig. 9. Speed-power compahonof a
variety of frequency divider
approaches corresponding to Table 11. At the far left, for reference,
is a Josephson Junction divider. Its power dissipation has been scaled
byafactor or 10 to accountfortheinefficientheatdissipationin
(c) fmax 1/4 r D
capacitance also increases directly, the ratio of device capaci-
tance to parasitic capacitance increases and thus the propagation
delay asymptotically approaches the intrinsic device perfor-
C mance. Therefore, it is very important t o only compare data
c for circuits with the same gate length FET's (and to a lesser
extent gatewidths) to obtain ameaningfulcomparison of
The performance of logic circuits such as a binary ripple fre-
quency divider is a more meaningful indicator of the overall
F g 8. Four circuit implementations of binary ripple frequency dividers
(divide by 2 circuits) with different theoretical maximum toggle fre- performance of a particular circuit anddevice approach because
quencies. These frequencies are expressed as inverse multiplesof logic fan-in, fanout, and capacitance loading are greater in an actual
gatepropagationdelays.(a) 1/4 rd D-type single-clocked FF. (b)
1/5 7d D-typesingle-clocked FF. (c) 1/4 Td master-slave, compla
sequential or combinational circuit than in a ring oscillator.
mentary-clocked FF, (d) 1/2 rd master-slave complementary-clocked Fig. 8 depicts the circuit diagrams of four types of frequency
FF. dividers which have been implemented in GaAs. The theoret-
ical maximum toggle frequency of these dividers depends on
gate at 77 K-a speed rivaling that of the Josephson Junction). the number of logic gates which must serially stabilize before
However, the interpretation of the Table I data is complex; the output reaches its correct state. This factor ranges from
performance is expected to vary with gate length and width 2Td for a complementary-clocked NAND/NOR implemented
and with other factors, such as source resistance and parasitic flip-flop (Fig. 8(d)) to 57d for the D-type flip-flop shown in
capacitance. At gate lengths in the 0.5- to 1.5-pm range, trans- Fig. 8(b). Thus equal gate delays will produce 2.5 times higher
conductance shouldincrease roughly as l/Lgat smallgate clock frequencies in the former circuit than in the latter.
biases abovethreshold (avoiding velocity saturation effects). Table I1 and Fig. 9 present a comparison of speed and power
Thus a shorter gate length device should provide higher current of a variety of frequency divider approaches. The propagation
(Zds) at fixed logic swing and load capacitance, and therefore delays determinedfromthe dividing frequencies of all the
will reduce propagation delay. An increase in gate width (wg) depletion-mode circuits are fairly close to those obtained from
will directly increase Zds at a given gate bias. While the device ring oscillator evaluation. This indicates that the speed of the
44 PROCEEDINGS OF THE IEEE, VOL. 70,NO. 1 , JANUARY 1982
Fig. 10. Photomicrograph of an 8 X 8 multiplier chip. The chip,
including bonding pads, covers a 2.7-mm X 2.25-mm area.
logic gate of the depletion-mode circuits is not greatly reduced TABLE 111
by fanouts of 2 or 3. The higher toggling frequencies (also at COMPARISONGaAs LSI 8 X 8 BIT PARALLEL
P R O M N E WITH STATEOFTHEART
E F R A C SILICON BIPOLAR
the expense of high power) demonstrated by the HP [ 201 BFL
circuits and the LEP  BFL circuits are primarily the conse- MPX-8H3-1 IULTIPLV TIRE POYER D I S S I P A T I O h .IULTlPLV T I H E -
quence of the use of complementaryclocked master-slave flip (NAYOSECONDSI
(UATTS) POYER PRODUCT
Rl ] 5.2 2.2 11.4 ( N a n o s e c - U a t t )
flops implemented with NAND/NOR gates. This complementary (GaAs) 16.8 0.9 15. 1
clock design can also be implemented in SDFL by using the 6.4 M"T(21 19 R4
oR/NAND gate discussed in Section 11.
1.2 TRW(31 45 54
With enhancement-mode GaAs FET's, a divide by eight fre- *OX-WJ-1
quency counter (gate length of 0.6 pm) has demonstrated a pHn
45 1.4 63
maximum clock frequency of 3.8 GHz with a power dissipation MH i 125
of 1.2 mW/gate. This corresponds to a gate delay time of 66 67558
ps and a speed-power product of 79 fJ. This is a significant ( I ) Under D e r e l o p n e n tM t e r i a l :
( 2 ) Uses Cdrry Lookahead
achievement. However, the enhancement-mode FET approach (3) C o n t a i n sn i l t i p l i e r b r a y and C u t p u t Latches m l y (No I n p u t Latches.)
hasa basic limitation on the permissible logic voltage swing Eftlnated t d t e Count = 900
"0.6 V, duetothe onset of gateconduction.To achieve
reasonable LSI/VLSIyields, further improvement gate thresh-
in bit, requiredover 1000 NOR gates (about3000 FET's and
old voltage control is required. On the other hand,most of the 3000 Schottky diodes) for the complete circuit. This level of
BFL depletion-modeapproaches would likely be prohibited complexity would clearly qualify this as an LSI GaAs digital
from achieving LSI/VLSIcomplexities duetothe relatively circuit and also the most complex GaAs circuit to be success-
high power dissipation required and the lower packing density. fully demonstrated to date.
To date,theSDFLapproach appears to be the only one The best performance observed on the 8 bit multiplier corre-
meeting the powerdissipation,gate density, and fabrication sponds to a propagation delay of 150 ps/gate at a power dissi-
yield required for LSI. In fact, the first GaAs LSI circuits to pation of about 2 mW/gate. At this speed, a full 16bit product
be reported have utilized the depletion-modelowpinchoff would be available every 5.25 ns. Lower power operation 0.6
voltage SDFL approach. As shownby the results in Table I mW/gate was also possible (using lower pinchoff voltages) at
and 11, the 1-pm SDFL circuits provide a middle ground be- the still respectable multiply time of 16.8 ns. This performance
tween the potentiallylower power but more difficult to control is summarized in Table 111 and contrasted to the reported per-
EIDCFL circuits and the higher power, higher pinchoff voltage, formance of state-of-the-art silicon-based multipliercircuits.
BFL approaches. The two best Si multipliersutilize 2jlm. bipolar technology
The LSI circuit recently demonstrated is a parallel multiplier , . The best speed of the 1-pm GaAs MESFET IC is
. This circuit, consisting of NOR gate full adders and half about 4 times better than that of the fastest Si 8 bit multiplier
adders in a regular array, forms the binary product of two 8  employing input bit recording  and carry-look-ahead
bit words. The planar, localized-implant fabrication adders. Even faster GaAs multipliers (1.5 to 3 ns) would be
approach, described in Section 111, was used to process the expected if these same circuit approaches were to beutilized.
2.25 x 2.7 chip shown in Fig. 10. This 8 X 8 multiplier, which The successful fabrication of theSDFL 8 X 8 multipliers
also contained D-type flip-flop latches every input and output brings the GaAs technology into the realm of LSI while ad-
LONG et al.: HIGH SPEED GaAs IC’s 45
vancing the state-of-the-art for multiplier chips. The propaga- circuits,”Proc. IEEE, this issue, pp. 13-25.
tion delay of 150 ps/gate observed on the 8 X 8 multiplier is [ 111 R. Zuleeg, J. K. Notthoff, and K. Lehovec,“Femtojoule high-
speed planar GaAs E-JFET logic,” IEEE Trans Electron Devices,
in good agreementwith the results of much simpler GaAs SDFL VOl. ED-25, Qp. 628-639, June 1978.
circuits such as ring oscillators and frequency dividers. [ 121 K. Lehovec and R. Zuleeg, “Analysis of GaAs FET’s integrated
logic,” IEEE Trans Electron Devices,vol. ED-27, pp. 1074-1091,
T i high speed of operation indicates that the extension of June 1980.
the planar SDFL circuit approach to the LSI level of complex- [ 131 G. Nuzillat, G. Bert, T. P. Ngu, and M. Gloanec, “Quasi-normally-
ity does not result in significant speed degradation. The low off MESFET logic for high-performance GaAs IC’s,’’ IEEE Trans.
Electron Devices, vol. ED-27, pp. 1102-1108, June 1980.
power dissipation on the 8 X 8 multipliers also indicates that [ 141 N. Yokoyama, T. Mimura, and M. Fukuta, “Planar GaAs MOSFET
the SDFL approach is a suitable candidate for theVLSI range integrated logic,” IEEE Trans. Electron Devices, vol. ED-27, pp.
of complexity if further modest reductions in power per gate 1124-1127, June 1980.
[ 151 L. Messick, “A dc to 16GHz Indium Phosphide MISFET,” Solid-
are achieved. State Electron., vol. 23, pp. 551-555, 1980.
[ 161 S. Judaprawira et aL, “Modulation doped MBE GaAs/nAl+a, - x
V. CONCLUSION As MESFET’s,” IEEE Electron Device Lett., vol. 1, EDL-2, pp.
14-15, Jan. 19, 1981.
GaAs has matured as a semiconductor material t o provide a
viable IC technology.Significant advantages inperformance
1171 T. Mimura, S. Hiyamizu, T. Fujii, and K. Nanbu, “A new field-
effect transistor with selectively doped GaAs/n-Al,Ga,
heterojunctions,” Japan. J. AppL P h y s L e t t , voL 19, no. 5,
over conventional silicon IC’s have been demonstratedwith pp. 225-227, 1980.
J. K. Notthoff and C. H. Vogelsang, “Gate design for DCFL with
the operation of GaAs circuits at high speed and low power. GaAs E-JFET’s,” in Research Abstracts of First Annual Gallium
Furthermore,theability to achieve LSI complexities with Arsenide Integrated Circuit Symp., Lake Tahoe, Sept. 27, 1979,
GaAs (1000 gates)has also been demonstrated. Further im- Paper 10.
R. Zuleeg, Jap. J. AppL P h y s , vol. 19, pp. 315-318, 1980.
provements in the performance of GaAs IC’s are still possible R. L. VanTuyl, C. Liechti, R. E. Lee,and E. Gowen, “GaAs
throughthe use of heterojunctions ina new generation of MESFET logic with 4-GHz clock rate,” IEEE J. SolidState Cir
devices. cuits, vol. SC-12, pp. 485-496, Oct. 1977.
R. C. Eden, B. M. Welch, and R. Zucca, “Lowerpower GaAs
Today,strong developmentprogramsexist inthe U.S.A., digital IC’s using Schottkydiode-FET logic,” 1978 Int.Solid
Europe, and Japan,and applications of GaAs logicinto systems State Circuits Con$ Dig. Tech Papers, pp. 68-69, Feb. 1977.
R.C. Eden, F. S. Lee, S. I. Long, B. M. Welch, and R. Zucca,
are anticipated soon. The first applicationsare expected to “Multi-level logic gate implementation in GaAs IC’s using
take place in the form of MSI circuits utilized at the front end Schottky diode-FET logic,” 1980 Int. Solid State Circuits Cons.
of high speed digital systems. In the near future, furtherappli- Dig. Tech. Papers, pp. 122-123, Feb. 1980.
S. I. Long, F. S. Lee, R. Zucca, B. M. Welch, and R. C. Eden,
cations of MSI/LSI GaAs circuits are expected in high speed ‘“SI high-speed low-power GaAs IC’s using Schottky diode FET
signal processing. A scenario can be envisioned where success- logic,” IEEE Trans. Microwave Theory T e c h , vol. MTT-28, pp.
466-471, May 1980.
ful utilization of GaAs IC’s will stimulate further development,
(241 C.A. Liechti, “GaAs FET logic,” 1976 Int. GaAs Symp., Inst.
which will, in turn, encourage further applications. Phys Con$ Series33a, ch. 5, pp. 227-236, 1977.
The potential for long range application of GaAs digital IC’s 1251 H. Ishikawa, H. Kusakawa, K. Suyama,and M. Fukuta, “Normally-
off type GaAs MESFET for low-power high-speed logic circuits,”
also exists in computer mainframes. A forecast on whether, or 1977 I n t Solid State CircuitsCon$, Dig. Tech. Papers, pp.
when and how this type of application may occur is presently 200-201, Feb. 1977.
difficult due to the many considerations which determine the M. Fukuta, K. Suyama,and H. Kusakawa, “Lowpower GaAs
digital integrated circuits with normally off MESFET’s,” IEEE
choice of an IC technology for a computer mainframe. How- Trans Electron Devices, vol. ED-25, p. 1340, Nov. 1978.
ever, the application of GaAs IC’s for this purpose is becoming G. Bert, G. Nuzillat,and C. Amodo, “Ferntojoule logic circuit
increasingly feasible with the advance of this high speed using normally-off GaAs MESFET’s,” Electron. Lett., vol. 13,
pp. 644-645, Oct. 1977.
technology. . R. E. Lundgren, C. F. Krumm, and R. L. Pierson, “Fast enhance-
ment-mode GaAs MESFET logic,” presented at 37th Annu. Dev.
Research Conf., Boulder, CO., June 25-27, 1979.
REFERENCES T. Mizutani, N. Kato, K. Osafune, and M. Ohmori, “Gigabit logic
operation with enhancement mode GaAs MESFET IC’s,’’ IEEE
[ 11 T. Mizutani, N. Kato, S. Ishida, K. Osafune, and M. Ohmori, Trans. Electron Devices, to be published.
“ G a s gigabit logic circuits using normally4FF MESFET’s,” G. Nuzillat, F. Damay-Kavala, G. Bert,and C. Amodo,“Low
Electron. Lett., vol. 16, pp. 315-316, Apr. 24, 1980. pinch-off voltage FET logic (LPFL): LSI oriented logic approach
[ 2 ] M. Cathelin, M. Gavant, and M. Rocchi, “A 3.5 GHzsingle-clocked using quasinormally off GaAs MESFET’s,” Proc. I n s t Elec. Eng.,
binary frequency divider on GaAs,” h o c . Inst. Elec. Eng., vol. vol. 127, pt. 1, no. 5, pp. 287-296, Oct. 1980.
127, pt. I, no. 5, pp. 270-277, Oct. 1980. 1311 K. Suyama, H. Kusakawa, and M. Fukuta, “Design andperfor-
[ 3 ] M. Cathelin and G. Durand, “Logic IC’s using GaAs FET’s in a mance of GaAs normally-off MESFET integrated circuits,” IEEE
planartechnology,” L’ondeElectrique, vol. 58, pp. 218-221, Trans. Electron Devices, vol. ED-27, pp. 1092-1097, June 1980.
Mar. 1978. [321 N. Yokoyama, T. Mimura, M. Fukuta, and H. Ishikawa, “A self-
[ 4 ] G.L. Troeger, A. F. Behle, P. E. Friebertshauser, K. L. Hu, and aligned source/drain planar ultrahigh
device for speed GaAs
S. H. Watanabe, “Fully ion implanted planar GaAs E-JFET pro- MESFET VLSI’s,” 1981 Int.SolidStateCircuitsCon$, Dig.
cess,” I979 Int. Electron Devices Meeting, Tech Dig., pp. 497- Tech. Papers, Feb. 1981.
500, Dec. 1979.  P. T. Greiling, R.E. Lundgren, C. F. Krumm, and R.F. Lohr, Jr.,
. _ _
[ 51 B. M. Welch et aL, “LSI processing technology for planar GaAs “Why design logic with GaAs and How? MSN, up. 48-60. Jan.
integrated circuits,” IEEE Trans. Electron D w . , vol. ED-27, pp. 1980.
1116-1 123, June 1980.  F. Katano, T. Furutsuka, and A. Higashisaka, “High speed
[ 61 H. Horikoshi et aL, “An example of LSI-oriented logic implemen- normallyaff GaAs MESFET integrated circuits,” Electron. Lett.,
tation in a large-scale computer, theHITAC M-POOH,” COMPCON 236-239, Mar. 1981.
vol. 1 7 , 1 1 0 . 6 , ~ ~ .
Tech Papers, pp. 62-65, Spring 1980. [ 35 ] TRW MPY8HJ-1, See “Digital processing gets a boost from bipolar
[ 7 ] R. J. Blumberg and S. Brenner, “A 1500 gate, randomlogic, large LSImultipliers,” EDN Magazine, vol. 20, pp. 38-43, Nov. 5 ,
scale integrated (LSI) masterslice,” IEEE J. SolidState Circuits, 1978.
V O ~ .SC-14, pp. 818-822, Oct. 1979.  “Single-chip 8 X 8multiplierforms16-bitproduct in 19 nsec,”
[ 8 ] F. S. Lee et aL, “High speed LSI GaAs digital integrated circuits,’’ EDNMagazine, vol. 22, p. 152, Dec. 15, 1980.
GaAs IC Symp. Abstracts, Las Vegas, NV, Nov. 1980.  “2 bit-by4 bit parallelbinarymultipliers,”Suppl. to the TTL
[ 91 R. C. Eden et aL, “The prospects for ultra-high speedVLSI G a h Data Book, Texas Instruments, Incorporated, 1974.
digital logic,” IEEE J. SolidState Circuit, voL SC-14, pp. 221-  R. Zucca et aL, “Process evaluation test structures and measure-
239, Apr. 1979. ment techniques for a planar GaAs IC technology,” IEEE Trans.
[ l o ] H. Kroemer,“Heterostructurebipolartransistorandintegrated Electron Devices, vol. ED-27, pp. 2292-2298, Dec. 1980.