Noise Coupling in Integrated Circuits

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Noise Coupling in Integrated Circuits Powered By Docstoc
					Contents



1      FUNDAMENTAL CONCEPTS                                     1
1.1      What is Noise Coupling                                 1

1.2      Resistance                                              3
   1.2.1   Resistivity and Resistance                            3
   1.2.2   Wire Resistance                                       4
   1.2.3   Sheet Resistance                                      5
   1.2.4   Skin Effect                                           6
   1.2.5   Resistance of Semiconductors                          7

1.3      Resistive Coupling                                      9
   1.3.1   Resistive Coupling in Lightly Doped Substrates       10
   1.3.2   Resistive Coupling in Heavily Doped Substrates       11
   1.3.3   Resistive Coupling Through Voltage Drops             12

1.4      Inductance                                             13
   1.4.1   Electric Current Flowing Through a Wire              13
   1.4.2   Conductive Wire Encircled by Magnetic Field          14
   1.4.3   Time Varying Current Flowing Through a Wire          15
   1.4.4   Self-Inductance of a Straight Wire Segment           16

1.5      Inductive Coupling                                     19


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     1.5.1     Mutual Inductance                                    19
     1.5.2     Total Inductance                                     21
     1.5.3     Loop Inductance                                      22
     1.5.4     Loop Mutual Inductance                               24

1.6      Capacitance                                                25
   1.6.1   Parallel Plate Capacitor                                 26
   1.6.2   Semiconductor Junction Capacitance                       27

1.7      Capacitive Coupling                                        30
   1.7.1   Wire to Wire Capacitive Coupling                         31
   1.7.2   Decoupling Capacitors                                    32


2        INTEGRATED CIRCUITS FABRICATION                            37
2.1          Introduction                                           37

2.2      Integrated Circuits Fabrication Technology                 37
   2.2.1   Wafer Manufacturing                                      38
   2.2.2   Device Manufacturing                                     39
   2.2.3   Bipolar Process                                          43
   2.2.4   CMOS Process                                             50
   2.2.5   BiCMOS Process                                           59
   2.2.6   Silicon on Insulator (SOI) Process                       60

2.3      Packaging Technology                                       61
   2.3.1   Wire Bonding Package                                     62
   2.3.2   Tape Automated Bonding Package                           62
   2.3.3   Flip-Chip Package                                        63

2.4          Printed Circuit Boards Technology                      65

2.5      Power Distribution                                         66
   2.5.1   Power Distribution Model                                 67
   2.5.2   Decoupling Capacitors                                    70
   2.5.3   Example of a Power Distribution Model                    73


3        MECHANISMS OF NOISE GENERATION                             75
3.1          Introduction                                           75

3.2      Substrate Noise Generation                                 76
   3.2.1   NPN Transistor in Common-Emitter Configuration           77
   3.2.2   NPN Transistor in Cascode Configuration                  79
   3.2.3   NPN Transistor in Emitter-Follower Configuration         80
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    3.2.4      NPN Transistor in Common-Base Configuration              80
    3.2.5      PNP Transistor in Common-Emitter Configuration           80
    3.2.6      PNP Transistor in Common-Base Configuration              82
    3.2.7      PNP Transistor in Cascode Configuration                  83
    3.2.8      PNP Transistor in Emitter-Follower Configuration         83
    3.2.9      NMOS Transistor in Common-Source Configuration           86
    3.2.10       Impact Ionization                                      88
    3.2.11       NMOS Transistor in Cascode Configuration               90
    3.2.12       NMOS Transistor in Source-Follower Configuration       91
    3.2.13       NMOS Transistor in Common-Gate Configuration           91
    3.2.14       PMOS Transistor in Common-Source Configuration         91
    3.2.15       PMOS Transistor in Cascode Configuration               94
    3.2.16       PMOS Transistor in Source-Follower Configuration       94
    3.2.17       PMOS Transistor in Common-Gate Configuration           95
    3.2.18       Schottky Diodes                                        95
    3.2.19       ESD Protection Structures                              97
    3.2.20       Resistors                                              99
    3.2.21       Capacitors                                            105
    3.2.22       Inductors                                             107
    3.2.23       Noise Generation Through Bias Contacts                110

3.3      Power Supply Noise Generation                                 112
   3.3.1   Transient Supply Currents                                   112
   3.3.2   Power Supply Noise Coupling into the Substrate              117
   3.3.3   Power Supply Noise Coupling into the Package and PCB        118
   3.3.4   Power Distribution Resonance                                119


4       MECHANISMS OF NOISE PROPAGATION                                125
4.1          Introduction                                              125

4.2      Propagation Through Chip Substrate                            126
   4.2.1   Propagation Through Lightly Doped Substrates                127
   4.2.2   Propagation Through Heavily Doped Substrates                133
   4.2.3   Propagation Through Silicon-On-Insulator (SOI) Substrates   134

4.3          Propagation Through Power Distribution                    136

4.4          Propagation Through Crosstalk                             140


5       MECHANISMS OF NOISE RECEPTION                                  145
5.1          Introduction                                              145

5.2          Noise Reception Through Substrate and N-well Contacts     147
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    5.2.1     Noise Reception in Standard CMOS Processes              147
    5.2.2     Noise Reception in Triple Well CMOS Processes           149
    5.2.3     Noise Reception in SOI CMOS Processes                   151
    5.2.4     Noise Reception in Silicon Bipolar Processes            152

5.3      Noise Reception in Bipolar Transistors                       155
   5.3.1   Noise Reception in NPN Transistors                         155
   5.3.2   Noise Reception in PNP Transistors                         157

5.4      Noise Reception in MOS Transistors                           160
   5.4.1   Noise Reception in NMOS Transistors                        160
   5.4.2   Noise Reception in PMOS Transistors                        162

5.5      Noise Reception in Resistors                                 165
   5.5.1   Noise Reception in Base Resistors                          165
   5.5.2   Noise Reception in Emitter Resistors                       166
   5.5.3   Noise Reception in Polysilicon Resistors                   167

5.6      Noise Reception in Capacitors                                169
   5.6.1   Noise Reception in Diffusion Capacitors                    169
   5.6.2   Noise Reception in MOS Capacitors                          170

5.7         Noise Coupling Effects on Latch-up                        171


6       NOISE COUPLING MEASUREMENT                                   175
6.1         Introduction                                              175

6.2         Requirements for Making Accurate Measurements             176

6.3         P+ Diffusion Contacts and Sense Lines                     177

6.4         Backgate Modulation Sensors                               180

6.5         On Chip Digitizing Sensors                                182

6.6         Differential Amplifiers                                   185

6.7         DC Coupled Substrate and Power Supply Differential Sensors 186

6.8         On Chip Sampler                                           193

6.9         Comparison of the Measurement Techniques                  196
Contents                                                                ix


7      NOISE COUPLING SUPPRESSION                                      199
7.1      Introduction                                                  199

7.2      Suppression of Noise Generation                               200
   7.2.1   Differential CMOS Logic                                     200
   7.2.2   Single Ended Current Steering CMOS                          201
   7.2.3   Current Balanced CMOS                                       203
   7.2.4   Supply Current Shaping                                      204
   7.2.5   Power Distribution Impedance                                205

7.3      Suppresion of Noise Propagation                               212
   7.3.1   Using Lightly Doped Substrates Instead of Heavily Doped     212
   7.3.2   Buried Substrate Shields: Faraday Shield                    213
   7.3.3   Buried Substrate Shields: Dielectric Shield (SOI process)   215
   7.3.4   Buried Substrate Shields: Junction Shield                   217
   7.3.5   Shunting Guard Rings                                        218
   7.3.6   High Resistance Guard Rings                                 220
   7.3.7   Active Guard Rings                                          221

7.4      Suppression of Noise Reception                                223
   7.4.1   Differential Versus Single Ended Circuits                   223
   7.4.2   Shunting Through Substrate Contacts                         226
   7.4.3   Circuit Level Compensation                                  227

7.5      Design Example 1: Circuit Level Compensation for Substrate
Noise Coupling in Common-Source NMOS Amplifier                      228
   7.5.1   Architecture and Functionality                           228
   7.5.2   Experimental Results                                     231

7.6      Design Example 2: Circuit Level Compensation for Substrate
Noise Coupling in NMOS Active Loads                                 233
   7.6.1   Architecture and Functionality                           233
   7.6.2   Experimental Results                                     235


8      NOISE COUPLING SIMULATION                                       239
8.1      Introduction                                                  239

8.2      Using Software Simulation Tools                               240
   8.2.1   Overview of Noise Coupling Simulation                       240
   8.2.2   Post-Layout Extraction and Simulation                       241
   8.2.3   Pre-Layout Extraction and Simulation                        242
   8.2.4   Early Estimation in the Architectural Stage of the Design   243
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8.3      Early Prediction of Noise Coupling                             244
   8.3.1   Modeling Requirements                                        244
   8.3.2   Modeling Assumptions                                         245
   8.3.3   Methodology                                                  246
   8.3.4   Estimation of the Digital Switching Noise                    247
   8.3.5   Two-Dimensional Analog Mesh                                  251
   8.3.6   Alternate One-Dimensional Analog Mesh                        255
   8.3.7   Digital Circuits, Package, and PCB Power Distribution        257

8.4      Example of Early Prediction of Noise Coupling                   259
   8.4.1   Model Construction                                            259
   8.4.2   Simulation Results and Correlation with Measurements          260