High aspect ratio etching and application in InP-based photonic

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					High aspect ratio etching and application in InP-based           performed.
             photonic integrated circuits
    F. Karouta, B. Docter, A.A.M. Kok, E.J. Geluk,            The starting process parameters of the Cl2:Ar:H2
           J.J.G.M. v.d. Tol and M.K. Smit                    chemistry were: Cl2:Ar:H2 (7:4:12 sccm), ICP power of
     COBRA Inter-University Research Institute on             1000W, RF power of 120W, electrode temperature of
             Communication Technology                         200°C, pressure of 4mTorr [4]. This process etches
         Eindhoven University of Technology                   ~3µm/min in a large open InP area, while the selectivity
           Faculty of Electrical Engineering                  towards SiOx and SiNx are 14:1 and 12:1 respectively.
    P.O.Box 513, 5600 MB Eindhoven, Netherlands               However those parameters needed a certain adjustment
               E-mail: f.karouta@tue.nl                       for the two applications i.e. the 1st order DBR gratings
                                                              and the PhC pillars:
Photonic crystals (PhC) are extensively investigated for      • 1st order DBR gratings: the ICP and RF powers have
application in advanced photonic circuits due to their            been changed to 750 and 150 W respectively. The
potential for miniaturization and possible new functions.         lower ICP power results in a lower plasma density
However to achieve 1-D and 2-D PhC patterns in low                while the higher RF power increases the ion
vertical index contrast the technological requirements are        bombardment. The final result was a lower etching
stringent as very high aspect ratio etching is a must to          rate and a reduced lag effect.
achieve low optical losses in InP-based structures. The       • PhC pillars: as this application requires mainly a
etching depth should be at least 1 µm below the                   higher ion bombardment, we found that increasing the
active/waveguide layer with smooth and vertical sidewalls         RF power to 140W improves the profile (verticality)
[1-2]. It is well known that reducing the feature size            of the pillars to 3 µm depth.
influences directly the achieved etching depth: the smaller
the hole, the shallower the depth. This phenomenon is         For PhC deep holes, the optimized ICP process consists of
known as RIE-lag [3]. Thus, deep etching requires a           Cl2:O2 (14:2 sccm), 1000W ICP, 160W RF, electrode
delicate balance in the choice of chemistry, process          temperature of 200°C, pressure of 1.2 mTorr and etching
parameters and the mask thickness.                            time of 1 min. A thermal adhesive is used between the
                                                              sample and the Si-carrier wafer. The etching depth is
In this work we have investigated high aspect ratio           about 7 µm in an open InP area while PhC holes were
etching in low index contrast InP using a high density        about 2.7 µm (in a cylindrical shape) for 170nm diameter
inductively coupled plasma (ICP) plasma reactor. Two          holes [5]. With the 500nm SiOx mask layer the etching
types of chemistries were investigated:                       time could be increased up to 1min 40sec resulting in an
1. Cl2-Ar:H2 at 4mTorr [4]                                    etching depth of >10 µm (large area), 3.5 µm in a
2. Cl2:O2 at 1.2 mTorr [5]                                    cylindrically shaped holes of 170nm diameter. By means
The first chemistry was used for fabricating 1st order        of this 3-level masking an important increase of aspect
distributed Bragg reflectors (DBR) gratings and 2D-           ratio was achieved up to a value >20 for holes with a
square-lattice PhC pillars while the second chemistry was     diameter of 130nm.
used to fabricate 2-D triangular-lattice PhC holes.           In the presentation we will also report the results of
Typical PhC patterns in InP have feature sizes in the order   devices realized using the above described technology
of 200-300 nm which do require the use of electron-beam       such as lasers integrated with DBR mirrors and
lithography (EBL). In our experiments we use a 30keV          polarization filters using PhC pillars. We shall also
RAITH-150 system in association with the positive E-          discuss the possibility of integrating PhC deep holes or
beam resist ZEP520A with a thickness of 320nm.                DBR gratings mirrors in standard waveguide technology.
Subsequently the patterns are transferred to a 400nm SiNx
that acts as a hard mask during the ICP etching. For          References
opening the SiNx mask we optimized the RIE process            1. R. Ferrini, R. Houdré, H. Benisty, M. Qiu, J.
towards its selectivity with respect to the ZEP layer. The       Moosburger, “Radiation losses in planar photonic
optimized RIE process uses CHF3 at an RF power of 50W            crystals: two-dimensional representation of hole depth
and at a pressure of 15 mTorr. With this technology it was       and shape by an imaginary dielectric constant”, J. Opt.
not possible to increase the mask thickness of SiNx              Soc. Am. B20, 469 (2003).
beyond 400nm. This allows transferring the PhC patterns       2. R. Ferrini, B. Lombardet, B. Wild, and R. Houdré,
of holes down to 200nm diameter. For smaller holes or a          “Hole depth- and shape-induced radiation losses in
thicker mask the ZEP layer is no longer sufficient. We           two-dimensional photonic crystals”, Appl. Phys. Lett.,
have investigated the use of a 3-level masking technique         82 (7), 1009 (2003).
[4] to enable the use of a thicker SiOx (420-500 nm) mask     3. R.A. Gottscho, and C.W. Jurgensen, “Microscopic
layer. Apart from the increased thickness, the SiOx mask         uniformity in plasma etching”, J. Vac. Sci. Technol.
presents the advantage of having a better resistance to the      B10, 2133 (1992).
ICP process as compared to SiNx. A 50 nm Cr layer is          4. Docter, B.; Geluk, E.J.; Karouta, F.; Sander-Jochem,
used as an intermediate layer between the SiOx layer and         M.J.H.; Smit, M.K., “Deep etched DBR gratings in
the E-beam resist. The process sequences differ                  InP for photonic integrated circuits”. proc. IPRM
depending on the PhC patterns:                                   2007, 14-18 May 2007, Matsue, Japan, 2007, pp. 226-
a. The 1st order DBR gratings and the PhC holes were             228.
    patterned in a 320nm of ZEP520A, subsequently the         5. C.F. Carlström, R. van der Heijden, F. Karouta,
    Cr is etched in an ICP process Cl2:O2 process; then          E. van der Drift, R.W. van der Heijden and H.W.M.
    removal of resist residues as well as the Cr in a            Salemink, “Cl2/O2-inductively coupled plasma etching
    stripper before proceeding with the ICP etching.             of deep hole-type photonic crystals in InP”. Journal of
b. The PhC pillars were patterned through a lift-off             Vacuum Science and Technology, B 24(1), Jan/Feb
    process using a PMMA layer followed by etching the           2006, pp 6-9.
    SiOx mask. After stripping the Cr the ICP process is