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Motherboard, also known as system board or motherboard; it installed in the chassis, is the most basic computer is one of the most important parts. Board is generally rectangular circuit board, installed above the main circuit composed of a computer system, generally have BIOS chips, I / O controller chip, keyboard and panel control switch interface lamp connectors, expansion slots, the motherboard and the card DC power supply connectors and other components.
DDR System Design Considerations Integrated Technology Group Micron 1 DDR Overview 2 SSTL2 Signal Levels Driver Receiver December, 00 3 SSTL2 Double Ended Termination VTTTermination Island VTT/VREF Generator SSTL_2 PC266 PC266 Address/Cmnd SDRAM Address / Command SDRAM VTT Termination Island Reg. Reg. Chip Selects DIMM DIMM Chipset “North Bridge” SSTL_2 Data/Strobe/Mask December, 00 4 SSTL2 Single Ended Termination VTT/VREF Generator SSTL_2 PC266 PC266 Address/Cmnd Address/Command SDRAM SDRAM VTT Termination Island Reg. Reg. Chip Selects DIMM DIMM Chipset “North Bridge” SSTL_2 Data/Strobe/Mask December, 00 5 Use Single Parallel Termination Resistor With Series Resistor m Lower system cost m Easier motherboard route m Improved bandwidth m Lower skew due to ISI m Reduced skew due to crosstalk if done properly – Consider crosstalk effects in the connector pinout December, 00 6 Double Data Rate Motherboard Components VDD generator switching regulator Series termination Series termination resistor packs resistor packs VDD VDD Differential Differential VTT VTT TT clock synthesizer clock synthesizer Processor Processor VTT/REF active NB NB VTT/REF active termination voltage termination voltage CLK CLK switching regulator switching regulator Four-layer motherboard VTT voltage island V TT voltage island de-couple thoroughly de-couple thoroughly V VSS to DD and VSS December, 00 7 Typical Signaling for DDR Main Memory m The values for the series and termination resistors vary depending on the system design December, 00 8 VTT/VREF Implementation 9 Goals of VTT and VREF Design m Minimize timing skew due to – Asymmetric logic highs versus logic lows – Noise on VREF or VTT – Offset of VTT relative to VREF – Drift of VREF or VTT over voltage and temperature – External component mismatch m Minimize cost m Minimize power dissipation December, 00 10 VREF Requirements m Track 50% of (VDDQ-VSSQ) over – Voltage – Temperature – Noise m Supplies minimal DC current (input leakage only) and only small transient currents – Input to NFET gates of a differential pair December, 00 11 VREF Tracking to VDDQ VDDQ A VDDQ B VREF VREF A B VSSQ VSSQ VDDQ C VREF C VSSQ December, 00 12 VREF Recommendations m Use global VREF distribution scheme – Eliminates variation and tracking of multiple generators – Best performance if kept clean m Use simple resistor divider with 1% or better accuracy – Inexpensive to use – Tracks voltage and temperature well m Use VREFOUT pin of ML6554 – Resistor divider is integrated on-chip – Fewer external components – Best accuracy and matching to V TT due to trimming – Minimizes DC error caused by the load current of multiple device input leakage December, 00 13 VREF Generation m Example of VREF generation using a resistor divider VDD VDDQ VDDQ VDDQ R VREF R VSS VSS VSS VSS Discrete Resistors or VREF ( OUT) of ML6654 December, 00 14 VREF Layout Recommendations m Maintain a 15-20 mil clearance from other nets m Use distributed decoupling scheme – Minimizes capacitor ESL – Localizes transient currents and returns m Simple implementation by routing on top signal layer trace – VREF is at connector pin 1 – Isolate VREF and/or shield with VDDQ and VSSQ December, 00 15 VREF PCB Routing December, 00 16 VTT Requirements m Track 50% of (VDDQ-VSSQ) over – Voltage – Temperature – Noise m Maintain <40mV offset from VREF over these conditions m Source and sink DC current for signal termination – Absolute maximum current is 2.6-2.9A for a 64/72-bit channel December, 00 17 VTT Recommendations m Several solutions exist that are tradeoffs of cost, integration, and performance – Standard analog components (Motorola, National, Fairchild, etc.) • High current output, good accuracy – Switching regulator with discrete MOSFETs (such as LTC1430) • High current output (10A), good accuracy, semi-integrated – Switching regulator with integrated MOSFETs (such as ML6554) • Adequate current output (3A) and accuracy, highest integration, lowest cost December, 00 18 VTT Recommendations (continued) m Use global VREF as input reference to minimize tracking error and offset m Use high-quality filter components – Low Rs on filter inductor – Low ESR and ESL on filter capacitor to minimize DC and dynamic offset • Recommend the use of multiple parallel capacitors and/or Sanyo OS-CONs to minimize ESR and ESL December, 00 19 VTT Regulation Circuit m VTT regulation circuit using Micro Linear ML6554 December, 00 20 VTT Layout Recommendations m Decouple to VSSQ – Decouple at both ends, and distribute decoupling across the island to localize transient currents and minimize ESL m Place termination resistors on a top layer V TT island – Island is at the end of the bus and non-obstructing – Use wide-island trace for current capacity – Place VTT generator as close to termination resistors as possible to minimize impedance (inductance) December, 00 21 VTT Island PCB Layout ML6554 Vtt Power Plane Termination Regulator Resistors Decoupling Capacitors December, 00 22 2.5 Volt Regulation m 2.5 volt regulation circuit using Linear Technology LTC1530-2.5 December, 00 23 2.5 Volt Regulation Layout m Regulated V2.5 ties to solid power plane under DIMM’s and DRAM controller portion of Samurai DDR Vcc Input LTC1530 Regulator Regulated V2.5 December, 00 24 Voltage Margining 25 VREF/VTT Margining m Use the V REF In pin on the ML6554 to margin V REF and VTT – VTT and VREF out follow VREF In m VREF specification is 0.49*VDD to 0.51*VDD m VTT specification is V REF +/- 40mV m Use simple resistor divider below connected to VREF In pin on ML6554 VDD VREF In On ML6554 1K 0.1uF 100 ohm Variable 1K 0.1uF Resistor December, 00 26 VDD Margining m VDD specification is 2.3 to 2.7 volts m To margin VDD change LTC1530-2.5 to LTC1530-ADJ m Adjust VDD with resistor divider R1/R2. December, 00 27 VDD Margining +5 volts input 2.5 Volt Vdd output R1 R2 December, 00 28 Board Implementation 29 Registered-Only Motherboard Topology VREF VTT/VREF Difntl CK/CK# Generator Clk Drvr Mem Clock SSTL_2 PC266 PC266 PC266 PC266 Address/Cmnd A A SDRAM A SDRAM A SDRAM SDRAM Reg. Reg. Reg. Reg. VTT Termination Island Chip Selects DIMM DIMM DIMM DIMM Chipset “North Bridge” SSTL_2 Data/Strobe/Mask December, 00 30 Unbuffered/Registered Motherboard Topology Vref Vtt/Vref Clocks Generator PC2100 PC2100 Address/Command B DDR B DDR Add/Comnd B VTT Termination Island DIMM DIMM Chipset PC2100 PC2100 Address/Command A DDR A DDR Add/Comnd A “North Bridge” Chip Selects DIMM DIMM Data/DM/DQS December, 00 31 PCB Considerations m PC2100 DDR can be implemented in a low-cost PCB (standard PC100 motherboard technology) m Standard pad, anti-pad and via sizes can be used m No additional PCB test requirements relative to PC100 December, 00 32 PCB Routing m DDR channel can be implemented in a 2S 2P board – Controller BGA ballout determines whether a four-layer board can be used, not the memory channel – Two signal layers to get from controller to series resistor – The channel can be routed on one signal layer from the series termination resistor out, with the exception of point-to-point signals December, 00 33 Reference Motherboard Routing m Maintain signal reference through DDR channel – Route signals on layers adjacent to a common reference plane. – Route each data group (8 x DQ + DQS + DM) on same layer to match propagation delays and minimize skew. – Address and control matching is less critical. – Separate data and control nets to minimize crosstalk. m Routing Rules – 5 mil trace/15 mil space on all in group SSTL nets – Connector rules: 5 mil trace, 2 mil space from antipad, 7 mils from trace December, 00 34 Micron Samurai DDR Trace length matching rules m Match trace lengths for each data group (8 x DQ + DQS + DM) to 0.1 inch from controller to first DIMM. m Match trace lengths to +/- 500 mils across the entire channel. m Match composite length from controller bond pad to first DIMM pad • LBGA + Lcontroller-R + LR-DIMM = matched m Length matching from last DIMM pad to parallel termination resistor is less critical December, 00 35 Length Matching from Controller to 1st DIMM Pin LC-R1 RS RT LBGA1 LR-D1 RS RT LC-R2 LR-D2 LBGA2 LBGA1 + LC-R1 + LR-D1 = LBGA2 + LC-R2 + LR-D2 December, 00 36 PCB Channel Routing Through the DIMMs m A 5-mil width / 7-mil space board will yield: – Three vertical signal-routing channels – Two diagonal signal-routing channels – Second layer void except for point-to-point signals – Lowest skew due to propagation-velocity mismatch between different signal layers December, 00 37 Routing Through DIMMs Series Resistors Two Diagonal Signals Three Vertical Signals December, 00 38 Termination Resistor Placement m Motherboard series resistors should be close to the first DIMM – Best performance for READ from last module • Limiting case – Simplifies routing and controller congestion December, 00 39 System Design Examples December, 00 40 DDR Memory Route 1st Layer December, 00 41 DDR Memory Route 2nd Layer December, 00 42 Reference Motherboard Stack-Up mReference board stack-up • 6 Layer Board Signal 1 4.5-Mils GND 6.5-Mils Signal 2 30-Mils Signal 3 6.5-Mils Power 4.5-Mils Signal 4 December, 00 43 Questions and Answers December, 00 44
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