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Motor Control - Brushless DC Motor Control

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					Motor Control - Brushless DC Motor Control

AN2227
Author: Andrey Magarita Associated Project: Yes Associated Part Family: CY8C27xxx GET FREE SAMPLES HERE Software Version: PSoC Designer™ 4.2 Associated Application Notes: AN2170

Application Note Abstract
The Application Note demonstrates a PSoC® implementation of brushless direct current (BLDC) motor control using sensorless, back-EMF technology.

The motor driver has the following features:

Introduction
BLDC motors are widely used in industrial applications, home appliances, and vehicle systems. Such motors consist of a multi-pole permanent magnet placed on the rotor and several windings [1]. Various methods can be employed to control the BLDC motor. The simplest way is to use rotor position sensors. The sensors can be optical, magnetic (Hall effect or magneto-resistance, effect-based) or inductive. However, sensors increase cost and add reliability problems in motors operating in harsh environments where demands for sensor robustness are high. The increasing power of embedded computing, coupled with lower prices for power semiconductors and microcontrollers, has allowed for more sophisticated methods of motor control. One popular technique is to use a back-electromagnetic force (backEMF) signal, which is induced by revolving the rotor permanent magnet around the drive coils. This Application Note describes how a BLDC motor driver can be built using back-EMF sensing.

Reliable motor start with and without load; Stable operation when the load on the drive shaft changes; Rotation speed stabilization with power supply and load fluctuations; Overload protection; Runtime rotation speed control using preset speed tables; Error diagnostics and recovery after failures. A distinctive feature of this driver is its use of three PSoC™ mixed-signal array low-pass filters (LPFs), built around PSoC’s switched capacitor (SC) blocks. These filters are second-order Bessel filters and used for phase delay in the drive phase switching mechanism, generating the optimal torque on the motor shaft. The proposed project uses a 75W BLDC motor with a nominal 220V power supply. However, the project can be adapted to motors with 12-, 24-, 48- or 120-volt power supplies; only the phase voltage resistive divider and the motor coil level translators (frequently named coil drivers) must be adapted to specific motors. Table 1 lists the main characteristics of a motor driver.

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Table 1. Driver Specifications
Parameter Number Phases Input Voltage Output Power Max Output Current Output Signal Frequency: Minimum Maximum Motor Motor Pole Pairs 3 220V AC ±20% 100W 3.5A 50 Hz 120 Hz BLDC, Sensorless 4 Value

For simplification, the driver status display LEDs and speed setting switches are omitted. Only a detailed view of the driver is provided in Figure 1. Power modules are fairly simple and not examined here. The driver consists of a bridge chip driver for the IGBT transistors and a current sense resistor for measuring current, which is proportional to the total bridge-arms current. The IGBT level translator converts the logic level signals from the PSoC (control bridge bus), into levels suitable for driving the IGBT bridges’ low and high sides. The International Rectifier IR2130 chip is used as the IGBT driver. This chip has elements to protect the bridge transistors from overcurrent conditions, a low-power voltage output stage, and internal dead time control. Such features let the PSoC concentrate its resources on motor control and react only when a complex DriverFault event is raised by the IR2130. Lower cost drivers can be used by integrating these features into the PSoC device.

Driver Flowchart
The driver flowchart is shown in Figure 1. The power circuit includes: AC input line noise filter, AC line LC filter, AC mains rectifier, A step-down regulator to produce regulated 15V and 5V electronic supplies (not shown on the flowchart), A three-phase power bridge with a level translator to control the bridge using low-power digital signals.

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Figure 1. BLDC Motor Driver Flowchart
3-phase Power Bridge

BLDC Motor AC Bus Input Filter and Rectifier DC Filter DC Bus N S

Control Bridge Bus Driver Fault AGND

Comp phase A

LPF phase A

CPU Core

MUX Comp phase B LPF phase B

MUX Comp phase C LPF phase C

MUX

PWM Generator 1.5 - 5 kHz PSoC

COMP + Internal Ref

Duty Cycle Conpensation

The device handles the following signals from the power driver circuit: Three voltage signals that are proportional to the output phase voltage of the IGBT driver. The voltage signal, which is relative to the DC bus voltage. This signal is the PSoC analog ground (AGND). The resistive divider attenuates this signal to double the phase signals. Driver fault signal, which indicates that at least one fault event has occurred. The phase voltage signals enter the LPFs. Their cutoff frequency is three times higher than the phase switching frequency generated by the motor driver. The PSoC analog blocks process the phase voltages. As mentioned above, PSoC's AGND is floating and proportional to half the DC bus voltage, which is the rectified and filtered AC main voltage.

LPFs serve two functions. The first is to generate the necessary phase delay for the motor phase voltages. Thirty degrees is optimum for motor operation in this application. The second function is to filter the phase voltage from the PWM frequency to generate a signal wave, which is close to sinusoidal. When the filtered signal crosses AGND, the internal comparator triggers and a falling or rising edge signal is determined. At runtime, the awaiting edge type and queried phase channel are determined in firmware. The comparator toggle initiates the interrupt, which is handled in the firmware. The PWM generator forms the pulse-with modulated signal for high side bridge. The low side is controlled by constant, clear logic levels.

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The bridge high side PWM signal-routing is routed through an internal, firmware-controlled de-multiplexer. Note that the divided phase voltages are non-symmetric relative to AGND. This results in a strong influence when a small PWM duty cycle is set. To resolve this, a single compensation voltage is added simultaneously to the three phase signals. This voltage is inversely proportional to the PWM duty cycle and is generated by inverting and filtering the PWM output signal. DC bus voltage monitoring is implemented using the programmable voltage window comparator. If the voltage value on the DC bus (which powers the bridge high side) is above or below preset values, an interrupt is generated. This stops the motor, prohibiting operation in unsafe regions. If necessary, the analog-to-digital converter (ADC) can be used to monitor the DC bus voltage.

The main tasks of PSoC are to detect the position of the rotor using the generated voltage and to perform the phase switching in such a way that the new driving phase assists rotor revolution in the desired direction. This is the main condition of motor rotation stability. At first glance, a simple comparator on each phase is enough for proper operation. But back-EMF voltage has a more complex waveform, as shown in Figure 6 in Appendix D. In Figure 6, the PWM induced noise from neighboring windings can clearly be seen because the back-EMF winding is not loaded. There are a couple of ways to separate the back-EMF signal from unwanted noise. The first way is to use lowpass filtering to suppress the PWM-induced noise. The second method is to perform the phase voltage analysis when the PWM signal is inactive and the transient process of the winding is complete. This method is suitable for low PWM duty cycle values or for low-power motors, where inductive/capacitance cross coupling between coils is weak. The first method for noise suppression works well when it is implemented using PSoC LPFs. After filtering, the signal can easily be compared to a reference signal. All filters have phase delay. This delay depends on the signal frequency. Thus, the moment of windings commutation is changed at the same time as rotor revolution frequency. This can cause a loss of back-EMF signal synchronization or large torque ripples. Two solutions for this problem are: 1. Use the phase correction filter, analog or digital, to provide near-constant phase delay in the operational frequency range. Apply the tunable conventional switched capacitorbased filter.

Device Schematic
Device schematics are shown in Appendix A. The device has three elements. The power element includes: Supply-Line Filter Rectifier DC Bus Filter IGBT Transistor Bridge Voltage Converter for Low-Voltage Parts Supply The second element includes the IR2130 driver and dividers for the phase voltages. The third element contains the PSoC chip and speed selector. The speed selector is made with opto-couplers (which perform the galvanic isolation and are connected in parallel with DIPswitches for manual speed control) for external speed control. The three LED indicators display alarm events. These three parts are presented as three different circuit boards to provide better flexibility for specific motor applications.

2.

Device Operation Details
As mentioned above, the motor control system uses the sensor-less back-EMF technique. The motor winding functions operate as position sensors during rotor rotation. To accomplish this, the winding, working in sensor-position mode, is disconnected from the line supply. An Induced voltage is generated on the winding by the revolving magnet on the motor rotor. The sign and direction of the voltage change indicates the rotor pole location relative to fixed stator windings.

The first approach requires using complicated analog circuits or a more expensive DSP core for multi-channel signal processing. Such firmware must continuously read and process triple ADC conversions in real-time. There are other tasks for the drive controller, such as speed control. This makes the first approach difficult to implement with low-cost microcontrollers. The second approach requires external reconfigurable filters when conventional microcontrollers are used. This increases the driver price and complicates the circuit. However, PSoC has many firmware-controlled filters inside. Therefore, the best solution is to use the tunable LPF approach. This gives the optimal combination of price, quality, and complexity.

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The phase-delay filters can be placed in three PSoC columns and the built-in comparators can be used for output signal-crossing detection. Bessel filters are preferred since they provide linear phase delay versus frequency up-to-a cutoff point. The filter phase delay at the cutoff frequency is 90 degrees. The SC filter cutoff frequency is directly proportional to the filter clock rate, which allows stable phase delay in the full input frequency range by properly adjusting the filter clock frequency. This delay corresponds to a constant angle between the rotor poles and the stator windings in commutation moment. The phase delay angle is kept to 30 degrees in this application. The clock rate for the filters can be generated using the 16-bit counter with a programmable period, which can be allocated in the PSoC digital resources. Each SC filter has an output comparator that compares the filter output signal to AGND. The comparator output drives the comparator bus, which can be polled in software or trigger the interrupts. The built-in look-up table (LUT) allows triggering the interrupts on the rising or falling edge of the comparator bus, as pre-configured in the firmware. This feature is used to detect the back-EMF signals’ zerocrossing events and to generate signals for motor winding commutation. Each filter triggers interrupts which are handled in the firmware using a dedicated state machine to determine the next phase switching order and adjust the next interrupt polarity in runtime by modifying the content of the LUT control register. Note For every motor phase change, the next expected back-EMF signal polarity change direction is opposite the previous. Therefore, the comparator bus signal is inversed using the LUT in the triggered interrupt service routine (ISR) just after it starts. This provides hysteresis and additional noise immunity with regard to triggering multiple interrupts. Figures 2 and 3 illustrate key principles of driver and motor operation. A, B, and C are the voltages on motor phases. UP_A, DOWN_A, UP_B, DOWN_B, UP_C, and DOWN_C

are the bridge branch control voltages. UP is the upper (high side) branch. DOWN is the lower (low side) branch. A high level denotes the “on” state and a low level denotes the “off” state). INT is the interrupt signal on the phases. А30, В30, and С30 are delayed 30 degrees from the filtered voltages phase. One peculiarity of this architecture is that the control PWM voltage is supplied only at the upper bridge branch (high side). This produces an asymmetrical signal relative to half of the supply DC bus voltage. At low PWM duty cycles, the filtered phase voltage is much smaller than half the supply voltage. This, together with ripple on the DC bus (which is in the filter’s passband), can cause false triggers on the comparators at motor start. To prevent this, the compensation network uses an inversed PWM signal and biases the three filters together. This raises the filter’s DC component to half of DC supply voltage throughout the whole PWM duty cycle range. For this purpose, the inversed main PWM signal is routed to an external pin and filtered using an RC filter with a voltage divider (R4, C5, and R5 on the driver schematic). As a result, the C1 DC voltage is inversely proportional to the main PWM DC component. The divided voltage from C1 is summed with the back-EMF signal relative to PSoC digital ground and compensates the DC component relative to the divided "DC bus in" signal. Figure 12 illustrates the compensation voltages for minimum and maximum rotation speeds and minimum and maximum PWM duty cycle values. Channel_1 displays the inversed PWM signal and Channel_2 displays the compensation voltage.

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Figure 2. Driver Phase Signals
Phase Angle 180 240 300 0 60 120 180 240 300 0 60 120

A B

B C

C A 30o Delay A

B

C

Up_A

PWM

PWM

Down_A

Up_B

PWM

PWM

Down_B

Up_C

PWM

Down_C

Int A

Int B

Int C

A30

B30 AGND C30 Table State Outputs 0 0 1 1 2 2 3 3 4 4 5 5

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Figure 3. Rotor Positions for Various Phase Drive Signals*

A

+

A

A

0 C _ Alignment State B _ C A _ C B + _ A _ B +

C A _

B +

C A _

1 B +

2 C + A B + A C B

3 C + A + C B _ + + A B _

4 C A + B _ C A + B _

5 _
* See Figure 2 for Voltage Diagrams

C

B

_

C

B

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Driver operation contains the following stages: 1. Stop Stage The events register marks which event triggered the stop stage. If the counter does not exceed the preset threshold, the PSoC reads the speed-setting switches. In this state, all bridge drivers are switched off and the PSoC polls the speed-setting switches. This stage is exited by setting a non-zero speed value. See Table 3 for possible speed values. 2. Full Stop Stage The driver enters full stop stage after a preset number of failed motor start attempts. LED D2 indicates this stage. Only power-on-reset can reinitialize the driver from this stage. 3. Driver Preparation Stage The IR2130 driver has a bootstrap capacitor feature. The bootstrap capacitor must be charged to 10V before it can be used. Otherwise, high side outputs are turned off regardless of control signals. It is necessary to hold the bridge low-side power transistors on during this stage. To precharge the bootstrap capacitor, the low side transistors are switched on and the IR2130 output DriverFault is interrogated. If this signal is low, the low-side power transistors are turned off and the cycle is repeated. Transistor on/off switching is necessary to clear the error flag of the internal IR2130 driver. The driver preparation stage is illustrated in Figure 10. Channel_1 shows the voltage of the motor coil windings’ current sense resistor during initial PWM duty cycle determination. Channel_2 shows the "Fault driver" signal, which triggers when the current reaches 3.5A. The falling edge of this signal turns off bridge drivers inside the IR2130 and stores this state in the driver internal trigger. To make the IGBT driver operational, this trigger should be cleared. This trigger is cleared after a preset timeout by applying a falling edge on any low-side bridge control input. In the project associated with this Application Note, the trigger is reset by applying pulses to the phase C lower switch and polling the "Fault driver" in the software. If the "Fault driver" signal cannot be cleared (trigger cannot be reset) within 2 ms, motor start attempts are aborted and a motor start error flag is set.

4. Binding Stage There are two actions in the binding stage. First, the rotor is set at a predetermined start position by applying the drive voltage to two windings. Second, the maximum possible startup duty cycle is determined. This duty cycle is proportional to the motor start-up current. Rotor position, set during the binding stage, is shown in Figure 3 on the left. The necessary windings are commutated in accordance with the jump table. The PWM generator frequency is set to 1.5 kHz during this stage. The duty cycle is then incremented every 0.8 ms. After each PWM duty cycle increment, the DriverFault output is queried. If DriverFault equals zero, the motor winding current exceeds the maximum possible value. In the example project, this maximum value is set to 3.5A. The PWM duty cycle increment is finished as soon as a zero value at the Driverfault output is received. The amplitude of the AC ripple voltage also depends on DC filter parameters. If this measured duty cycle is directly selected as the maximum PWM pulse width, the overcurrent protection can prematurely turn off the motor. Therefore, the maximum measurable duty cycle ratio must be slightly decreased to prevent a false overcurrent protection trigger. The measured duty cycle is decreased by 25% and used to start the PWM duty cycle value in the example project. 5. Free Running Stage In this stage, the rotor begins rotation and is synchronized with a back-EMF signal. The stage the PWM operational frequency is set to is 5 kHz (it is possible to increase to 8 kHz). The timeout for every winding combination is determined using Table 4 in Appendix B, where units are PWM periods (200 us). This time is controlled by using reprogrammable 16-bit timer interrupts. The PSoC's CycleCounter is used for this purpose. The time intervals between phase switching events during motor start-up are much longer than during normal motor operation. As a result, the motor coils accumulate more energy during the driving stage. Considerable time is required to dissipate this energy though the IGBT's transistors’ reverse current protection diodes when the coil driving stops. The back-EMF signal can be received only when all stored energy is dissipated and the diodes are closed. This limits the time interval during which the backEMF signal can be sensed. The dedicated 16-bit counter is used to set the delay proportional to the current phase switching period. This determines the interval during which a valid back-EMF signal should be sensed. This counter is used for other purposes later, thanks to PSoC’s dynamic re-configuration capabilities.

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The LPF cut-off frequency has a fixed value at this driver stage and is set by using the dedicated 16-bit counter, Filt_Counter16, in the PSoC configuration. The back-EMF signal is sensed after each phase switch event (starting from the second switch event). If the expected event is well received, the driver exits from free running stage and switches to the synchronous rotation state. Figure 13 illustrates the motor start-up procedure and the switch to back-EMF control mode. For motor start-up the rotor is accelerated in the free-running stage by decreasing the step-by-step coil switching time intervals. These intervals are longer than normal phase switching intervals. During these intervals, the rotor can reach equilibrium position where the shaft torque drops. To get maximum starting torque, the coil switching can be implemented by analyzing the back-EMF signal. The backEMF signal is analyzed during the free running stage. This is after the second windings commutation and the first valid back-EMF signal transition across AGND level finishes the free-running stage and switches to the backEMF sensored stage. The back-EMF signal is analyzed by the comparator bus control register software polling in the loop, unlike the interrupt-driven operation of the sensored state. Using the back-EMF signal analysis during motor start-up allows a reduction in the motor current overload by eliminating redundant free-running stage operation time, which is characterized by larger winding currents. 6. Sensored Rotation Stage Phase switching is initiated by the back-EMF signal, which is delayed at the phase plane by the LPF. This is the primary motor operation stage. The period between winding commutations is measured by a cycle counter with accuracy equal to 1/32 of the PWM period. This value is used to adjust the rotor rotation frequency with the PI regulator. The counter terminal count interrupts are used to generate the timeout to wait for the proper back-EMF signal. If the timeout has expired and no back-EMF received, the control state machine leaves the sensored rotation state and switches to the stop state and increases maximum driver start attempts counter. When this counter reaches the threshold value, the driver switches to the full stop stage and powers on an error LED. The PI regulator calculates the PWM duty cycle to maintain constant rotation speed and is activated every sixth commutation cycle phase. This corresponds to one electric motor period. The speed-setting switches are queried in this loop and, if a new value is read, the new LPF’s clock frequency and new PI regulator reference values are set. The following characteristics should be known in order to design an optimal rotation speed control PI regulator: Loaded and unloaded motor transfer function; Regulation control parameters such as suitable control overshoot and maximum speed-setting time.

Since this project is intended to demonstrate PSoC in control of a sensor-less BLDC motor, the PI regulator is implemented using a simple approach. As mentioned above, the speed control is induced once every motor electrical period. The rotation period is determined by using the measuring counter. The regulator input signal is obtained as the difference between the reference (Tref) and measured (Tmes) periods. The new PWM value is calculated by using the formulae:

ti = T ref − Ti mea

Equation 1

Pi PWM =

( Kint -1) DiPWM + Kint −1
Kint

ti

+ K prg ti

⎡ ⎤ ⎛ 17 ⎞ 15 DiPWM = max ⎢ min ⎜ DiPWM , Pi PWM ⎟ , DiPWM ⎥ −1 −1 ⎝ 16 ⎠ 16 ⎣ ⎦ Equation 2
The proportion term:

K prp = 1/ 32
was selected empirically for the motor used with this example project. The integration term was selected to be:

K int = 1/ 32
This value is the same as the proportional term. The end user can adjust the regulator coefficients according to load specifications. The maximum PWM change speed value is limited in effort to prevent large PWM duty cycle changes over time. The regulator coefficients were chosen to be powers of 2 in the example project. However, the PSoC power is enough (due to a built-in MAC) to run the regulator with other coefficients. The falling edge of the IR2130 DriverFault triggers an interrupt, which turns off all the bridge transistors, exits the current state, enters the stop state, and turns on the LED D1 (see schematics). As described above, the motor makes several attempts to restart from the stop state after a several-second delay. The nominal time to reach speed is checked in the sensored state as well. If motor rotation speed does not reach 7/8 of the nominal value during a predefined timeout, the driver leaves the sensored state and switches to the stop state. The time is measured in motor rotation periods. LED D3 displays that the nominal rotation speed exceeds the timeout.

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Conclusion
This Application Note demonstrates a PSoC sensor-less BLDC motor driver. With minimal hardware and software modifications, this driver can be used to control BLDC.

References
1. “Handbook of small electric motors”, William H.
Yeadon, Alan W. Yeadon, McGraw-Hill, 2001.

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Appendix A. Driver Schematics
DC_BUS D1 1N4148 R1 22R D2 1N4148 R2 22R D3 1N4148 R3 22R C1 10nF 630V R4 100R HO1 R7 47K D4 1N4148 1 R10 22R LO2 Q4 LO1 R13 100R R16 47K R14 100R R17 47K R18 47K R19 0.1 LO1 Q5 D5 1N4148 R11 Q1 HO2 R8 47K 2 22R LO3 R15 100R Q6 HO3 3 D6 1N4148 R5 100R Q2 HO3 R9 47K 3 R12 22R HO2 2 HO1 1 R6 100R Q3

F1 2 ~220V2 FUSE EARLY L1 1 2 ~200V1 2mH C5 10nF_Y1 T1 sf C6 47nF 275V C7 10nF_Y1 4 3 4 C3 1nF + D7 C4 1nF R22 DC_OUT I_SENSE 3 C8 1nF BR805D C9 1nF 220R

Non Inductive
LO2

1

LO3

C2 10nF

DC_BUS R23 DC_OUT 510k + C10 330uF_400V R25 300k DC_BUS_IN R26 5.1k J8 1 2 3 4 5 CON5 DC_BUS_IN I_SENSE C11 10nF 2R R24

DC_BUS R27 U1 C15 100pF 1kV 1 ByPass Drain Source Source Source Source Source 5 8 7 6 3 2 100R

1

T2

D9 3

VDD

~200V1 EARLY ~220V2

2

4 C12 1000uF 25V C14 10nF Q7 BC547 R20 20R R28 100 D10 12V

C13 0.33uF

1 2 3

VDD

4 C16 0.1

EN

TNY255

The Driver Power Schematic

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U1 HO1_IN HO2_IN HO3_IN LO1_IN LO2_IN LO3_IN 5 6 7 2 3 4 LIN1 LIN2 LIN3 HIN1 HIN2 HIN3 VB1 HO1 VS1 VB2 HO2 VS2 VB3 HO3 VS3 LO1 13 1 VS0 VCC LO2 LO3 FAULT 28 27 26 24 23 22 20 19 18 C5 16 15 14 8 LO1 LO2 LO3 FAULT D5 UF4007 LO3 1 2 0.1 D4 UF4007 HO3 HO2 C3 0.1 + C4 10uF 25V HO1 C1 0.1 C2 10uF 25V VDD HO1 1 R2 47R 1 D2 UF4007 2 + C6 10uF 25V HO2 2 1 2 1 2 J1 CON2

D1 UF4007

R1 10R

+

J2 CON2

R3

47R

R15 12k

11 R14 5.1k 9 10

CAITRIP CAO

HO3 3

1 2

J3 CON2

D3 UF4007 3 R4 47R LO1 1 2

J4 CON2

I_SENSE

VDD

D6 UF4007

LO2

1 2

J5 CON2

J6 CON2

IR2130 C7 100uF 25V C8 0.1

+

DC_BUS_IN I_SENSE R5 1.5M 1 R8 300k 2 R9 300k R6 1.5M 3 R10 300k HO3_IN HO2_IN HO1_IN LO3_IN LO2_IN LO1_IN FAULT 1 3 5 7 9 11 13 CON14A R7 1.5M J7 2 4 6 8 10 12 14 VDD DC_BUS_IN IN3 IN2 IN1

IN1 C9 680pF R11 27k C10 680pF R12 27k

IN2 C11 680pF R13 27k

IN3

IGBT Driver Schematic

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1 J1 1 2 3 4 CON4 R9 750R R7 750R 2 1 R8 750R 2 1 2 U6 PC817 U5 PC817 U7 PC817 3 4 3 4 3 4 VCC U3 R4 IN3 IN2 C1 0.47 R5 1.1k SW3 SW1 IndSpeedFault LO2_IN 1 2 3 4 5 6 7 8 9 FAULT LO3_IN IndStartFault LO1_IN 10 11 12 13 14 P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss CY8C27443 VCC P0[6] P0[4] P0[2] P0[0] P2[6] P2[4] P2[2] P2[0] XRES P1[6] P1[4] P1[2] P1[0] 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C2 0.1 IN1 SW2 DC_BUS_IN HO3_IN IndStartFault SW DIP-3 SW1 SW2 SW3

SW1

Remote speed select

4.3k

IndSpeedFault

HO2_IN HO1_IN

D1 LED I/U_FAULT R1 510R

D2 LED START_FAULT R2 510R

D3 LED SPEED_FAULT R3 510R

J7 HO3_IN HO2_IN HO1_IN LO3_IN LO2_IN LO1_IN FAULT 1 3 5 7 9 11 13 CON14A 2 4 6 8 10 12 14 VDD

VCC DC_BUS_IN R6 VDD 75R 0.5W + C6 22uF 25V 1

U4 VIN VO

IN3 IN2 IN1

C2 0.1

78L05

CPU Module Schematic

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Appendix B. Referenced Tables
Table 2. IGBT Bridge Control Table
# Phase 0. 1. 2. 3. 4. 5. 0 0 0 1 1 0 Up A 1 0 0 0 0 1 Up B 0 1 1 0 0 0 Up C 1 1 0 0 0 0 Down A 0 0 1 1 0 0 Down B 0 0 0 0 1 1 Down C

Table 3. Speed-Setting Switches and Nominal Speeds
Setting b000 b001 b010 b011 b100 b101 b110 b111 Speed RPM Stop 2200 2400 2600 2800 3000 3200 3400 Electrical Frequency Hz 0 73.3 80.0 86.6 93.3 100.0 106.6 113.3 Filter Frequency Hz 0 220 240 260 280 300 320 340 Period in Counter Units* 0 2182 2000 1846 1714 1600 1500 1412

* Counter unit = PWM_period*32*6 The following items were selected in this driver: Freq_mechanical = RPM / 60, where RPM – revolutions per minute Freq_electrical = Freq_mechanical*p Freq_interrupt = Freq_electrical*6 (rising and falling edges) RisingEdge_interrupt_Freq = Freq_electrical*3 p = motor pairs poles number

Table 4. Phase Commutation Duration During Motor Free-Running Starting
Cycle Duration in PWM Period Units (200uS) 125 0 113 1 100 2 88 3 75 4 5 and More 63

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Appendix C. Firmware Flowcharts
Figure 4. Driver Initialization and Determination of Maximum PWM Value
Device initialization

Loop

display stall event StallCounter+1 StallFlags==1 Yes StallCounterOver No StallFlags = 0

No

Switch read

Yes Stop

Wait 3s

No

Speed set Yes Charging the IR 2130 bootstrap capacitor

Set minimal Dutycycle PWM Set frequency PWM 1.5kHz

Turn on the high switch of phase A and low switch of phase B

Current is more maximum Yes Reduce the PWM duty cycle on 25%

No

Increase the PWM value on one

Get to memory max Dutycycle PWM Set frequency PWM 5kHz

1

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Figure 5. Motor Operational
1

Set FreeRunCycles Set FreeRunTimeOut

Commutation of next phase

FreeRunTimeOut Over ? Yes Yes

No

Zerro Cross detect

No FreeRunCycles Over ? No

Yes FreeRunBreak Yes SET MAX_PULSE_TIME No

Yes

MAX_PULSE_TIME Over ?

No Yes

Fault Driver ? No No

StallFlags =1

Zerro Cross Enable ? Loop Yes Routing the PWM signals for next stage

Speed calculate

Yes

Speed fault ?

Yes

Speed control time ?

No

PI control time ? Yes Calculate and Set new DutyCycle

No

Switch read and set new speed

No

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Appendix D. Scope Images
Figure 6. Back-EMF Signal (a) and Filtered Signal (b)

Back EMF Voltage

(a)

Delay 30°

(b)

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Figure 7. Motor Phase Signals

Figure 8. Filter Output Signals

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Figure 9. Motor Start Procedure for Varied Loads

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Figure 10. Scope Image for Initial Duty Cycle Determination (Driver Preparation)

Figure 11. Scope Images for the Compensation Voltage for Two Different PWM Values

(a)

(b)

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Figure 12. Unfiltered Back-EMF Signal (a) and Signal After LPF (b) When Driver Switches from Free-Running Stage to Sensored Stage
First Back EMF commutate for CH1

(a)

(b)

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Appendix E. Driver Photograph
Figure 13. Assembled Driver Photograph

Note Driver components are mounted on three separate PCBs to simplify future upgrades and modifications.

Figure 14. Driver Photograph with 75W Motor

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About the Author
Name: Title: Background: Andrey Magarita Sr. Application Engineer Andrey graduated from National University “Lvivska Polytechnika” (Lviv, Ukraine) in 1989 and presently works as a Senior Application Engineer at “Zuvs,” a private company. He has more than 15 years experience in embedded systems design. You can contact him at makar@ltf.lviv.net

Contact:

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