An Efficient OFDM Transceiver Design suitable to IEEE 802.11a WLAN standard

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An Efficient OFDM Transceiver Design suitable to IEEE 802.11a WLAN standard Powered By Docstoc
					                                                           (IJCSIS) International Journal of Computer Science and Information Security,
                                                           Vol. 8, No. 2, May 2010

   An Efficient OFDM Transceiver Design suitable to
             IEEE 802.11a WLAN standard

                           T.Suresh                                                            Dr.K.L.Shunmuganathan
      Research Scholar, R.M.K Engineering College                                     Professor & Head, Department of CSE
               Anna University, Chennai                                              R.M.K Engineering College, Kavaraipettai
                    TamilNadu, India                                                            TamilNadu, India

Abstract—In today’s advanced Communication technology one of                 tool. Therefore, to support high data rates and computational
the multicarrier modulations like Orthogonal Frequency Division              intensive operations, the underlying hardware platform must
Multiplexing (OFDM) has become broadened, mostly in the field                have significant processing capabilities. FPGAs, here,
of wireless and wired communications such as digital audio/video             promotes itself as a remarkable solution for developing
broadcast (DAB/DVB), wireless LAN (802.11a and HiperLAN2),
                                                                             wireless LAN (802.11a and HiperLAN2), and broadband
and broadband wireless (802.16). In this paper we discuss an
efficient design technique of OFDM transceiver according to the              wireless systems (802.16) with their computational
IEEE 802.11a WLAN standard. The various blocks of OFDM                       capabilities, flexibility and faster design cycle[2]. Therefore,
transceiver is simulated using ModelSimSE v6.5 and                           to support high data rates and computational intensive
implemented in FPGA Xilinx Spartan-3E Platform. Efficient                    operations, the underlying hardware platform must have
techniques like pipelining and strength reduction techniques are             significant processing capabilities. The aim of this paper is to
utilized to improve the performance of the system. This                      implement the reconfigurable architecture for the digital
implementation results show that there is a remarkable savings in            baseband part of an OFDM transceiver that conforms the
consumed power and silicon area. Moreover, the design has                    802.11a standard, by including 16 QAM modulator, FFT (Fast
encouraged the reduction in hardware resources by utilizing the
                                                                             Fourier Transform) and IFFT (Inverse Fast Fourier
efficient reconfigurable modules.
                                                                             Transform), serial to parallel and parallel to serial converter
   Keywords-FPGA; VHDL; OFDM; FFT; IFFT; IEEE 802.11a                        using hardware programming language VHDL (VHSIC
                                                                             Hardware Description Language). Moreover, this design is
                      I.     INTRODUCTION                                    area and power efficient by making the use of strength
    Wireless communications are evolving towards the Multi-                  reduction transformation technique that will reduce the
standard systems and other communication technologies, are                   number of multipliers used to perform the computation of
utilizing the widely adopted Orthogonal Frequency Division                   FFT/IFFT processing.
Multiplexing (OFDM) technique, among the standards like
IEEE 802.11a&g for Wireless Local Area Networks (WLANs),                         The paper is organized as follows: Section II describes the
Wi-Fi, and the growing IEEE802.16 for Metropolitan Access,                   OFDM point to point system. Section III represents the
Worldwide       Interoperability   for    Microwave       Access             simulated methods of OFDM blocks and their results. Section
(WIMAX)[1]. The fast growth of these standards has helped                    IV briefs about the pipelining process. Section V explains the
the way for OFDM to be among the widely adopted standards                    FFT/IFFT implementation by using Strength Reduction
and to be the fundamental methods for the improvements of the                technique. Section VI shows the implementation results and
next generation telecommunication networks. In broadband                     resource reductions. Section VII concludes the paper.
wireless communication, designers need to meet a number of
critical requirements, such as processing speed, flexibility, and
fast time to market. These requirements influence the designers
in selecting both the targeted hardware platform and the design
     Serial data
          in        Convolution           Modulation           Serial to                               Parallel to           Cyclic            C
                      encoder             (16 QAM)              parallel                IFFT             serial               prefix           h
                                                               converter                               converter            insertion          a
     Serial data                                                                                        Serial to              Cyclic
         out       Convolution          Demodulation           Parallel to                                                                     e
                                         (16 QAM)                serial                 FFT              parallel              prefix
                                                                                                        converter             removal

                              Figure 1. OFDM point to point System

                                                                                                        ISSN 1947-5500
                                                                    (IJCSIS) International Journal of Computer Science and Information Security,
                                                                    Vol. 8, No. 2, May 2010

                   II.        OFDM POINT TO POINT SYSTEM
    The simplest form of a point-to-point OFDM system could                                                                                   A=a+b
be considered as transmitter building blocks into the receiver
side. It represents the basic building blocks that are used in
both the transmission and reception sides as shown in Fig. 1.
                                                                                          b                                                 B=(a-b)WN
A. Convolution Encoder
    Convolution encoder is used to create redundancy for the                                        Figure 2. 2 Point Butterfly structure
purpose of secured transmission of data. This helps the system
to recover from bit errors during the decoding process. The
802.11a standard recommends to producing two output bits for
each input. To achieve higher data rates, some of the redundant                     D. Strength Reduction Transformation
bits are removed after the encoding process is completed.                              Fig. 2 shows the 2 point Butterfly structure where
B. QAM Modulation                                                                   multiplication is performed with the twiddle factor after
                                                                                    subtraction. Consider the problem of computing the product of
    QAM (Quadrature Amplitude Modulation) is widely used                            two complex numbers R and W
in many digital radio and data communications. It also
considers the mixture of both amplitude and phase modulation.
In this paper we used 16 bit QAM and is used to refer the                                             X = RW = (Rr+jRi)(Wr+jWi)
number of points in constellation mapping. This is because of                                           =(RrWr-RiWi)+j(RrWi+RiWr)                       (4)
QAM achieves a greater distance between adjacent points in
the I/Q plane by distributing the points more evenly. By this                           The direct architectural implementation requires a total of
way the points in the constellation are distinct and due to this,                   four multiplications and two real additions to compute the
data errors are reduced.                                                            complex product as shown in (4). However, by applying the
                                                                                    Strength Reduction transformation we can reformulate (4) as
    The key kernel in an OFDM transceiver is the IFFT/FFT
processor. In WLAN standards it works with 64 carriers at a                                        Xr=(Rr-Ri)Wi+Rr(Wr-Wi)                               (5)
sampling rate of 20 MHz, so a 64-point IFFT/FFT processor is                                       Xi=(Rr-Ri)Wi+Ri(Wr+Wi)                               (6)
required. The Fast Fourier Transform (FFT) and Inverse Fast
Fourier Transform (IFFT) are derived from the main function                             It is clearly shown as given in (5) and (6), by using the
which is called Discrete Fourier Transform (DFT). The idea of                       Strength Reduction transformation the total number of real
using FFT/IFFT instead of DFT is that the computation can be                        multiplications is reduced to only three. This however is at the
made faster where this is the main criteria for implementation.                     expense of having three additional adders. So in this paper the
In direct computation of DFT the computation for N-point DFT                        above discussed strength reduction transformation technique is
will be calculated one by one for each point. But for FFT/IFFT,                     used in the implementation of OFDM transceiver while
the computation is done simultaneously and this method helps                        multiplying the transmitted/received signal by twiddle factor.
to save lot of time, and so this is similar to pipelining
    The derivation starts from the fundamental DFT equation
for an N point FFT. The equation of IFFT is given as shown in
(1) and the equation of FFT is given as shown in (2)

               #              #
     {J{                  ("
                                  {{                   .            (1)

     {J{                 ("
                              {{                       .            (2)

where the quantity                  (called Twiddle Factor) is defined as
                              D$π EÈ4
                        ‡                                              (3)
This factor is calculated and put in a table in order to make the
computation easier and can run simultaneously. The Twiddle
Factor table is depending on the number of points used. During
the computation of FFT, this factor does not need to be                                                   Figure 3. Cyclic Prefix
recalculated since it can refer to the Twiddle factor table, and
thus it saves time.

                                                                                                                 ISSN 1947-5500
                                                              (IJCSIS) International Journal of Computer Science and Information Security,
                                                              Vol. 8, No. 2, May 2010

 E. Cyclic Prefix                                                            summed to give the transmitted signal. The baseband signals
     One of the most important properties of OFDM                            are sampled and passed through the OFDM receiver in FPGA
 transmission is its robustness against multi path delay. This is            and a forward FFT is used to convert back to the frequency
 especially important if the signal’s sub-carriers are to retain             domain. This returns of parallel streams, is converted to a
 their orthogonality through the transmission process. The                   binary stream using an 16-QAM demodulator. These are re-
 addition of a guard period between transmitted symbols can be               combined into a serial stream, is an estimate of the original
 used to accomplish this. The guard period allows time for                   binary stream at the transmitter. The cyclic prefix is used in
 multipath signals from the previous symbol to dissipate before              OFDM Transceiver for the purpose of eliminating the ISI.
 the information from the current symbol gets recorded. The                  This overall simulation part is done by ModelSim SE v6.5
 most effective guard period is a cyclic prefix, which is                    software with VHDL language and simulated results are
 appended at the front of every OFDM symbol. The cyclic                      shown in Fig. 5.
 prefix is a copy of the last part of the OFDM symbol, and is of
 equal or greater length than the maximum delay spread of the
 channel as shown in Fig. 3.
    In this paper the simulated blocks of OFDM transceiver are
 explained and the results were analyzed. The blocks those are
 simulated using ModelSim SE v6.5 are given in Fig. 4. The
 blocks consist of OFDM transmitter which includes 16 QAM
 modulator and IFFT and OFDM receiver which includes FFT
 and 16 QAM demodulator.
     In the initial stage the serial binary data value can be
 applied to the transmitter block through convolution encoder
 for the purpose of secured data transmission and modulated by
 the 16-QAM because of its advantageous compared to other
 modulations like BPSK, QPSK. An OFDM carrier signal is
 the sum of a number of orthogonal sub-carriers, with baseband
 data modulation (QAM) and it is demultiplexed into parallel
 streams, and each one mapped to a complex symbol stream
 using 16-QAM modulation.

             IFFT        IFFT
             Real         img
              out          out

                                 I              Rectangular
           Rectangular           F     F          QAM             QAM
QAM          QAM                               demodulation
                                 F     F                          OUT
 IN        modulation            T     T

            OFDM Transmitter               OFDM Receiver
                                                                                                         Figure 5. Simulated Results
                           OFDM Transceiver
                                                                                                 IV.    PIPELINE PROCESS
                                                                                 Each block in this architecture is designed and tested
          CLK     RESET                      FFT    FFT
                                             Real   img                      separately, and later those blocks are assembled and extra
                                              in     in                      modules are added to compose the complete system. The
            Figure 4. Simulated Blocks of OFDM Transceiver
                                                                             design makes use of pipelining process and this is mainly
                                                                             achieved through duplicating the memory elements like
      An inverse FFT is computed on each set of symbols,                     registers or RAMs in simulation function processing and it will
 delivering a set of complex symbols. The real and imaginary                 buffer the incoming stream of bits while the previous stream is
 components (I/Q) are used to modulate the cosine and sine                   being processed. The design environment is completely based
 waves at the carrier frequency respectively, these signals are              on the Xilinx Integrated Software Environment (ISE) and

                                                                                                         ISSN 1947-5500
                                                           (IJCSIS) International Journal of Computer Science and Information Security,
                                                           Vol. 8, No. 2, May 2010

                         1b                            I
        Bits              2b          ROM(4*16)
                                         16 QAM
                                                                                  +          +               -            -
                              4bits     ROM(16*16)
                                           64 QAM      Q
                               6 bits                                                                            -                     -          +

                       Figure 6. Mapper Architecture
                                                                                                                     Х             Х              Х
implemented in the Xilinx Spartan-3E FPGA. As a first step,
the data stream is encoded using a convolution encoder, which
uses a number of delay elements by representing the D-type
Flip-flop for duplicating purpose. The final purpose of the                                                                    +              +
coding stage is to provide the receiver with the capability to
detect and correct errors through redundancy. By using this
design, the need of more number of multiplexers is avoided and
the abundant memory inside the FPGA is used. To perform the                           Figure 7. PE and its resources of FFT/IFFT block
Pipeline process, the bits are translated or mapped into two
components the In-phase and the Quadrature of (I/Q)                       task of designing the digital baseband part of an OFDM
components, those are mapped as shown in Fig. 6.                          transceiver that conforms to the IEEE 802.11a standard.
    The representation of these I and Q values is based on a              However, the implemented design supports only the data rates
fixed point representation. Depending on the data rate                    6, 12 and 24 Mbps in the standards.
selected, the OFDM sub-carriers are modulated using 16-                    Table I shows the resources used for implementing the blocks
QAM. This capability came from the pipelining provided by                 of OFDM system and also shows the percentage of device
the previous and the next stages, where each generated I/Q                utilization by this design from the available resources on
pair is fed to the IFFT processor. The generated real and
                                                                          FPGA and the memory elements of estimated values. From
imaginary Pairs are forwarded to the Cyclic Prefix block. The
                                                                          this table we understood that the number of multiplexers is
last samples of the generated OFDM symbol are copied into
the beginning to form the cyclic prefix. In the 802.11a                   reduced by using the efficient pipelining and strength
standard, the last samples of the Pipelining IFFT output are              reduction transformation methods, and the total number of
replicated at the beginning to form a complete samples of                 resources is also reduced remarkably.
OFDM symbol. These samples are considered as the
                                                                                      TABLE I.        COMPLETE SYSTEM RESOURCES
maximum delay in the multipath environment.
                 V.      FFT/IFFT IMPLEMENTATION                                   Device Utilization Summary(Estimated Value)

    FFT/IFFT computation is performed using strength                           Logic Utilization      Used           Available             Utilization
reduction transformation technique in this paper. Fig. 7 shows                Number of Slices         1521              3584                 42%
the Processing Element(PE) and its resources used to perform
FFT/IFFT computation. This implementation is compared                         Number of Slice          1682              7168                 23%
with the direct computation of FFT/IFFT. It is demonstrated
that there are four multipliers used in the direct computation of             Number of 4 input        2549              7168                 35%
FFT/IFFT, but the number of multipliers used in the                           LUTs
implementation of strength reduction transformation technique                 Number of                 66               141                  46%
is reduce to only three.                                                      bonded IOBs

                 VI.      IMPLEMENTATION RESULTS                              Number of                 12               16                   75%
    The work presented in this paper is to implement the
capability of an OFDM transceiver standard in a pure VHDL                     Number of                 1                 8                   12%
code implementation, and to encourage the reduction in                        GCLKs
hardware resources by utilizing the efficient techniques and
suitable reconfigurable platform. The approach of divide and
conquer is used to design and test each entity alone and helps                                     VII. CONCLUSION
to make the complete system. The work has accomplished the                   Orthogonal Frequency Division Multiplexing is an
                                                                          important technology because so many developing

                                                                                                        ISSN 1947-5500
                                                                    (IJCSIS) International Journal of Computer Science and Information Security,
                                                                    Vol. 8, No. 2, May 2010

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       2001.                                                                                                 T.Suresh received his BE and ME degrees in
[6]    Zhi Yong Li, a thesis of “OFDM Transceiver Design with FPGA and                                       Electronics and Communication Engineering
       demo on de2-70 board”, July 2008.                                                                     from Madras University and Alagappa
[7]    IEEE Std 802.11a-1999, "Wireless LAN Medium Access Control                                            Chettiar College of Engineering and
       (MAC) and Physical Layer (PHY) specifications: high speed physical                                    Technology in 1991 and 1996, respectively,
       layer in the 5 GHZ band", July 1999.
                                                                                                             and pursuing Ph.D from Anna University,
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                                                                                                             Chennai ,India. Currently, he is an Assistant
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                                                                                                             Networks, Multiagent Systems, DBMS.

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