Data Flow Structural Modeling of Combinational Logic by qws18475

VIEWS: 37 PAGES: 72

									                                 ECE 545
                                 Lecture 2

               Data Flow & Structural
                    Modeling of
                Combinational Logic


ECE 545 – Introduction to VHDL               George Mason University
 Resources
    • Sundar Rajan, Essential VHDL: RTL Synthesis
      Done Right
       Chapter 1, VHDL Fundamentals
       Chapter 2, Getting Your First Design Done
       Chapter 3, Gates, Decoders and Encoders
       Chapter 9, Design Partitioning
         (Design Hierarchy, Hierarchy in VHDL)
    • Peter J. Ashenden, The Designer’s Guide to VHDL
       Chapter 1, Fundamental Concepts


ECE 545 – Introduction to VHDL                      2
Register Transfer Logic (RTL)
Design Description
                                 Today’s Topic




                        Combinational
                           Logic
                                                 Combinational   …
                                                   Logic




                          Registers



ECE 545 – Introduction to VHDL                                   3
VHDL Design Styles

                                 VHDL Design
                                    Styles



            dataflow                structural        behavioral

         Concurrent              Components and      Sequential statements
         statements              interconnects    • Registers
                                                  • State machines
                                                  • Test benches


                                 Subset most suitable for synthesis

ECE 545 – Introduction to VHDL                                               4
                     VHDL Fundamentals




ECE 545 – Introduction to VHDL           5
 Naming and Labeling (1)

 • VHDL is not case sensitive
       Example:
            Names or labels
              databus
              Databus
              DataBus
              DATABUS
            are all equivalent




ECE 545 – Introduction to VHDL   6
 Naming and Labeling (2)
 General rules of thumb (according to VHDL-87)

 1.     All names should start with an alphabet character (a-z
        or A-Z)
 2.     Use only alphabet characters (a-z or A-Z) digits (0-9)
        and underscore (_)
 3.     Do not use any punctuation or reserved characters
        within a name (!, ?, ., &, +, -, etc.)
 4.     Do not use two or more consecutive underscore
        characters (__) within a name (e.g., Sel__A is invalid)
 5.     All names and labels in a given entity and architecture
        must be unique

ECE 545 – Introduction to VHDL                                    7
 Free Format
 • VHDL is a “free format” language
     No formatting conventions, such as spacing or
   indentation imposed by VHDL compilers. Space
   and carriage return treated the same way.
       Example:
                 if (a=b) then
            or
                 if (a=b)        then
            or
                 if (a =
                 b) then
            are all equivalent


ECE 545 – Introduction to VHDL                       8
 Readability standards


        ESA VHDL Modelling Guidelines
                 published by
 European Space Research and Technology Center
              in September 1994

                  available at the course web page




ECE 545 – Introduction to VHDL                       9
    Readability standards
Selected issues covered by ESA Guidelines:

•   Consistent Writing Style
•   Consistent Naming Conventions
•   Consistent Indentation
•   Consistent Commenting Style
•   Recommended File Headers
•   File naming and contents
•   Number of statements/declarations per line
•   Ordering of port and signal declarations
•   Constructs to avoid

ECE 545 – Introduction to VHDL                   10
 Comments
 • Comments in VHDL are indicated with
   a “double dash”, i.e., “--”
         Comment indicator can be placed anywhere in the
          line
         Any text that follows in the same line is treated as
         a comment
         Carriage return terminates a comment
         No method for commenting a block extending over
          a couple of lines
 Examples:
 -- main subcircuit
 Data_in <= Data_bus; -- reading data from the input FIFO

ECE 545 – Introduction to VHDL                                   11
 Comments

 • Explain Function of Module to Other
   Designers
 • Explanatory, Not Just Restatement of Code
 • Locate Close to Code Described
       • Put near executable code, not just in a header




ECE 545 – Introduction to VHDL                            12
             Modeling wires and buses




ECE 545 – Introduction to VHDL          13
 Signals

 signal A : std_logic;

                                      A
                                 1   wire

 signal B : std_logic_vector(7 downto 0);

                                      B
                                 8   bus


ECE 545 – Introduction to VHDL              14
Standard Logic Vectors
signal A: STD_LOGIC;
signal B: STD_LOGIC_VECTOR(3 downto 0);
signal C: STD_LOGIC_VECTOR(3 downto 0);
signal D: STD_LOGIC_VECTOR(7 downto 0);
signal E: STD_LOGIC_VECTOR(15 downto 0);
signal F: STD_LOGIC_VECTOR(8 downto 0);
                        ……….
A <= „1‟;
B <= ”0000”;      -- Binary base assumed by default
C <= B”0000”;      -- Binary base explicitly specified
D <= ”0110_0111”; -- You can use „_‟ to increase readability
E <= X”AF67”;     -- Hexadecimal base
F <= O”723”;       -- Octal base
ECE 545 – Introduction to VHDL                                 15
                     Describing
               Combinational Logic
                       Using
               Dataflow Design Style


ECE 545 – Introduction to VHDL         16
                                  Data-flow VHDL

                                 Major instructions

                          Concurrent statements
    •     concurrent signal assignment ()
    •     conditional concurrent signal assignment
                                     (when-else)
    •     selected concurrent signal assignment
                                     (with-select-when)
    •     generate scheme for equations
                                     (for-generate)


ECE 545 – Introduction to VHDL                            17
                                  Data-flow VHDL

                                 Major instructions

                          Concurrent statements
    •     concurrent signal assignment       ()
    •     conditional concurrent signal assignment
                                     (when-else)
    •     selected concurrent signal assignment
                                     (with-select-when)
    •     generate scheme for equations
                                     (for-generate)


ECE 545 – Introduction to VHDL                            18
                          Data-flow VHDL: Example
                                                                                    xi yi
                                                                               ci           00     01      11       10

                                                                                     0              1               1
                           ci xi yi         c



                                                i   +   1
                                                            si
                                                                                     1      1              1
                           0   0   0                0       0
                           0   0   1                0       1
                                                                                             s i = x i  y i  c i
                           0   1   0                0       1
                           0   1   1                1       0                       xi yi
                           1   0   0                0       1
                                                                               ci           00     01      11       10
                           1   0   1                1       0
                           1   1   0                1       0                        0                     1
                           1   1   1                1       1
                                                                                     1              1      1        1

                               (a) Truth table
                                                                                    ci + 1 = xi yi + xici + yici


                                                                                    (b) Karnaugh maps

                                       xi

                                       yi                                                                  si

                                       ci




                                                                                                           ci + 1




                                                                 (c) Circuit
ECE 545 – Introduction to VHDL                                                                                           19
                       Data-flow VHDL: Example

  LIBRARY ieee ;
  USE ieee.std_logic_1164.all ;

  ENTITY fulladd IS
        PORT (x, y, Cin           : IN     STD_LOGIC ;
                s, Cout           : OUT    STD_LOGIC ) ;
  END fulladd ;

  ARCHITECTURE LogicFunc OF fulladd IS
  BEGIN
       s <= x XOR y XOR Cin ;
       Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
  END LogicFunc ;

ECE 545 – Introduction to VHDL                             20
Logic Operators

 • Logic operators
             and        or       nand   nor   xor    not    xnor



 • Logic operators precedence
           Highest
                                             not
                           and     or   nand   nor    xor    xnor
            Lowest




ECE 545 – Introduction to VHDL                                      21
No Implied Precedence
                             Wanted: Y = ab + cd
 Incorrect
 Y <= a and b or c and d
 equivalent to
 Y <= ((a and b) or c) and d
 equivalent to
 Y = (ab + c)d

 Correct
 Y <= (a and b) or (c and d)

ECE 545 – Introduction to VHDL                     22
Concatenation

       signal A: STD_LOGIC_VECTOR(3 downto 0);
       signal B: STD_LOGIC_VECTOR(3 downto 0);
       signal C, D, E: STD_LOGIC_VECTOR(7 downto 0);

       A <= ”0000”;
       B <= ”1111”;
       C <= A & B;               -- C = ”00001111”

       D <= ‘0’ & ”0001111”;     -- D <= ”00001111”

       E <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
            ‘1’ & ‘1’;
                               -- E <= ”00001111”


ECE 545 – Introduction to VHDL                         23
Rotations in VHDL

                                         A<<<1

                                 A(3) A(2) A(1) A(0)




                                 A(2) A(1) A(0) A(3)


                       A_rotL <= A(2 downto 0) & A(3)

ECE 545 – Introduction to VHDL                          24
Arithmetic Functions in VHDL (1)
To use basic arithmetic operations involving
std_logic_vectors you need to include the
following library packages:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;




ECE 545 – Introduction to VHDL                 25
Arithmetic Functions in VHDL (2)
You can use standard +, - operators
to perform addition and subtraction:

      signal A :                 STD_LOGIC_VECTOR(3 downto 0);
      signal B :                 STD_LOGIC_VECTOR(3 downto 0);
      signal C :                 STD_LOGIC_VECTOR(3 downto 0);
         ……
      C <= A + B;




ECE 545 – Introduction to VHDL                                   26
                                  Data-flow VHDL

                                 Major instructions

                          Concurrent statements
    •     concurrent signal assignment ()
    •     conditional concurrent signal assignment
                                     (when-else)
    •     selected concurrent signal assignment
                                     (with-select-when)
    •     generate scheme for equations
                                     (for-generate)


ECE 545 – Introduction to VHDL                            27
Data Flow Instructions (1)

       When - Else
            target_signal <= value1 when condition1 else
                             value2 when condition2 else
                               . . .
                             valueN-1 when conditionN-1 else
                             valueN;


 Value N
                            .…    …
Value N-1                                                                        Target Signal

                                 Value 2
                                                         Value 1
            Condition N-1

                                           Condition 2
                                                                   Condition 1

ECE 545 – Introduction to VHDL                                                           28
Operators

 • Relational operators
              =          /=      <    <=    >      >=



 • Logic and relational operators precedence
             Highest                       not
                           =     /=     <     <=    >     >=
             Lowest        and   or   nand   nor   xor   xnor




ECE 545 – Introduction to VHDL                                  29
Priority of logic and relational operators

                             compare a = bc
 Incorrect
   … when a = b and c else …
 equivalent to
   … when (a = b) and c else …

 Correct
  … when a = (b and c) else …



ECE 545 – Introduction to VHDL                30
                                  Data-flow VHDL

                                 Major instructions

                          Concurrent statements
    •     concurrent signal assignment ()
    •     conditional concurrent signal assignment
                                     (when-else)
    •     selected concurrent signal assignment
                                     (with-select-when)
    •     generate scheme for equations
                                     (for-generate)


ECE 545 – Introduction to VHDL                            31
Data Flow Instructions (2)
        With - Select
        with choice_expression select
           target_signal <= expression1 when choices1,
                            expression2 when choices2,
                                . . .
                            expressionN when choicesN;



                     expression1   choices1
                    expression2    choices2
                                                         target_signal


                    expressionN    choicesN

                                              choice expression

ECE 545 – Introduction to VHDL                                           32
                                 MLU Example




ECE 545 – Introduction to VHDL                 33
    MLU: Block Diagram

                                  MUX_0
                        A1
A


                                                  IN 0
                                 MUX_1
                NEG_A                             IN 1
                                                                        Y1
                                 MUX_2
                                                  IN 2

                                                  IN 3     O U T PU T                Y
                                                  S E L1

                                                  S E L0

                      B1                                                     NEG_Y
B                                                   MUX_4_1

                                 MUX_3


                NEG_B
                                          L1 L0




ECE 545 – Introduction to VHDL                                                           34
 MLU: Entity Declaration
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;

 entity MLU is
     port(
           NEG_A : in STD_LOGIC;
           NEG_B : in STD_LOGIC;
           NEG_Y : in STD_LOGIC;
           A : in STD_LOGIC;
           B : in STD_LOGIC;
           L1 : in STD_LOGIC;
           L0 : in STD_LOGIC;
           Y : out STD_LOGIC
        );
 end MLU;


ECE 545 – Introduction to VHDL     35
 MLU: Architecture Declarative Section
 architecture MLU_DATAFLOW of MLU is

 signal A1:STD_LOGIC;
 signal B1:STD_LOGIC;
 signal Y1:STD_LOGIC;
 signal MUX_0:STD_LOGIC;
 signal MUX_1:STD_LOGIC;
 signal MUX_2:STD_LOGIC;
 signal MUX_3:STD_LOGIC;
 signal L: STD_LOGIC_VECTOR(1 downto 0);




ECE 545 – Introduction to VHDL             36
 MLU - Architecture Body
begin
   A1<= not A when (NEG_A='1') else
         A;
   B1<= not B when (NEG_B='1') else
         B;
   Y <= not Y1 when (NEG_Y='1') else
         Y1;

    MUX_0 <= A1 and B1;
    MUX_1 <= A1 or B1;
    MUX_2 <= A1 xor B1;
    MUX_3 <= A1 xnor B1;

    L<=L1 & L0;

    with (L) select
       Y1 <= MUX_0 when "00",
               MUX_1 when "01",
               MUX_2 when "10",
               MUX_3 when others;

end MLU_DATAFLOW;
ECE 545 – Introduction to VHDL         37
                                  Data-flow VHDL

                                 Major instructions

                          Concurrent statements
    •     concurrent signal assignment ()
    •     conditional concurrent signal assignment
                                     (when-else)
    •     selected concurrent signal assignment
                                     (with-select-when)
    •     generate scheme for equations
                                     (for-generate)


ECE 545 – Introduction to VHDL                            38
                            PARITY Example




ECE 545 – Introduction to VHDL               39
PARITY: Block Diagram




ECE 545 – Introduction to VHDL   40
For Generate Statement

    For Generate

       name: for parameter_specification generate
                 [Declaration Statements]
                 begin
                  {Concurrent Statements}
                 end generate name;




ECE 545 – Introduction to VHDL                      41
 PARITY: Entity Declaration
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;

 entity PARITY is
     port(
           Parity_in : in STD_LOGIC_VECTOR(7 downto 0);
           Parity_out : out STD_LOGIC
        );
 end PARITY;




ECE 545 – Introduction to VHDL                            42
PARITY: Block Diagram

                 Xor_out(1)
                              Xor_out(2)
                                           Xor_out(3)
                                                        Xor_out(4)
                                                                     Xor_out(5) Xor_out(6)
                                                                                          Xor_out(7)




ECE 545 – Introduction to VHDL                                                                         43
 PARITY: Architecture
 architecture PARITY_DATAFLOW of PARITY is

 signal Xor_out: std_logic_vector (7 downto 1);

 begin

     Xor_out(1) <= Parity_in(0) xor Parity_in(1);

     G2: for i in 1 to 6 generate
          Xor_out(i+1) <= Xor_out(i) xor Parity_in(i+1);
     end generate G2;

     Parity_out <= Xor_out(7);

 end PARITY_DATAFLOW;


ECE 545 – Introduction to VHDL                             44
                  Verifying the operation
                    of the circuit using
                        testbenches



ECE 545 – Introduction to VHDL              45
Testbench Block Diagram


                                 Testbench

              Processes
                                             Design Under
             Generating                       Test (DUT)
                Stimuli



                                                    Observed Outputs




ECE 545 – Introduction to VHDL                                     46
Testbench Defined
 • Testbench applies stimuli (drives the inputs) to
   the Design Under Test (DUT) and (optionally)
   verifies expected outputs.
 • The results can be viewed in a waveform window
   or written to a file.
 • Since Testbench is written in VHDL, it is not
   restricted to a single simulation tool (portability).
 • The same Testbench can be easily adapted to
   test different implementations (i.e. different
   architectures) of the same design.

ECE 545 – Introduction to VHDL                             47
Testbench Anatomy
Entity TB is
                --TB entity has no ports
End TB;

Architecture arch_TB of TB is

               --Local signals and constants

  component TestComp --All Design Under Test component declarations
            port ( );
  end component;
-----------------------------------------------------
  for DUT:TestComp use entity work.TestComp(archName)--Specify entity/arch pair
                                                     -- (OPTIONAL)
  begin
  testSequence: Process
                              --Main test process
  end process;
  DUT:TestComp port map(        --Port map all the DUTs
                       );
End arch_TB;

ECE 545 – Introduction to VHDL                                                48
 Testbench For XOR3
 library ieee;
 use ieee.std_logic_1164.all;

 entity XOR3_TB is
 end XOR3_TB;

 architecture XOR3_TB_ARCHITECTURE of XOR3_TB is
 -- Component declaration of the tested unit
 component xor3
 port(
  A : in std_logic;
  B : in std_logic;
  C : in std_logic;
  RESULT : out std_logic );
 end component;

 -- Stimulus signals - signals mapped to the input and inout ports of tested entity
 signal TEST_VECTOR:STD_LOGIC_VECTOR(2 downto 0);
 signal TEST_RESULT: STD_LOGIC;



ECE 545 – Introduction to VHDL                                                        49
 Testbench For XOR Gate(2)
 begin
 UUT : xor3
  port map (
              A => TEST_VECTOR(0),
              B => TEST_VECTOR(1),
              C => TEST_VECTOR(2),
              RESULT => TEST_RESULT);
                                 );
 TESTING: process
 begin
 TEST_VECTOR<="000";
 wait for 10 ns;
 TEST_VECTOR<="001";
 wait for 10 ns;
 TEST_VECTOR<="010";
 wait for 10 ns;
 TEST_VECTOR<="011";
 wait for 10 ns;
 TEST_VECTOR<="100";
 wait for 10 ns;
 TEST_VECTOR<="101";
 wait for 10 ns;
 TEST_VECTOR<="110";
 wait for 10 ns;
 TEST_VECTOR<="111";
 wait for 10 ns;
 end process TESTING;
 end XOR3_TB_ARCHITECTURE;


ECE 545 – Introduction to VHDL          50
 Execution of statements in a PROCESS
                                    TESTING: process
                                    begin
                                           TEST_VECTOR<=“00”;
• The execution of statements              wait for 10 ns;
  continues sequentially till the
                                           TEST_VECTOR<=“01”;




                                       Order of execution
  last statement in the process.
• After execution of the last              wait for 10 ns;
  statement, the control is again          TEST_VECTOR<=“10”;
  passed to the beginning of the           wait for 10 ns;
  process.                                 TEST_VECTOR<=“11”;
                                           wait for 10 ns;
                                    end process TESTING;
                                    Program control is passed to the
                                      first statement after BEGIN



ECE 545 – Introduction to VHDL                                         51
 PROCESS with a WAIT Statement
 • The last statement in the         TESTING: process
   PROCESS is a WAIT instead of      begin
   WAIT FOR 10 ns.                          TEST_VECTOR<=“00”;
 • This will cause the PROCESS              wait for 10 ns;
   to suspend indefinitely when
                                            TEST_VECTOR<=“01”;




                                        Order of execution
   the WAIT statement is
   executed.                                wait for 10 ns;
 • This form of WAIT can be used            TEST_VECTOR<=“10”;
   in a process included in a               wait for 10 ns;
   testbench when all possible              TEST_VECTOR<=“11”;
   combinations of inputs have
   been tested or a non-periodical          wait;
   signal has to be generated.       end process TESTING;

  Program execution stops here



ECE 545 – Introduction to VHDL                                   52
 Wait for vs. Wait
      Wait for: waveform will keep repeating itself
      forever

          0        1        2    3   0   1   2   3   …

      Wait : waveform will keep its state after the
      last wait instruction.
                                                     …
ECE 545 – Introduction to VHDL                           53
 Sequential Statements (3)

 • Loop Statement
                                 for i in range loop
                                      statements
                                 end loop;

 • Repeats a Section of VHDL Code
       • Example: process every element in an array in
         the same way



ECE 545 – Introduction to VHDL                           54
 Loop Statement - Example

                  TEST_DATA_GENERATOR: process
                  begin
                          TEST_AB<="00";
                          TEST_SEL<="00";
                          for I in 0 to 3 loop
                                    for J in 0 to 3 loop
                                              wait for 10 ns;
                                              TEST_AB<=TEST_AB+"01";
                                    end loop;
                                    TEST_SEL<=TEST_SEL+"01";
                          end loop;
                  end process;




ECE 545 – Introduction to VHDL                                         55
             Structural Design Style




ECE 545 – Introduction to VHDL         56
                                 Structural VHDL

                                 Major instructions

    • component instantiation (port map)
    • generate scheme for component instantiations
                                 (for-generate)
    • component instantiation with generic
                                 (generic map, port map)




ECE 545 – Introduction to VHDL                             57
                                 Structural VHDL

                                 Major instructions

    • component instantiation (port map)
    • generate scheme for component instantiations
                                 (for-generate)
    • component instantiation with generic
                                 (generic map, port map)




ECE 545 – Introduction to VHDL                             58
Structural Example:
                                               in1
                                                      nand_out
                                               in2


                                 Component NAND2 Instantiated Four Time




ECE 545 – Introduction to VHDL                                            59
                                 Structural VHDL

                                 Major instructions

    • component instantiation (port map)
    • generate scheme for component instantiations
                                 (for-generate)
    • component instantiation with generic
                                 (generic map, port map)




ECE 545 – Introduction to VHDL                             60
Iterative circuits: 8-bit comparator

                         A(7) B(7) A(6) B(6)      A(0) B(0)

       CMP_IN(1)                                              CMP_OUT(1)

       CMP_IN(0)                                              CMP_OUT(0)

                                               COMPARE8
         entity COMPARE8 is
            port(
               A, B: in STD_LOGIC_VECTOR(7 downto 0);
               CMP_IN: in STD_LOGIC_VECTOR(1 downto 0);
               CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0));
         end COMPARE8;



 ECE 545 – Introduction to VHDL                                            61
8-bit comparator: Truth Table

               CMP_IN                     CMP_OUT

                    00                    00 if A=B
                                          10 if A>B
                                          01 if A<B
                    10                    10 independently of A and B

                    01                    01 independently of A and B

                    11 (invalid inputs)   --



 ECE 545 – Introduction to VHDL                                     62
Basic building block

                                     A    B

                             X_IN             X_OUT

                             Y_IN             Y_OUT

                                         BIT_COMPARE


                  entity BIT_COMPARE is
                         port(A, B, X_IN, Y_IN: in STD_LOGIC;
                                 X_OUT, Y_OUT: out STD_LOGIC);
                  end BIT_COMPARE;


ECE 545 – Introduction to VHDL                                   63
 Basic building block – Truth Table

              X_IN & Y_IN                X_OUT & Y_OUT

                   00                    00 if A=B
                                         10 if A=‘1’ and B=‘0’
                                         01 if A=‘0’ and B=‘1’
                   10                    10 independently of A and B

                   01                    01 independently of A and B

                   11 (invalid inputs)   --



ECE 545 – Introduction to VHDL                                     64
 8-bit comparator - Architecture


                                 INT_X(7) INT_X(6) INT_X(1)

                        A(7) B(7) A(6) B(6)            A(0) B(0)

      CMP_IN(1)                                                    CMP_OUT(1)

      CMP_IN(0)                                                    CMP_OUT(0)



                                 INT_Y(7) INT_Y(6) INT_Y(1)




ECE 545 – Introduction to VHDL                                                  65
Architecture without for-generate
  architecture STRUCTURE of COMPARE8 is
     component BIT_COMPARE
        port(A, B, X_IN, Y_IN: in STD_LOGIC;
             X_OUT, Y_OUT: out STD_LOGIC);
     end component;

      signal INT_X, INT_Y: STD_LOGIC_VECTOR(7 downto 1);

  begin
     C7: BIT_COMPARE port map(A(7), B(7), CMP_IN(1), CMP_IN(0),
                              INT_X(7), INT_Y(7));
     C6: BIT_COMPARE port map(A(6), B(6), INT_X(7), INT_Y(7),
                              INT_X(6), INT_Y(6));
         . . .
     C0: BIT_COMPARE port map(A(0), B(0), INT_X(1), INT_Y(1),
                              CMP_OUT(0), CMP_OUT(1));
  end STRUCTURE;


ECE 545 – Introduction to VHDL                                    66
 8-bit comparator - Architecture


                 INT_X(8)        INT_X(7)     INT_X(1) INT_X(0)

                        A(7) B(7) A(6) B(6)       A(0) B(0)

      CMP_IN(1)                                               CMP_OUT(1)

      CMP_IN(0)                                               CMP_OUT(0)



                 INT_Y(8)        INT_Y(7)     INT_Y(1) INT_Y(0)




ECE 545 – Introduction to VHDL                                             67
Architecture with for-generate
architecture STRUCTURE of COMPARE8 is
   component BIT_COMPARE
      port(A, B, X_IN, Y_IN: in STD_LOGIC;
           X_OUT, Y_OUT: out STD_LOGIC);
   end component;
   signal INT_X, INT_Y: STD_LOGIC_VECTOR(8 downto 0);

begin
   INT_X(8) <= CMP_IN(1);
   INT_Y(8) <= CMP_IN(0);

    CASCADE: for I in 7 downto 0 generate
       C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1),
                             INT_X(I), INT_Y(I));
    end generate;

   CMP_OUT(1) <= INT_X(0);
   CMP_OUT(0) <= INT_Y(0);
end STRUCTURE;

ECE 545 – Introduction to VHDL                                       68
                                 Structural VHDL

                                 Major instructions

    • component instantiation (port map)
    • generate scheme for component instantiations
                               (for-generate)
    • component instantiation with generic
                               (generic map, port map)




ECE 545 – Introduction to VHDL                           69
N-bit Comparator – Entity declaration


         entity COMPAREN is
            generic(N: positive); -- N – width of operands
            port(
               A, B: in BIT_VECTOR(N-1 downto 0);
               CMP_IN: in BIT_VECTOR(1 downto 0);
               CMP_OUT: out BIT_VECTOR(1 downto 0));
         end COMPAREN;




ECE 545 – Introduction to VHDL                               70
N-bit Comparator – Architecture
 architecture STRUCTURE of COMPAREN is
    component BIT_COMPARE
       port(A, B, X_IN, Y_IN: in STD_LOGIC;
            X_OUT, Y_OUT: out STD_LOGIC);
    end component;
    signal INT_X, INT_Y: STD_LOGIC_VECTOR(N downto 0);
 begin
    INT_X(N) <= CMP_IN(1);
    INT_Y(N) <= CMP_IN(0);

     CASCADE: for I in N-1 downto 0 generate
        C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1),
                              INT_X(I), INT_Y(I));
     end generate;

    CMP_OUT(1) <= INT_X(0);
    CMP_OUT(0) <= INT_Y(0);
 end STRUCTURE;

ECE 545 – Introduction to VHDL                                        71
N-bit Comparator – Instantiation
         component COMPAREN
            generic(N: positive); -- N – width of operands
            port(
               A, B: in STD_LOGIC_VECTOR(N downto 0);
               CMP_IN: in STD_LOGIC_VECTOR(1 downto 0);
               CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0));
         end component;
         ………

         CMP8: COMPAREN
            generic map(N => 16)
            port map(A => P1,
               B => P2,
               CMP_IN => SIG_IN,
               CMP_OUT => SIG_OUT
            );


ECE 545 – Introduction to VHDL                               72

								
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