Efficient Prototyping of Analog and Mixed Signal Integrated Circuits

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					SAME 2008 Forum



                           Tutorial 3

        Efficient Prototyping
    of Analog and Mixed Signal
         Integrated Circuits
Author and Speaker: Dipl.-Ing. Peter Pann, austriamicrosystems AG


                                                                    1
        Table of contents

  Introduction
  Tape-out procedure
  Parallel prototyping
  Reduction of NRE costs
  Efficient product launch
  Online tools
  Conclusions
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        Introduction

  Abstract
   - This tutorial recommends procedures, methods and tools for the
     layout tape-out phase of a project until series production ramp-up.

   - Goal is to show how to establish an efficient interface to external
     foundries including back-end services (assembly and test).

   - Focus is on prototyping of analog and mixed signal integrated circuits
     on advanced analog fabrication processes.




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        Introduction

  What is efficiency ?
                                    Benefit
                    Efficiency =                       (Wikipedia)
                                    Effort

   - Benefit: Fast time to market (“first-time-right” design), large revenues,
              high margin, high yield, reliable product, competitive product,
              market leadership.

   - Effort:        Usage of internal and external resources, NRE development
                    costs, investments, license fee for tools and IP blocks,
                    costs for failure analysis and bug fix.
                                                                            4
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        Introduction

  Prototype definition
   – Engineering samples,
     eng. dice or eng. wafers

             untested wafers to WAT spec
             untested dice
             untested assembled parts


   – Prototypes, prototype dice
     or prototype wafers

             tested wafers
             tested dice
             tested and qualified parts

                                           5
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        Introduction

  IDM vs. fabless semiconductor industry
   - Low capital investment, need of specialty processes
   - Concentration on Marketing, business development and IP design




                                                                      6
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        Introduction

  Concerns when using an external foundry
   -   Design Kit and IP block availability and quality
   -   Simulation model accuracy
   -   Package model availability (RF)
   -   Testability (Mixed Signal, RF, HV)
   -   Yield
   -   Costs
   -   Quality
   -   Reliability
   -   Cycle time
   -   Supply chain

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        Tape-out Procedure

  Interface to foundries
   -   Confidentiality agreement
   -   General procurement contract
   -   IP block license agreement
   -   Datasheets
   -   Design kit
   -   Design rule document
   -   Process parameter document
   -   Test specification
   -   Tape-out form
   -   Purchase order
   -   Data drop-box (ftp, sftp, encryption)
                                               8
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        Tape-out Procedure

   - Input checks performed by foundries

             Integrity of GDSII file
             Grid check
             Derived layer generation check
             Boolean EXOR combination with previous layout version
             Line mode check
             Die size check
             Seal ring check
             Pad stack and bond pitch check
             Scribe line width requirements review
             Poly/metal/contact density checks (local and global)
             Basic ESD rule check
             Electrostatic antenna check
             DRC with reference (sign-off) tool (optional)
             ERC (optional)
             DFM (basic, extended optional)                          9
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        Tape-out Procedure


   - Layout and consultancy services

             Automatic place & route
             IP block implementation
             Fill and hole structure generation
             MPW clustering for dedicated MPWs

             ESD and EMC consultancy
             Test review
             Design review (if foundry is an IDM)



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        Parallel Prototyping

  Dedicated MPW
   – Fabrication of wafers up to metallization


         base layers       base layers        base layers
       for all product   for all product    for all product    Chip layout
          versions          versions           versions        cluster size
                                                                      =
                                                                    up to
         base layers       base layers        base layers
                                                              full reticle size
       for all product   for all product    for all product
          versions          versions           versions



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        Parallel Prototyping

  Dedicated MPW
   – Product options on metallization masks


        metallization    metallization      metallization
         for product     for product        for product        Chip layout
          version 1       version 2          version 3         cluster size
                                                                      =
                                                                    up to
        metallization   metallization for     metallization
                                                              full reticle size
        for product      for product          for product
        version 1.1      versions 2.1         version 3.1



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        Parallel Prototyping

  Dedicated MPW
   – Final mask set is not longer an MPW


        metallization    metallization      metallization
         for product     for product        for product      Chip layout
          version 1       version 1          version 1       cluster size
                                                                    =
                                                                  up to
        metallization   metallization for   metallization
                                                            full reticle size
        for product      for product        for product
         version 1        versions 1         version 1



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        Parallel Prototyping

  Dedicated MPW
   – Piggyback design: 10 % ramp-up yield loss spent for next product
     development (only possible if full level-redesigns are planned)

      1    1     1   1    1    1     1   1   1   1    1    1    1 1       1    1
      1    1     1   1    1    1     1   1   1   1    1    1    1 1       1    1       Chip layout
      1    1    1    1    1    1     1   1   1   1    1    1    1 1       1    1       cluster size
                                                                                              =
      1    1    1    1    1    1     1   1   1   1    1    1    1 1       1    1            up to
                                                                                      full reticle size
      1    1    1    1 1       1     1   1   1 1      1    1    1 1       1    1
      1    1    1    1 1       1     1   1   1 1      1    1    1 1       1    2
                                                                               1

                                                     timeline product 1 development
    timeline product 2 development
                                                                                                     14
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        Parallel Prototyping

  Single die mask with metal options
   – Fabrication of wafers up to metallization


         base layers        multiple            multiple
       for all product     placement          placement
          versions        in maskshop        in maskshop     Chip layout
                                                                    <
                                                           full reticle size
            multiple         multiple          multiple
          placement        placement          placement
         in maskshop      in maskshop        in maskshop



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        Parallel Prototyping

  Single die mask with metal options
   – Finishing of wafers with metallization set 1


        metallization       multiple            multiple
        for product        placement          placement
         version 1        in maskshop        in maskshop      Chip layout
                                                                     <
                                                            full reticle size
            multiple         multiple           multiple
          placement        placement           placement
         in maskshop      in maskshop         in maskshop



                                                                           16
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        Parallel Prototyping

  Single die mask with metal options
   – Finishing of wafers with metallization set 2


        metallization       multiple            multiple
        for product        placement          placement
         version 2        in maskshop        in maskshop      Chip layout
                                                                     <
                                                            full reticle size
            multiple         multiple           multiple
          placement        placement           placement
         in maskshop      in maskshop         in maskshop



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        Reduction of NRE Costs

  MPW (Multi Product Wafer) program

                     - Shared masks with up to 30 participants
                     - Participation fee per mm²
                     - Minimum charge for small dice
                     - Delivery of dice or assembled parts
                     - Additional services like DRC possible
                     - Low volume production possible



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        Reduction of NRE Costs

  MLM (Multi Level Mask) program

                               - Different mask levels on one reticle
       metal 1       metal 2   - Mask cost reduction up to 75 %
                               - Suitable for prototyping and low volume
                                 production
       metal 3       metal 4   - High volume production is not possible,
                                 new mask set is needed.




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        Efficient Product Launch

  Parallel development flows




                                   20
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        Efficient Product Launch

  Test and qualification
   –   Check for tester capability prior to design start
   –   Design for testability
   –   Consider hardware influence (probecard, final test loadboard)
                                                                Qualification
                                                          (minimum requirement)
                                                        ESD qualification
                                                        Latch-up qualification
                                                        QA test program release
                                                        Temperature characterization
                                                        GR&R

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        Efficient Product Launch

  Test and qualification
   – Correlation between production and bench test


                                                             Goal
                                            Correlation with golden samples
                                            (from bench test, design verification)
                                            Generation of silver samples
                                            (from production test)
                                            Definition of final specification
                                            limits for 25 °C



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        Efficient Product Launch

  Test and Qualification
   – Temperature characterization


                                           Goal
                                    Define final test
                                                  C
                                    limits for 25° test
                                    QA sample tests
                                    at 3 temperatures




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        Efficient Product Launch

  Yield investigation
   – Defect based yield based on D0=0.1 D/mm², die size 50mm² ~ 99.5 %
   – Parametric yield for analog circuits is lower due to various reasons
                                                   Distribution cut
                                     Parasitic effects on silicon which cannot
                                     be simulated
                                     Package influence (bond wire inductance,
                                     plastics mold material influence)
                                     Guard bands to bench test
                                     Model inaccuracy
                                     Interferences between building
                                     blocks (top level chip simulation)
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        Efficient Product Launch

  Yield optimization
   – Process capability analysis
   – Six Sigma Design (Cpk=2)
                                               Definition
                                   Cpk = min (µ-LSL, USL-µ ) / 3σ
                                   Cp = (USL-LSL) / 6σ




                                                               25
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        Efficient Product Launch

  Yield optimization
   – Yield pareto analysis

                                      Task
                             Find “yield killers”
                             Find “test time killers”
                             - never failing tests
                             due to redundancy




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        Efficient Product Launch

  Yield optimization
   – “What If” limit investigation (example IDS Solutions / DataPower)

                                                                      Task
                                                               Investigate
                                                               limit change impact
                                                               on yield




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        Efficient Product Launch

  Safe product launch concepts
   –   SBL Statistical Bin Limit:     µ+3σ
   –   SYL Statistical Yield Limit:   µ-3σ
   –   PAT Part Average Testing:      outlier removal
                                                            SBL/SYL/PAT
                                                        based on historical data
                                                        variable during ramp-up
                                                        reduces field returns
                                                        automotive requirement




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            Efficient Product Launch

   Corner lots
     – Typical corner lot definition
     – Individual corners on request

Condition              NMOS Transistor    PMOS Transistor   Bipolar   HR Poly + Poly 2   Capacitor    Wafers
                      LEFF          VT   LEFF          VT    BETA      SHEET RES           VALUE
Typical Mean          typ          typ   typ          typ     typ             typ           typ           2
Worst Case Speed       >            >     >            >       <               >             >            2
Worst Case Power       <            <     <            <       >               <             <            2
Worst Case One         typ          <     typ          >      typ             typ           typ           2
Worst Case Zero        typ          >     typ          <      typ             typ           typ           2




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        Efficient Product Launch

  Corner lots
   – Example CMOS transistor driving capability

                                                                                physical
              Vt PMOS




                                          Corner Lot - Matrix
                                                                                limitation
                        Leff typ.                                      Leff >                       Conditions
        max
                                          WO                    WS                           TM = typical mean
                                                 TM                                          WS = worst case speed
                                                                                             WP = worst case power
                                      WP                        WZ
        min
                           Leff <                                      Leff typ.             WO= worst case digital 1
                                                                                             WZ = worst case digital 0
                                    min                          max            Vt NMOS




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        Efficient Product Launch

  Corner lots
   – Practical example of a MIM capacitor variation



                                                               Conditions
                                                      min 2 wafers per split
                                                      typical wafers as reference




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        Efficient Product Launch

  Corner lots
   – Evaluation of a PLL VCO band overlap versus MIM capacitor variation


                                                                Conditions
                                                            best result but risky
                                                            due to “out of spec”
                                                            MIM cap value
                                                            acceptable result,
                                                            low risk
                                                            verification of MIM
                                                            cap influence



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        Online Tools
                                                 Examples
  WEB portal                      Design kits including cell libraries
                                  Simulation models
                                  Design rules / process parameters
                                  Application notes
                                  Package information
                                  Memory generators
                                  IP block and library datasheets
                                  Qualification monitoring reports
                                       drop-
                                  Data drop-box
                       customer
                                  MPW shuttle service
                                  WIP/ORDER/SHIP data
                                  Key performance indicators (KPI)
                                  WAT data                           33
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        Conclusions

  Include test development
  for prototyping of analog circuits
  Use parallel flows to reduce cycle times
  Share mask costs with other customers
  or other projects
  Choose foundries with back-end service
  Establish safe product launch concepts to
  reduce field returns
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