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Lecture 26: Virtual Memory, TLBs, and
Caches
Chapter 7
Multitasking
• Most OS’s multitask
– Run Program A and B at the same time
• Most CPUs must support multitasking
– Not run at exactly the same time:
• Run Program A for 20ms
• Run Program B for 20ms
• Run Program A for 20ms, etc
Programs Sharing Memory
• Computer has 128MB
– Netscape uses 60MB
– Word uses 35MB
– Windows uses 45MB
– Total: 140MB
• How to run all 3?
• It gets worse….
– Netscape assumes memory starts at address 0
– Word assumes memory starts at address 0
• How can they both run if they both assume memory starts at 0 ??
– Windows ? It’s the OS…. who knows!
Programs Sharing Memory
• It gets even worse Word
Net
– Windows starts using 45MB
– Netscape starts using 16MB Word
– Word starts using 20MB
Net
– User opens web page, Netscape wants +32MB
Word Main
– User opens document, Word wants +10MB
– User opens 2nd web page, Netscape wants +12MB Mem
– User edits document, Word wants +5MB
Net
– TOTAL
• Windows 45MB, Netscape 60MB, Word 35MB
Win
Programs Sharing Memory
• It gets even worse
– Exit Word
– Start Engineering program
Net
• Wants 30MB for a matrix
• Must be contiguous!
• How? Net
• Move Netscape? Not realistic
Main
• Solution?
– Divide Main Memory into pages,
Mem
say 4KB each Net
– Divide Programs into pages (same size)
– Map Program Pages into Main Memory Pages
– Store extra Program Pages on disk Win
Solution: Virtual Memory
Netscape sees this Main Memory sees this
Virtual addresses Physical addresses
Address translation
Net
Net
Net Pages
Net
Net Net
Net
Net
Net
Fragmented:
Non-contiguous
Can store some (holes),
on disk! out-of-order,
Disk addresses
some on disk
Address Translation
Page Size:
Virtual address 2^12 = 4096 bytes
31 30 29 28 27 15 14 13 12 11 10 9 8 3210
Virtual page number Page offset
Table Lookup
Translation
29 28 27 15 14 13 12 11 10 9 8 3210
Physical page number Page offset
Physical address
Virtual Memory
• Program Viewpoint
– Addresses start at 0
– Malloc() gives program contiguous memory (consective addresses)
– Malloc(), Free(), Malloc(), Free()
• Can malloc() re-use parts that are freed?
• Causes internal fragmentation within one program
– There is lots of free memory available
• CPU/OS Viewpoint
– Keep all programs separate
• Don’t all start at 0
• Security implications…. programs should not read each other’s data!
– Dynamic program behaviour cause memory fragmentation
• Starting & ending programs, swapping to disk
• Causes external fragmentation between programs
– Limited memory available
• Use Disk to hold extra data
• Use Main Memory like a cache for the program data stored on disk
• New structure: Page Table
Page Table: Big Lookup Table
Netscape sees this Main Memory sees this
Virtual Addresses Physical Addresses
Address Net
Translation
Net
Net
Net
Net Net
Net
Net
Net
Fragmented:
Non-contiguous
(holes),
Page Table out-of-order,
Disk addresses
some on disk
Page Table
• Holds virtual-to-physical address translations
• Access like a memory
– Input: Virtual Address
• Only need Virtual PageNumber portion (upper bits)
• Lower bits are PageOffset, ie which byte inside the page
– Output: Physical Address
• Lookup gives a Physical PageNumber
• Combine with PageOffset to form entire Physical Address
• Where to hold the PageTable for a program?
– Dedicated memory inside CPU? Too big! not done!
– Instead, store it in main memory
Page Table Translation Structure
Page Table Register
Virtual Address
31 30 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0
Virtual Page Number Page Offset
20 12
Size of Valid Physical Page Number
Page Table?
2^20 or
~1 million Page
entries Table
18
If 0 then page
is on disk
1 Page Table 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0
Per Program! Physical Page Number Page Offset
Physical Address
Page Table Implications
• CPU executes “Load” instruction
– Recall: address is now a Virtual Address
– First step: Lookup address translation
• Where is page table? In main memory
• Special CPU register called Page Table Register (PTR)
– Holds starting address of page table
• Read DataMem from PTR+PageNumber to get Physical Address
– Second step: Access the data
• Read DataMem from Physical Address
• Every load/store requires TWO memory accesses
– Slow!
– Can we speed up the translation step? Yes, use a cache!
TLB: Translation Looksaside Buffer
(A special cache for the Page Table)
Virtual page Physical Page
V Tag
number Number
TLB
1
1 Physical Memory
1
1
0
1
Physical Page Number
V or Disk Address
1
1
1 Disk
1
0
1
1
Page 0
1
Table 1
0
1
Memory Access:
TLB Usage Algorithm
Virtual address
NOTICE: software
NOTICE: TLB access designates some memory
exception pages as READ-ONLY
(interrupt) on miss,
software (OS) Example: pages holding
handles TLB instructions.
misses, not TLB miss No Yes
TLB hit? It will may share some
hardware exception Physical address read-only pages with
multiple programs, eg you
run Netscape twice.
No Yes
Write?
Try to read data
from cache No Write access Yes
bit on?
Write protection
exception Write data into cache,
No Yes update the tag, and put
Cache miss stall Cache hit? the data and the address
into the write buffer
Deliver data
to the CPU
TLB Notes
• TLB Miss
– Not handled by hardware
– CPU raises exception (interrupt)
– OS must fix, because it may have to get data from the disk
– OS handles security issues as well
• Read-only pages
– Can share non-sensitive data, eg instructions and pre-compiled data
tables in a program such as Netscape
– Writes to read-only pages cause exception
– OS handles, possible outcomes:
• Illegal to write to this page
• Change page to writable
• If page is shared, make a new writable copy of this page for this program
only. Remaining program share the original read-only copy.
Combined TLB & Cache Structure V irtu a l a dd res s
31 3 0 29 15 14 1 3 12 11 10 9 8 3 2 1 0
V irtu a l p a g e n u m b e r P a g e o ffs et
20 12
V a lid D irty Tag P h y sic a l pa g e n u m be r
T LB
1. TLB lookup T L B h it
20
2. Convert VA to PA P h y sica l p a ge n u m b e r P a g e o ffs e t
P h y sica l a d d re s s
P h y sica l a d d re ss ta g C a c h e in d e x B y te
o ffse t
16 14 2
3. Access data
cache V a lid Tag D a ta
C a ch e
NOTE: TLB is
now slowing 32
our cache!! C a ch e hit D a ta
TLB first, Cache second ?
• TLB first, Cache second strategy is slow
– Called Physically Indexed, Physically Tagged
• To improve performance:
– Lookup TLB, Lookup Cache at same time
– Must use Virtual Address to lookup in cache
– Compare Physical Address (output of TLB) to TAG
(output of cache) when checking cache hit
– If OK, we can use the data
– Called Virtually Indexed, Physically Tagged
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