DSP with FPGA

Document Sample
DSP with FPGA Powered By Docstoc
					   DSP with FPGA
ASIC & FPGA Café
  2004년 4월 18일
  발표자 : 김 한 수
Introduction
   Overview of Digital Signal Processing.
   FPGA Technology.
       Classification By Granularity.
       Classification By Technology.
       Benchmark for FPLs.
   DSP Technology Requirements.
       FPGA and Programmable Signal Process.
   Design Implementation.
       FPGA Structure.
FPGA Technology
   FPGA는 FPL의 한 종류이다.
       FPL은 작은 Logic Block과 element를 반복하여 저장하는 Programmable
        Device.
       ASIC Technology.
       Application-Specific ICs.
   알갱이 모양에 의한 분류.
       Fine Granularity. (Sea of Gate Architecture)
       Medium Granularity. (FPGA)
       Large Granularity. (CPLD)
Classification By Granularity
   Fine-Granularity Device.
       License By Plessey and later by Motorola.
       기본 Logic Cell은 NAND 와 Latch이다.
           Any Binary Logic Function Using NAND Gate.
   Medium-Granularity Device.
       대부분의 공통되는 FPGA Architecture. (Medium-grain FPGA)
       기본 Logic Block은 작은 Table이다. (4 to 5 bit Input Table)
       Programmable I/O with F/F는 Device의 주위에 물리적으로 연결.
   Large-Granularity Device.
       CPLD는 SPLD로 불리워지는 결합되어짐으로서 정의.
       SPLD는 PLA로 구성된다.
           AND/OR array and universal I/O Logic Block와 같은 도구.
CPLDs and FPGAs
                     CPLD                               FPGA
       Complex Programmable Logic Device     Field-Programmable Gate Array




Architecture          PAL-like                         Gate array-like
Density               Low-to-medium                    Medium-to-high
Basic Cell            Product Term                    CLB & LUT
Application          Combination based                Register Based
Performance          Predictable timing                Application dependent
Design Entry          Equation & Schematic             Schematic & HDL
Classification by Technology
   Available in all memory Technology for FPL.
       SRAM, EPROM, E2PROM, Antifuse.
   SRAM device dominate Technology for FPGAs.
       Based on static CMOS Memory Technology.
   Electrically Programmable Read-Only (EPROM).
       One time CMOS Programmable (Ultraviolet Light for Erasure)
   Electrically Erasable Programmable (E2PROM).
       Reprogrammable and In system Program.
   Based on an EPROM Technology.
       Called Flash Memory.
       물리적으로 작은 Cell들을 가지는 System.
       In-System Reprogrammable.
Xilinx FPGA Top-level Architecture
   Gate-array like architecture
   Configurable logic blocks
     Implement logic here!

   I/O blocks
     16+ signal standards

   Block RAM
     On-chip memory for
       higher performance
   Clocks & Delay-Locked
    Loop
   Interconnect resources
     Three-state internal
       buses
The CLB Structure
Simple Slice Architecture
   Each slice has two sets of
       Four-input LUT
           Any 4-input logic
            function
           Or 16-bit x 1 RAM
           Or 16-bit shift register
       Carry & Control
           Fast arithmetic logic
           Multiplier logic
           Multiplexer logic
       Storage element
           Latch or flip-flop
           Set and reset
           True or inverted inputs
           Sync. or Async. Control
DSP Technology Requirements
   FPGA and Programmable Signal Processors.
       Most DSP Algorithm is Multiply와 accumulate (MAC).
       FPGA can used to implement MAC Cells.
       Cost issues will Most give PDSPs an Advantage.
   Design Implementation.
       FPGA is Programmable but fixed.
       Gate Level using register transfer design language.
       IP, Macro cell, mega core cells.
       A key point in FPGA Technology.
           Shorten the design cycle.
           Provide good utiltization of the device.
           Provide synthesizer option.
    Example
   Comparison of VHDL Design Styles.
       Component Instantiation (Stuctural Style.)
       Data Flow Representation.
       Sequential Design (Using Process)
Example Code
PACKAGE eight_bit_int IS                    -- use Defines Type
  SUBTYPE BYTE IS INTERGER RANGE -128 TO 127;
END eight_bit_int;

LIBRARY work;
USE work.eight_bit_int.ALL;

LIBRARY lpm;                           -- Using Predefined Package
USE lpm.lpm_components.ALL;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
Example Code
ENTITY example IS                                            -- Interface
   GENERIC( WIDTH : INTEGER := 8);
  PORT( clk : IN STD_LOGIC;
                    a, b : IN BYTE;
                    op1 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                    op2 : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                    d    : OUT BYTE
         );
END example;

ARCHITECTURE flex OF example IS
   SIGNAL c, s               : BYTE;                 -- Auxiliary variable
   SIGNAL op2, op3           : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
BEGIN
   -- Conversion int -> logic vector
   op2 <= CONV_STD_LOGIC_VECTOR(b,8)
Example Code
add1 : lpm_add_sub                       -- component instantiation
   GENERIC MAP ( LPM_WIDTH => WIDTH,
                     LPM_REPRESENTATION => “SIGNED”,
                     LPM_DIRECTION => “ADD”)
   PORT MAP ( dataa => op1,
                 datab => op2,
                 result => op3);
   reg1 : lpm_ff
         GENERIC MAP (LPM_WIDTH => WIDTH)
         PORT MAP ( data => op3,
                       q => sum,
                       clock => clk);
   c <= a + b;                           -- Data Flow Style
Example Code
  p1 : PROCESS                   -- Behavioral Style
  BEGIN
         WITH UNTIL clk = „1‟;
         s <= c + s;                     -- Signal assignment statement
  END PROCESS p1;
         d <= s;
END flex;

				
DOCUMENT INFO
Shared By:
Categories:
Stats:
views:20
posted:6/5/2010
language:English
pages:15