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                           Syed K. Islam, Hafijur Rahman & Venkatesh Srinivasan
       Department of Electrical & Computer Engineering, University Of Tennessee, Knoxville, TN 37996-2100


Timing information in the form of clock or oscillator signals play a critical role in most modern applications. The
timing jitter or uncertainty in the timing information presents a serious limitation in the achievable system
performance. For instance, timing errors can degrade the signal-to-noise ratio (SNR) of an A/D converter, limit the
speed of a digital I/O interface or the bit error rate of a communications link. And these are just a few of the many
examples. Furthermore, Phase Locked Loops (PLL’s) are used in most of the applications to generate the necessary
timing signals. With the need for high integration implementations, there has been a growing demand for fully
monolithic, on-chip PLLs. However, minimizing the timing jitter in PLLs is non–trivial and requires careful
attention to a number of factors. Our research focuses on fully integrated PLLs with low phase noise and timing
jitter used in frequency synthesizer applications.

Amongst all the PLL components, the VCO is the noisiest. Reducing the VCO noise can lead to significant gains in
the PLL performance. Towards this end, a ring oscillator with symmetric loads is designed and optimized for low
phase noise and jitter. A theoretical analysis of the noise processes in the ring oscillator provides an insight into the
design parameters. Though the frequency divider contributes negligible noise compared to the VCO, it is a challenge
to design high frequency, low noise programmable dividers. The research focuses on current mode differential
structures, as they lend themselves to high speed operations and possess low phase noise

Project Description
The block diagram for the proposed chip is shown in Figure 1. The Bias and Control unit houses the biasing and
control circuitry needed for the VCO. The VCO operating frequency is controlled using the ‘Vcon’ pin. In order to
validate theoretical analysis, it is important that each block be tested individually as well. To achieve this, the
divider can be decoupled from the VCO through an external pin (‘Select’) as shown in Figure 1. This way, the phase
noise performance of the VCO can be measured independently and also, the frequency divider can be characterized
for its performance from an external signal generator.

                                      Bias +
              Vcon                                                                                fout1
                                      Control                         VCO


                          Select                                   Frequency
                                                                    Divider                      fout2

                                             Figure 1. Chip Block Diagram
Voltage Controlled Oscillator

One of the most popular approaches for realizing a VCO is by implementing it using a ring oscillator. Ring
oscillators are attractive from an integration and cost point of view, but are very noisy and hence introduce a lot of
jitter in the generated clock. Ring oscillators with symmetric loads offer very high supply noise rejection and also
lend themselves to a self-biasing scheme as in [1]. For this reason, this project comprises of a 3-stage ring oscillator
with symmetric loads and its associated biasing and control circuitry. Using a differential delay stage further
improves performance on account of its ability to reject common-mode noise. A single stage of the ring oscillator is
shown in Figure 2. The VCO jitter is on account of the internal devices noise such as thermal and flicker. However,
thermal noise is the most important factor as the low frequency flicker noise is rejected by the PLL loop bandwidth.
Also, the supply and substrate noise degra de the VCO performance with regards to jitter. Based on the work in [2] &
[3], a theoretical approach for predicting the jitter generated by this symmetric load ring oscillator is being
developed both in the time domain and frequency domain. The chip fabrication and testing will help validate the

                                      Figure 2. Delay Cell used in Ring Oscillator

Frequency Divider

The dividers with current mode control and differential structure are preferred over their conventional counterparts
for high speed and low noise applications [4]. The current mode structure gives better control over the circuit and is
capable of providing higher speed operation. A series of D Flip-Flops (DFF) are pipelined to form the divider
architecture. Current mode logic combined with differential configuration has better electromagnetic compatibility
(EMC) properties because of constant supply current and differential voltage switching operation [5]. The dividers
in the frequency synthesizers can have fixed dividing ratios and programmable diving ratios. The conventional way
to design the programmable dividers is to use a modular approach, which is used for digital design as shown in
Figure 3  (a). Now days, programmable dividers with phase-switching architecture as shown in Figure 3 are     (b)
becoming popular. This is because, phase-switching architecture provides consecutive ratios starting from any
number and offer higher speed, but however are more complex to design. We design both types of dividers and
compare their various performance parameters.

                           (a)                                                              (b)

        Figure 3 Programmable divider (a) without phase-switching circuits (b) with phase-switching circuits
The chip will be designed for the AMI 0.5 micron process and is targeted for the February 25, 2002 run. Also, the
design is expected to conform to the tiny chip size of 2.25 sq mm.

Design and Simulation
The initial design and simulation will be performed using HSPICE. Using the FFT analysis capability of HSPICE,
the output spectrum of the ring oscillator can be observed. Once satisfactory results are obtained, the design will be
ported to the Cadence design environment. The frequency domain equivalent of jitter, namely phase noise, can be
measured using Spectre and from this, the timing jitter number can be obtained. It is hoped that this will be a first
step towards validation of the theory. A similar approach is planned for the frequency divider. Next, using the layout
tool Virtuoso, the designs will be laid out. In the cadence design environment, a Design Rules Check (DRC) and a
Layout Versus Schematics (LVS) check will be performed to ensure that everything is in order. Finally, a post –
layout simulation will be carried out for both the ring oscillator and the frequency divider.

Test & Characterization

The characterization will be performed using the HP4145B semiconductor parameter analyzer. Because, the
expected timing jitter is in the picoseconds range, a direct time domain measurement will be both complicated and
cumbersome. Frequency domain measurements of Phase Noise on the other hand are easy and elegant and can give
a quick estimate of the amount of jitter present. The phase noise will be measured using the HP8560EC spectrum
analyzer and using this information, the timing jitter will be back calculated. The frequency divider will be tested
both standalone and also using the output of the VCO.

[1] John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE
    JSSC, Vol. 31, No.11, pp. 1723 – 1732, Nov. 1996
[2] Todd C. Weigandt, B. Kim and P. R. Gray, “Analysis of Timing Jitter in CMOS Ring Oscillators,” IEEE JSSC,
    Vol. 4, pp. 27 – 30, Nov. 1994.
[3] Behzad Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE JSSC, Vol.31, No.3, pp. 331 – 343,
    March 1996
[4] S. Mehta, “ Design of High Frequency Dividers for Frequency Synthesis”, Research 1994-1995, Department of
    Electrical      Engineering     and      Computer    Science, University    of     California,    Berkeley
[5] F. Piazza and Q. Huang, " A low power CMOS dual modulus prescaler for frequency synthesizers," IEICE
    Trans. Electron., vol. E80-C, pp. 314-319, Feb 1997.

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