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Table 68 Thermal & Thin Film Difficult Challenges
Difficult Challenges 32 nm Summary of Issues
Gate dielectric scaling (including interface Extension of oxynitride gate dielectric materials to <
control and SiO2 mobility equivalence) 1.0 nm E.O.T for high performance MOSFETs, consistent
with device reliability requirements. Control of boron
penetration from doped polysilicon gate electrodes while
minimizing depletion of dual-doped polysilicon
electrodes.
Alternate high k dielectric with mobility > Timely introduction and process integration of high-k gate
90% of SiO2 (including interface control) stack materials and processes for high performance, low
operating and low standby power MOSFETs
Gate electrode scaling and alternate gate Enhanced doping of Poly-Si gate electrodes to minimize
electrodes depletion. Timely (2008) introduction of dual
workfunction metal gate electrodes having appropriate
workfunctions.
Channel mobility enhancement Optimization of local and/or global strain to
simultaneously enhance NMOS and PMOS channel
mobility without exceeding the critical yield strength of
the substrate.
Scaling silicide thickness Issues of scaling silicide thicknesses on gates and
junctions include: substrate consumption, linewidth
dependent sheet resistances, gate dopant loss through
segregation and evaporation, silicide transport along grain
boundaries to the gate dielectric, and reduced thermal
stability
Shallow trench isolation materials and High aspect ratio filling of trenches, stress control, and
processes bottom corner rounding to fill etched trenches without
damaging the substrate. Top corner rounding and recess
control to avoid parasitic device turn-on or shorting along
trench edges.
Difficult Challenges < 32 nm
Alternate high k dielectric with mobility > The ongoing need for each new generation is to find gate
95% of SiO2 (where interface layers may dielectric material(s) that have reduced EOT with no
be impractical) increased leakage, yet which provide high channel
mobility. In this regime even molecular interface layers
may contribute excessively to the overall EOT.
Alternate gate electrode (including etch Alternate gate electrode materials having different or
issues) tunable workfunctions will be required to satisfy the needs
of different device types (bulk, FDSOI, and multi-gate)
and different applications (HP, LOP, and LSTP). Etching
of these new gate stacks presents new challenges.
Devices having enhanced currents Control and optimization of strained layers in bulk
devices to enhance both electron and hole mobilities--
particularly in the context of non-classical CMOS devices.
Integration of alternate dielectric and gate The limited thermal stability of candidate materials may
materials with conventional CMOS require a dramatic lowering of junction formation
processing temperatures in conventional processes or, possibly, a
reversal of the junction and gate-stack formation
sequence.
Materials and processes for alternate Processes are required to controllably form ultra-thin
MOSFET device structures silicon layers as well as gate stacks for single- and dual-
gate SOI structures in either planar or vertical geometries.
Table 71a and b Thermal and Thin Film, Doping and Etching Technology Requirements
Near-term
Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 35 32
MPU/ASIC Metal 1 (M1) ½ Pitch
90 78 68 59 52 45 40 36 32
(nm)(contacted)
MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for 1E20-Doped Poly- 1.1 1.0 1.0
Si [A, A1, A2]
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for 1.5E20-doped Poly- 1.2 1.1 1.1 0.5
Si [A, A1, A2]
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for 3E20-Doped Poly- 1.3 1.2 1.2 0.71 0.54 0.41
Si [A, A1, A2]
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for Metal Gate [A, A1, 0.9 0.75 0.65 0.5 0.5
A2]
Gate dielectric leakage at 100°C (A/cm 2 )
1.8E+02 5.4E+02 8.0E+02 9.1E+02 1.1E+03 1.6E+03 2.0E+03 2.4E+03
Bulk High-performance [B, B1, B2]
Metal Gate Workfunction for Bulk
<0.2 <0.2 <0.2 <0.2 <0.2
MPU/ASIC |E c,v - f m | (eV) [C]
Mobility enhancement factor for bulk
1.09 1.09 1.08 1.09 1.1 1.1 1.12 1.11
MPU/ASIC [E]
Silicide thickness for Bulk MPU/ASIC (nm)
21 19 17 15 13 12 11 9
[L]
Contact silicide sheet Rs for Bulk MPU/ASIC
7.5 8.6 9.6 10.5 12.1 13.5 15.1 17.3
( W /sq) [M]
STI depth bulk (nm) [O] 367 359 353 339 335 331 323 316
Trench width at top (nm) [P] 80 70 65 57 50 45 40 35
Trench sidewall angle (degrees) [Q} >86.9 >87.2 >87.4 >87.6 >87.9 >88.1 >88.2 >88.4
Trench fill aspect ratio - Bulk [R] 5.1 5.6 5.9 6.4 7.2 7.9 8.6 9.5
Equivalent physical oxide thickness for
FDSOI MPU/ASIC Tox (nm) for Metal Gate 0.9 0.8 0.7 0.6 0.5 0.5
[A, A1, A2]
Gate dielectric leakage at 100°C (A/cm 2 )
7.7E+02 9.5E+02 1.2E+03 1.4E+03 2.1E+03 2.2E+03
FDSOI High-performance [B, B1, B2]
Metal Gate Workfunction for FDSOI
MPU/ASIC | f m - E i | (eV)| NMOS/PMOS +/- 0.15 +/- 0.15 +/- 0.15 +/- 0.15 +/- 0.15 +/- 0.15
[S]
Mobility enhancement factor for FDSOI
1.06 1.06 1.06 1.06 1.05 1.05
MPU/ASIC [E]
Effective ballistic transport factor for FDSOI
1 1 1 1 1 1.1
MPU/ASIC [T]
Si thickness FDSOI (nm) [U] 8 7 6.5 5.5 4.5 3
Silicide thickness for FDSOI MPU/ASIC
28 24 22 19 17 16
(nm) [L]
Contact silicide sheet Rs for FDSOI
5.8 6.7 7.4 8.3 9.5 10.2
MPU/ASIC ( W /sq) [M]
Trench fill aspect ratio - FDSOI [W] 0.6 0.6 0.6 0.6 0.6 0.6
Equivalent physical oxide thickness for multi-
gate MPU/ASIC T ox (nm) for metal gate [A, 0.8 0.7 0.6
A1, A2]
Gate dielectric leakage at 100°C (nA/µm)
6.3E+02 7.9E+02 8.5E+02
muti-gate High-performance [B, B1, B2]
Metal Gate Workfunction for multi-gate
midgap midgap midgap
MPU/ASIC [S]
Mobility enhancement factor for multi-gate
1.05 1.04 1.05
MPU/ASIC [E]
Effective ballistic transport factor for multi-
gate MPU/ASIC [T] 1.17 1.25 1.31
Si thickness for multi-gate (nm) [U] 9.5 8.5 8
Maximum allowble parasitic series
resistance for Multi-Gate NMOS MPU/ASIC 105 95 90
x width (( W-m m) [G]
Silicide thickness for Multi-Gate MPU/ASIC
19 17 16
(nm) [L]
Contact silicide sheet Rs for Multi-Gate
8.3 9.5 10.2
MPU/ASIC ( W /sq) [M]
Physical gate length low operating power
45 37 32 28 25 23 20 18 16
(LOP) (nm)
Equivalent physical oxide thickness for bulk
low operating power T ox (nm) for 1.5E20- 1.4 1.3 1.2 0.8 0.7 0.6 0.6 0.6
doped Poly-Si [A, A1, A2]
Equivalent physical oxide thickness for bulk
low operating power Tox (nm) for metal gate 1.1 1 0.9 0.9 0.9
[A, A1, A2]
Table 71a and b Thermal and Thin Film, Doping and Etching Technology Requirements
Near-term
Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 35 32
Gate dielectric leakage at 100°C for
6.7E+00 8.1E+00 1.6E+01 1.8E+01 2.0E+01 2.3E+01 9.0E+01 1.4E+02
bulk(A/cm 2 ) LOP [B,B1, B2]
Metal Gate Workfunction for Bulk low
<0.2 <0.2 <0.2 <0.2 <0.2
operating power |E c,v - f m | (eV) [S]
Equivalent physical oxide thickness for
FDSOI low operating power Tox (nm) for 0.9 0.9 0.8
metal gate [A, A1, A2]
Gate dielectric leakage at 100°C for FDSOI
4.0E+01 5.6E+01 6.3E+01
(A/cm 2 ) LOP [B,B1, B2]
Metal Gate Workfunction for FDSOI LOP
midgap midgap midgap
[S]
Equivalent physical oxide thickness for multi-
gate low operating power Tox (nm) for metal 0.9 0.9 0.8
gate [A, A1, A2]
Gate dielectric leakage at 100°C for multi-
2.5E+01 3.9E+01 4.4E+01
gate (A/cm 2 ) LOP [B,B1, B2]
Metal Gate Workfunction for multi-gate LOP
midgap midgap midgap
[S]
Physical gate length low standby power
65 53 45 37 32 28 25 23 20
(LSTP) (nm)
Equivalent physical oxide thickness for bulk
low standby power Tox (nm) for 1.5E20- 2.1 2.0 1.9 1.2 1.1 1 1 0.9 0.8
doped Poly-Si [A, A1, A2]
Equivalent physical oxide thickness for bulk
low standby power Tox (nm) for metal gate 1.6 1.5 1.4 1.4 1.3 1.2
[A, A1, A2]
Gate dielectric leakage at 100°C for bulk
1.5E-02 1.9E-02 2.2E-02 2.7E-02 3.1E-02 3.6E-02 4.8E-02 7.3E-02 1.1E-01
(A/cm 2 ) LSTP [B, B1, B2]
Metal Gate Workfunction for Bulk LSTP
<0.2 <0.2 <0.2 <0.2 <0.2 <0.2
|E c,v - f m | (eV) [S]
Equivalent physical oxide thickness for
FDSOI low standby power Tox (nm) for 1.3 1.2
metal gate [A, A1, A2]
Gate dielectric leakage at 100°C for FDSOI
4.5E-02 5.0E-02
(A/cm 2 ) LSTP [B, B1, B2]
Metal Gate Workfunction for FDSOI and
multi-gate LSTP | f m - E i | (eV)| -/+ 0.1 -/+ 0.1
NMOS?PMOS [S]
Equivalent physical oxide thickness for multi-
gate low standby power Tox (nm) for metal 1.2 1.1
gate [A, A1, A2]
Gate dielectric leakage at 100°C for multi-
4.5E-02 5.0E-02
gate (A/cm 2 ) LSTP [B, B1, B2]
Thickness control EOT (% 3 s ) [X] <±4 <±4 <±4 <±4 <±4 <±4 <±4 <±4 <±4
Poly-Si or Metal Gate electrode thickness
64 56 50 46 40 36 32 28 26
(approximate) (nm) [Y]
Trench dielectric maximum film stress TBD TBD TBD TBD TBD TBD TBD TBD TBD
Reduction in dopant segregation (%) TBD TBD TBD TBD TBD TBD TBD TBD TBD
Allowable Vt shift from charge in dielectric
10 10 10 10 10 10 10 10 10
(mV) [AG]
Allowable interfacial charge in high k gate
1.0E+11 1.1E+11 1.1E+11 1.8E+11 2.0E+11 2.2E+11 2.2E+11 2.4E+11 2.7E+11
stack (cm -2 )[AH]
Allowable bulk charge in high k gate stack
2.4E+17 2.7E+17 3.0E+17 7.5E+17 8.9E+17 1.1E+18 1.1E+18 1.3E+18 1.7E+18
(cm-3) [AI]
Allowable bulk charge in high k gate stack
11.1 12.3 13.6 34.0 40.5 49.0 49.0 60.5 76.6
(ppm) [AI]
Allowable critical metal impurity level in
1.1 1.2 1.4 3.4 4.1 4.9 4.9 6.1 7.7
high k dielectric (ppm) [AJ]
* Refer to supplemental material worksheets, 2003 Contact Rs and 2003 RsXj online for a more complete description of the modeled devices.
Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known
Interim solutions are known
Manufacturable solutions are NOT known
Table 71a and b Thermal and Thin Film, Doping and Etching Technology Requirements
Long-term
Year of Production 2014 2015 2016 2017 2018 2019 2020 Driver
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14 DRAM
MPU/ASIC Metal 1 (M1) ½ Pitch
28 25 23 20 18 16 14 MPU
(nm)(contacted)
MPU Physical Gate Length (nm) 11 10 9 8 7 6 6 MPU
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for 1E20-Doped Poly- MPU
Si [A, A1, A2]
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for 1.5E20-doped Poly- MPU
Si [A, A1, A2]
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for 3E20-Doped Poly- MPU
Si [A, A1, A2]
Equivalent physical oxide thickness for Bulk
MPU/ASIC Tox (nm) for Metal Gate [A, A1, MPU
A2]
Gate dielectric leakage at 100°C (A/cm 2 )
MPU
Bulk High-performance [B, B1, B2]
Metal Gate Workfunction for Bulk
MPU
MPU/ASIC |E c,v - f m | (eV) [C]
Mobility enhancement factor for bulk
MPU
MPU/ASIC [E]
Silicide thickness for Bulk MPU/ASIC (nm)
[L]
Contact silicide sheet Rs for Bulk MPU/ASIC
( W /sq) [M]
STI depth bulk (nm) [O] Bulk
Trench width at top (nm) [P] Bulk
Trench sidewall angle (degrees) [Q} Bulk
Trench fill aspect ratio - Bulk [R] Bulk
Equivalent physical oxide thickness for
FDSOI MPU/ASIC Tox (nm) for Metal Gate 0.5 0.5 MPU
[A, A1, A2]
Gate dielectric leakage at 100°C (A/cm 2 )
3.3E+03 3.7E+03 MPU
FDSOI High-performance [B, B1, B2]
Metal Gate Workfunction for FDSOI
MPU/ASIC | f m - E i | (eV)| NMOS/PMOS +/- 0.15 +/- 0.15 MPU
[S]
Mobility enhancement factor for FDSOI
1.04 1.04 MPU
MPU/ASIC [E]
Effective ballistic transport factor for FDSOI
1.15 1.28
MPU/ASIC [T]
Si thickness FDSOI (nm) [U] 3.3 3 MPU
Silicide thickness for FDSOI MPU/ASIC
13 12
(nm) [L]
Contact silicide sheet Rs for FDSOI
12.1 13.3
MPU/ASIC ( W /sq) [M]
Trench fill aspect ratio - FDSOI [W] 0.6 0.6 MPU
Equivalent physical oxide thickness for multi-
gate MPU/ASIC T ox (nm) for metal gate [A, 0.6 0.6 0.5 0.5 0.5 0.5 0.5 MPU
A1, A2]
Gate dielectric leakage at 100°C (nA/µm)
1.0E+03 1.1E+03 1.2E+03 1.4E+03 1.6E+03 1.8E+03 2.2E+03 MPU
muti-gate High-performance [B, B1, B2]
Metal Gate Workfunction for multi-gate
midgap midgap midgap midgap midgap midgap midgap MPU
MPU/ASIC [S]
Mobility enhancement factor for multi-gate
1.4 1.04 1.04 1.04 1.03 1.03 1.03 MPU
MPU/ASIC [E]
Effective ballistic transport factor for multi-
gate MPU/ASIC [T] 1.37 1.53 1.67 1.87 1.99 1.97 2.11
Si thickness for multi-gate (nm) [U] 6.5 6 5.5 4.5 4 3 2.5 MPU
Maximum allowble parasitic series
resistance for Multi-Gate NMOS MPU/ASIC 85 70 65 65 60 55 50
x width (( W-m m) [G]
Silicide thickness for Multi-Gate MPU/ASIC
13 12 11 10 8 7 7
(nm) [L]
Contact silicide sheet Rs for Multi-Gate
12.1 13.3 14.8 16.7 19.0 22.2 22.2
MPU/ASIC ( W /sq) [M]
Physical gate length low operating power
14 13 11 10 9 8 7 Low Power
(LOP) (nm)
Equivalent physical oxide thickness for bulk
low operating power T ox (nm) for 1.5E20- LOP
doped Poly-Si [A, A1, A2]
Equivalent physical oxide thickness for bulk
low operating power Tox (nm) for metal gate LOP
[A, A1, A2]
Table 71a and b Thermal and Thin Film, Doping and Etching Technology Requirements
Long-term
Year of Production 2014 2015 2016 2017 2018 2019 2020 Driver
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14 DRAM
MPU/ASIC Metal 1 (M1) ½ Pitch for
Gate dielectric leakage at 100°C
LOP
bulk(A/cm 2 ) LOP [B,B1, B2]
(nm)(contacted)
Metal Gate Workfunction for Bulk low
LOP
operating power |E c,v - f m | (eV) [S]
Equivalent physical oxide thickness for
FDSOI low operating power Tox (nm) for 0.8 0.8 0.7 LOP
metal gate [A, A1, A2]
Gate dielectric leakage at 100°C for FDSOI
7.1E+01 7.7E+01 2.3E+02 LOP
(A/cm 2 ) LOP [B,B1, B2]
Metal Gate Workfunction for FDSOI LOP
midgap midgap midgap midgap midgap midgap midgap LOP
[S]
Equivalent physical oxide thickness for multi-
gate low operating power Tox (nm) for metal 0.8 0.8 0.7 0.7 0.7 0.7 0.7 LOP
gate [A, A1, A2]
Gate dielectric leakage at 100°C for multi-
7.1E+01 7.7E+01 1.8E+02 2.0E+02 2.2E+02 2.5E+02 2.9E+02 LOP
gate (A/cm 2 ) LOP [B,B1, B2]
Metal Gate Workfunction for multi-gate LOP
midgap midgap midgap midgap midgap midgap midgap LOP
[S]
Physical gate length low standby power
18 16 14 13 11 10 9 LSTP
(LSTP) (nm)
Equivalent physical oxide thickness for bulk
low standby power Tox (nm) for 1.5E20-
doped Poly-Si [A, A1, A2]
Equivalent physical oxide thickness for bulk
low standby power Tox (nm) for metal gate LSTP
[A, A1, A2]
Gate dielectric leakage at 100°C for bulk
LSTP
(A/cm 2 ) LSTP [B, B1, B2]
Metal Gate Workfunction for Bulk LSTP
MPU
|E c,v - f m | (eV) [S]
Equivalent physical oxide thickness for
FDSOI low standby power Tox (nm) for 1.1 1.1 1.1 1.0 1.0 0.9 0.9 LSTP
metal gate [A, A1, A2]
Gate dielectric leakage at 100°C for FDSOI
5.6E-02 6.3E-02 7.1E-02 7.7E-02 8.3E-02 9.1E-02 1.0E-01 LSTP
(A/cm 2 ) LSTP [B, B1, B2]
Metal Gate Workfunction for FDSOI and
multi-gate LSTP | f m - E i | (eV)| -/+ 0.1 -/+ 0.1 -/+ 0.1 -/+ 0.1 -/+ 0.1 -/+ 0.1 -/+ 0.1 MPU
NMOS?PMOS [S]
Equivalent physical oxide thickness for multi-
gate low standby power Tox (nm) for metal 1 0.9 0.8 0.8 0.8 0.8 0.8 LSTP
gate [A, A1, A2]
Gate dielectric leakage at 100°C for multi-
6.0E-02 6.5E-02 7.5E-02 8.0E-02 8.6E-02 1.0E-01 1.3E-01 LSTP
gate (A/cm 2 ) LSTP [B, B1, B2]
Thickness control EOT (% 3 s ) [X] <±4 <±4 <±4 <±4 <±4 <±4 <±4 MPU/ASIC
Poly-Si or Metal Gate electrode thickness
22 20 18 16 14 12 12 MPU/ASIC
(approximate) (nm) [Y]
Trench dielectric maximum film stress TBD TBD TBD TBD TBD TBD TBD Bulk
Reduction in dopant segregation (%) TBD TBD TBD TBD TBD TBD TBD Bulk
Allowable Vt shift from charge in dielectric
10 10 10 10 10 10 10 MPU/ASIC
(mV) [AG]
Allowable interfacial charge in high k gate
2.0E+11 2.0E+11 2.0E+11 2.2E+11 2.2E+11 2.4E+11 2.4E+11 MPU/ASIC
stack (cm -2 )[AH]
Allowable bulk charge in high k gate stack
8.9E+17 8.9E+17 8.9E+17 1.1E+18 1.1E+18 1.3E+18 1.3E+18 MPU/ASIC
(cm-3) [AI]
Allowable bulk charge in high k gate stack
40.5 40.5 40.5 49.0 49.0 60.5 60.5 MPU/ASIC
(ppm) [AI]
Allowable critical metal impurity level in
4.1 4.1 4.1 4.9 4.9 6.1 6.1 MPU/ASIC
high k dielectric (ppm) [AJ]
* Refer to supplemental material worksheets, 2003 Contact Rs and 2003 RsXj online for a more complete description of the modeled devices.
ons exist, and are being optimized Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known
Interim solutions are known
Manufacturable solutions are NOT known
Footnotes
[E] Bulk/FDSOI/DG - Long channel Electron Mobility Enhancement Factor, representing the enhancement in peak electron mobility in NMOS devices.
[I] Contact Junction Depth = 1.1*Physical Gate Length (with a range of ±33%) for Bulk devices. Junction depths for NMOS and PMOS are the same
[M] Contact silicide sheet resistance: assumes 16 µ W -cm silicide resistivity for NiSi.
[P] Assumes a minimum trench width equal to the MPU half-pitch.
[Q] Assumes that the trench width is reduced by no more than half of the top dimension.
[R] Assumes a mask thickness equal to half of the DRAM half-pitch adds to the trench depth in the substrate
[T] Ballistic enhancement factor footnote
[W] Based on a trench depth equal to the FDSOI thickness
[X] From Modeling of Manufacturing Sensitivity and of Statistically Based Process Control [4] Requirements for 0.18 micron NMOS device.
[Z] Bias is defined as the difference between the printed gate length and the final post-etch gate length.
[AD] 15% dense-iso CD budget is a combination of measurements from Etch, Lithography and Metrology.
[AH] Assumes that all of the charge is at the Si-gate dielectric interface, i.e., there is no bulk charge and no charge at an SiO 2 /high k interface
References
Dielectrics,‖ SPIE Proc., Vol. 3506, 1998, 253.
[3] C.M. Osburn, J.Y. Tsai and J. Sun, “Metal Silicides: Active Elements of ULSI Contacts,” J. Electronic Mater.,
Vol. 25(11), 1996, 1725.
Footnotes
[A] This number represents the effective thickness of the dielectric alone, at the maximum operating frequency of the technology, without substrate or
electrode effects. This parameter is determined through an electrical measurement of capacitance corrected for substrate (quantum) and electrode
(depletion) effects. The electrical, or capacitance equivalent, thickness (CET), in contrast to EOT, includes a contribution due to gate (Poly-Si)
depletion. A more detailed discussion of the measurement of EOT is on a separate workbook page of the linked file online at http://public.itrs.net.
Values for EOT were derived from the electrical device requirements (CET) as given in the PIDS chapter. MASTAR and other simulations were used to
subtract the substrate dark space and gate depletion for the prescribed channel configuration, doping and voltage at each node.
[A1] EOT values are reported for alternate gate electrode options: Poly-Si whose doping at the dielectric interface is 1 x 10 20 /cm 3 (light doping), 1.5 x
10 20 /cm 3 (the nominal case) and 3 x 10 20 /cm 3 (representing aggressive doping) and Metal gate. In approximate terms, Poly depletion for 1.5E20
doping was about 0.4 nm, and it was about 0.3 nm for 3e20. Thus, increasing Poly-Si doping from 1E20 to 3E20 increases the allowable EOT by 0.2
nm. Similarly, metal gates can use EOTs that are about 0.4 nm thicker than 1.5E20-doped Poly-Si. Due to numerous practical difficulties at the high-
k/Poly-Si interface, it is envisioned that many companies may want to introduce metal gate at the same time, or maybe even before, high k dielectrics are
introduced.
[A2] The color coding of each node considers the ability of known dielectrics to meet gate leakage, uniformity, and reliability requirements. For all
three applications (HP, LOP, and LSTP), the gate leakage requirements, in this scenario, can no longer be met by optimized oxynitride (which is taken to
have a leakage of 1/30 that of SiO2); hence high-k dielectric is needed. Based on early announcements and encouraging results with high-k dielectrics
and poly-Si gates, particularly at 1 nm EOT and above, (many of which employed a layered SiON-HfSiON system), were colored yellow. All other high
k dielectrics, i.e., those thinner than 1 nm and those requiring metal gates, are colored red because a manufacturing solution to all known problems is
not at hand
[B] The gate leakage, specified at 100°C, is derived from the transistor sub-threshold leakage at room temperature. This device leakage is specified in
the PIDS chapter section on Logic—High Performance and Low Power Technology Requirements as the off-state leakage (excluding the junction and
the gate leakage components) at room temperature. The gate leakage specification (at is taken to be multiple of the (room temperature) device
sub-threshold leakage spec. The multiplier includes two factors: The first, or Initial Factor, accounts for the fact that not all transistors on real chips
are not the low Vt (high leakage but high current drive; hence, fast) transistors specified in the PIDS table. Most transistors on HP chips are higher Vt,
lower leakage and current drive. The factor of 0.1 is our estimate of a reasonable number to use to take account of these multiple transistor in HP.
Conversely in LOP and LSTP chips, most of the devices are the lower Vt; hence the initial factor is 1. The second factor, High T Factor, is used to
account for the fact that the device sub-threshold leakage, which is specified at room temperature, rapidly increases with operating temperature. For
high performance devices, which operate at high temperatures, this factor was
taken as 10; for low operating and low standby power applications, where the temperature is lower, the factors were taken as 5 and 1, respectively.
Models are provided online as linked supplemental files, in the electronic version of this chapter at http://public.itrs.net. Tying the gate leakage to the
device sub-threshold leakage in this way was assumed to be satisfactory from a circuit’s operation standpoint, but it should be noted that not all design
approaches (companies) will allow such a high gate leakage. The gate leakage is measured on the minimum nominal device, and the specification is
taken to apply to all transistor bias configurations, that is, both when Vg = Vs = 0 and Vd = Vdd as well as when V s =V d ≈ 0 and V g = V dd .
[B1] The areal gate leakage is modeled as the allowable gate leakage divided by the physical gate length. However, it should be noted that the total gate
leakage is the sum of three leakage components: 1) leakage between the source and the gate in the gate-source overlap area, 2) leakage between the
channel and the gate over the channel region, and 3) leakage between the gate and the drain in the gate-drain overlap area. The magnitude of each of
these three components will depend on the gate, source, and drain biasing conditions. The color coding of leakage nodes is based on UTQUANT
simulations of tunneling current from an inversion channel to the gate for the mid-point EOT. (These simulation results are given in a separate
worksheet file online at http://public.itrs.net.) It should be emphasized that the tunneling current density will generally be much higher between the
junction and gate than between an inversion channel and gate. Thus these simulations represent a best case (lowest leakage) condition, wheractor, High
T Factor, is used to account for the fact that the device sub-threshold leakage, which is specified at room temperature, rapidly increases with operating
temperature. For high performance devices, which operate at high temperatures, this factor was
[B2] The unmanaged gate leakage power is the total static chip power that would occur if all the devices on a chip had gate leakage equal to the
maximum allowable value. Power management will require the extensive use of power reduction techniques, such as power-down or multiple Vt devices
to achieve an acceptable static power level.
[C] The gate electrode workfunctions come from the PIDS device design. In bulk devices, the electrode workfunction and the channel doping jointly
control device threshold, which is selected to maximize I on , while meeting the I off specification. In addition, the doping affects both short channel
effects and channel mobility and, thus, requires an optimization. The PIDS design shows that workfunctions 0.1eV below Ec and 0.1 eV above Ev are
best for NMOS and PMOS respectively. The requirement stated in the table is for the workfunciton to be within 0.2eV of the Silicon band edge. Even
though there is some leeway in the choice of the gate workfunctions, the workfunction itself needs to be controlled to within about 10 mV 3 s , since that
it becomes a component of the device threshold voltage tolerance.
[D] The channel doping for bulk CMOS devices comes from the PIDS device design. The doping, along with the gate dielectric thickness and the
junction depth control short channel effects and thus must be co-optimized. The reduced short channel effects associated with higher channel doping
must also be traded off for reduced channel mobility and increased tunnel leakage. The values presented in the table reflect a representative co-
optimization. Channel doping above 5 x 10 18 /cm 3 was colored yellow because of concerns about excessive band-to-band tunneling leakage in
junctions. Silicon thickness for all multi-gate nodes was colored red, where control of the thickness, sidewall angle, and channel mobility have not been
demonstrated.
[E] Bulk/FDSOI/DG - Long channel Electron Mobility Enhancement Factor, representing the enhancement in peak electron mobility in NMOS devices.
[F] Xj at Channel (Extension Junction) as given by the PIDS Bulk device designs (with a range of 25%). In earlier roadmaps Xj was taken as
0.55*Physical Gate Length; however since CET is no longer scaling with gate length, extension junction scaling has become more aggressive. Junction
depths for NMOS and allowable parasitic
[G] [G] The maximumPMOS are the same. series resistance for NMOS devices comes from the PIDS device design. The allowable resistance for PMOS
is taken to be 2.2 times the NMOS values. The maximum drain extension sheet resistance is modeled by allocating 15% of the allowable source and
drain parasitic resistances to the drain extensions. (See the worksheet labeled RsXj in the linked file of the electronic version of this chapter, online at
http://public.itrs.net). The drain extension sheet resistance value must be optimized together with the contact resistance and junction lateral abruptness
(which effects spreading resistance), in order to meet the overall parasitic resistance requirements. This is a relatively crude model and the resultant
sheet resistance values should only be used as a guide.
[H] Channel abruptness in nm per decade drop-off in doping concentration) = 0.11 * Physical Gate Length (nm – based on Short Channel effect.[1]
This lateral abruptness is consistent with a 3 decade fall off of doping over the lateral extent of the junction, which is taken to be 60% of the vertical
junction depth. Note discussion of the integration choices in the supplemental material online at http://public.itrs.net.
[I] Contact Junction Depth = 1.1*Physical Gate Length (with a range of ±33%) for Bulk devices. Junction depths for NMOS and PMOS are the same
[J] Spacer thickness (width) is taken as the same as the Contact Junction Depth, namely 1.1 x Lgate,, for bulk devices.. Validity established using
response surface methodology in ―Response Surface Based Optimization of 0.1 µm PMOSFETs with Ultra-Thin Oxide Dielectrics‖ . For FDSOI and
Multi-gate devices, the spacer width was taken to be half that value, i.e., 0.55 x Lgate . (See the worksheet labeled RsXj in the linked file of the electronic
version of this chapter, online at http://public.itrs.net).
[K] Silicon consumption is based on half the contact junction depth, for bulk devices. For advanced fully depleted and multi-gate devices, having
elevated contacts, the silicide thickness is such that the silicide/silicon interface is coplanar with the channel/gate dielectric interface. The silicon
consumption is equal to the added silicon thickness.
[L] Silicide thickness is based on the silicon consumption, which is taken to be 1/2 of the Contact Xj midpoint to avoid consumption-induced increase in
contact leakage for bulk devices. Less than half of the junction can be consumed.[3] For fully-depleted and multi-gate devices, having elevated contact
structures, the silicide thickness is that thickness yielded by consumption of the contact silicon added above the plane of the gate dielectric/channel
interface. For cobalt and titanium di-silicide layers this silicide thickness is nominally equal to the silicon consumed. For nickel mono-silicide the
silicide thickness is equal to 2.22/1.84´ of the silicon consumed. In the table we have assumed NiSi implementation. (See the worksheet labeled RsXj in
[M] Contact silicide sheet resistance: assumes 16 µ W -cm silicide resistivity for NiSi.
[N] The Si/Silicide maximum interfacial contact resistivity values were calculated assuming that 100% of the PIDS total allowed MOSFET Source/Drain
resistance is allocated to the contact resistivity. It further assumes that the transistor contact length is taken to be twice the MPU half pitch, where length
is in the direction of current flow. Since the PIDS allocation is in terms of Rs W, the equation for the contact resistivity rhoc is: rhoc = Rs W M.
These values should be appropriately modified if different transistor contact lengths are assumed. (See the worksheet on Contact Rs in the linked file of
the electronic version of the chapter online at http://public.itrs.net). Note that this contact resistivity is the maximum allowable and cannot be used for
real devices. The contact resistivity was colored red below 9x10 -8 ohm-cm 2 and white above 1x10 -7 ohm-cm 2 . The values of contact resistivity, drain
extension sheet resistance and drain extension lateral abruptness must be co-optimized in order to meet the overall parasitic resistance requirements.
[O] Assumes that the trench depth for bulk is proportional to the contact junction depth plus depletion width into the well. The constant of
proportionality was determined by setting the 2003 node value equal to 400 nm.
[P] Assumes a minimum trench width equal to the MPU half-pitch.
[Q] Assumes that the trench width is reduced by no more than half of the top dimension.
[R] Assumes a mask thickness equal to half of the DRAM half-pitch adds to the trench depth in the substrate
[S] In fully-depleted and multi-gate devices, the gate workfunction is the prime determinant of device threshold; accordingly values near midgap are
more appropriate. The scenario depicted in the table is one which seeks to maintain the same workfunction over time for a given device type and to
minimize the number of different workfunctions needed for different applications. Dual workfunction gates are best served with workfunctions that are
+/- 0.15 eV from midgap for NMOS and PMOS respectively (-/+ 0.1eV for LSTP applications). Several applications, including some low cost ones, can
be satisfied with a single midgap workfunction for both NMOS and PMOS. As with gate electrodes for bulk devices, workfunction control of 10 mV, 3 s
is required.
[T] Ballistic enhancement factor footnote
[U] Si thicknesses for FDSOI and multi-gate devices was based on PIDS device optimization to control short channel effects. Although some company-to-
company differences in the final optimized nominal thickness is expected, the tolerance on the final thickness is +/-10%. The colorization of the FDSOI
thickness is based on thinning the material specified in the Starting Materials tables (in Tables 70a and 70b), which are controlled to +/- 5%, to the final
thicknesses required by PIDS devices, which require a +/- 10% tolerance, assuming that the thinning process introduces no additional variation in
thickness.
[V] The thickness of the elevated junctions in FDSOI and in Multi-gate was taken as equal to the Physical Gate Length. In this model, the entire
thickness of the elevated junction is consumed to form silicide. By adjusting this thickness tradeoffs can be made between silicide sheet resistance and
lateral parasitic junction-to-gate capacitance.
[W] Based on a trench depth equal to the FDSOI thickness
[X] From Modeling of Manufacturing Sensitivity and of Statistically Based Process Control [4] Requirements for 0.18 micron NMOS device.
[Y] Gate thickness is taken as two times the physical gate length. Thicker gates reduce gate series resistance, but at the expense of increased topography
and aspect ratio .
[Z] Bias is defined as the difference between the printed gate length and the final post-etch gate length.
[AA] The total gate length 3 s variation encompasses all random process variation including point to point on a wafer, wafer to wafer, and lot to lot
variations. It excludes systematic variations such as lithography proximity effects, and etch variations such as CD bias between densely spaced and
isolated lines. This total variability is taken to be less than or equal to 12% of the final feature size. A conventional MOS structure is the basis for these
calculations. MOS transistor structures that vary in any way from the conventional structure (e.g. Vertical MOS transistors) will have different technical
challenges and will not fall within these calculations. The data is computed taking into account lithographic errors during resist patterning and
combined etch errors due to both resist trim and gate etch.
[AB] The allowable lithography variance s 2 L is limited to 3/4 of the total variance, s 2 T of the combined lithography and etch processes. It is further
assumed that the lithographic and etch processes are statistically independent and therefore that the total variance is the sum of the etch and
lithography variances. This implies among other things that the printed features in the resist have vertical wall profiles and be sufficiently thick to with-
stand the etch process without loss of dimensional fidelity. Refer to the Etch supplemental file in the electronic version of this chapter online at
http://public.itrs.net.
[AC] It is assumed that the resist trim and gate etch processes are statistically independent and therefore that the respective variances, s 2 , of the two
processes are additive. 1/3 of the combined trim-etch variance is allocated to the trim process, with the remaining 2/3 allocated to the etch process.
[AD] 15% dense-iso CD budget is a combination of measurements from Etch, Lithography and Metrology.
[AE] It is important that some dielectric remains after the gate etch clean step. Between technology nodes the dielectric thickness decreases and there is
an onset of using high- k materials (2008) to replace the gate dielectric. Both advances represent challenges to ensure there is an amount of remaining
dielectric and the ability to measure the remaining material.
[AF] Profile can be a major contributor to etch errors (see inset). Accurate measurement of vertical profiles remains difficult. Long term, the effect of
edge roughness on device performance needs to be addressed and methodology of the measurement determined.
[AG] Values taken from SEMATECH working documents. Charge includes centers that are initially charges or centers which trap/detrap charge during
long term stressing.
Gate error produced @ 89 degrees = 3.5 nm
Gate
65nm 53nm 45nm 37nm 32nm 30nm 25nm
Length:
% error = 5.4 6.6 7.8 9.4 10.9 11.7 14
89
Error Gate Length
[AH] Assumes that all of the charge is at the Si-gate dielectric interface, i.e., there is no bulk charge and no charge at an SiO 2 /high k interface
[AI] Assumes: i) a single (high-k) dielectric with uniformly-distributed charge, and ii) a relative dielectric constant of 4 times that of SiO 2 . Conversion
of the bulk concentrations to units of ppm in the dielectric assume the metal atom density in the high k dielectric is the same as that of Si in SiO 2 ,
namely 2.2 x 10 22 /cm 3 .of the charge (and traps) in the high k are due to intrinsic bonding defects and that 10% can be due to metallic impurities. The
[AJ] Assumes that 90%
critical metals are expected to be: a) transition metals with low or mid-gap d-states, including Ti, Sc, Nd, V, Ta, Nb, b) transition metals having more d
electrons than the high k metal, c) Cu, Ag, Ag, and d) radioactive isotopes of high k metals.
[1] Y. Taur, “25 nm CMOS Design Considerations,”References Technical Digest, IEEE, December 1998,
IEDM 1998,
789–792.
[2] A. Srivastava and C.M.Osburn, “Response Surface Based Optimization of 0.1 µm PMOSFETs with Ultra-Thin
Dielectrics,‖ SPIE Proc., Vol. 3506, 1998, 253.
[3] C.M. Osburn, J.Y. Tsai and J. Sun, “Metal Silicides: Active Elements of ULSI Contacts,” J. Electronic Mater.,
Vol. 25(11), 1996, 1725.
[4] P. Zeitzoff and A. Tasch, “Modeling of Manufacturing Sensitivity and of Statistically Based Process Control
Requirements for 0.18 micron NMOS device,” Characterization and Metrology for ULSI Technology: 1998
International Conference, D.G. Seiler, et al. eds., 73.
Measurement of Equivalent Oxide Thickness
The equivalent oxide thickness (EOT) is the thickness of silicon dioxide that would produce the same capacitance-voltage curve as that
obtained from the alternate dielectric system. Because the dielectric constant of the material is seldom known with any certainty, the EOT
must be determined from an electrical capacitance measurement. The EOT is obtained from the gate dielectric capacitance (C diel) which is
the capacitance of the dielectric alone, at the maximum operating frequency of the technology, without substrate or electrode effects. The
EOT is related to Cdiel as EOT » (e0 eSiO2 Agate)/ Cdiel, where e0 is the permittivity of free space, eSiO2 is the relative dielectric constant of silicon
dioxide (» 3.9), and Agate is the gate area. The intent is to provide a metric that does not depend on other quantities, e.g. the type of
electrode, the electrode work function, or the substrate doping. The EOT is different than the Capacitance
Effective Thickness (CET). The CET is an effective thickness that depends on other quantities such as the type of electrode, the electrode
work function, the substrate doping, and the gate voltage of measurement. The CET is derived from the relationship CET(V) » (e0 eSiO2 Agate)/
C(V), where C(V) is the capacitance at a bias voltage, V. Both the EOT and CET must be determined from an electrical capacitance
measurement. However, neither the measurement of capacitance nor the analysis of the measurement data is straightforward.
The measurement of capacitance of an ultra-thin dielectric is complicated by the presence of leakage currents through the dielectric [1-9].
When appreciable current flows through the dielectric, voltage drops occur along the series resistances of the gate electrode and of the
substrate. The gate dielectric can be modeled as a voltage dependent resistor in parallel with a capacitor. The gate electrode and substrate
act as distributed series resistance. When measuring FETs, further complications associated with the resistance of the channel are also an
issue. As a result of these distributed parasitic resistances, the measured value of the parallel capacitance depends on these resistances
(sample geometry) as well as measurement frequency. The references below reflect some of the recent attempts to more precisely extract
the true capacitance-voltage curve. Typically, to compensate for these parasitic resistances, the DC I-V characteristics are used to correct the
C-V data, the capacitance is measured as a function of frequency, or a test structure is used in which the parasitic resistances are negligible.
Once the capacitance has been determined, an even greater challenge is the task of correcting the data to eliminate the effects of gate
dopant depletion and substrate channel quantum effects [10-12]. At present different correction algorithms are used to calculate the impact of
quantum effects in the substrate. As a result, slightly different values of EOT will be extracted depending on the approach and software used
[10]. EOT values are used as inputs to device simulation programs, so it is important that the quantum corrections used to extract EOT be
consistent with those used to simulate device performance. The use of two different device simulators may well require the use of two
different values of EOT for the same physical dielectric in order to accurately model device currents.
References
[1]. E. M. Vogel and G. A. Brown, “Challenges of Electrical Measurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor
Devices,” in Characterization and Metrology for ULSI Technology: 2003 International Conference, The American Institute of Physics (2003).
[2]. J. Schmitz, F. N. Cubaynes, R. J. Havens, R. de Kort, A. J. Scholten, and L. F. Tiemeijer, “RF Capacitance-Voltage Characterization of
MOSFETs With High Leakage Dielectrics,” IEEE Elec. Dev. Lett. 24(1), 37-39 (2003).
[3]. D. W. Barlage, J. T. O‟Keeffe, J. T. Kavalieros, M. M. Nguyen, and R. S. Chau, “Inversion MOS capacitance extraction for high-leakage di-
electrics using a transmission line equivalent circuit,” IEEE Elec. Dev. Lett. 21, 454–456 (2000).
[4]. H.-T. Lue, C. Y. Liu, and T. Y. Tseng, “An improved two-frequency method of capacitance measurement for SrTiO3 as high-k gate
dielectric,” IEEE Elec. Dev.Lett. 23, 553-555 (2002).
[5]. A. Nara, N. Yasuda, H. Satake, A. Toriumi, “Applicability limits of the two-frequency capacitance measurement technique for the thickness
extraction of ultrathin gate oxide,” IEEE Trans. Semi. Manuf. 15(2), 209-213 (2002).
[6]. K. Ahmed, E. Ibok, G. C.-F. Yeap, Q. Xiang, B. Ogle, J. J. Wortman, J. R. Hauser, “Impact of Tunnel Currents and Channel Resistance on
the Characterization of Channel Inversion Layer Charge and Polysilicon-Gate Depletion of Sub-20-Å Gate Oxide MOSFET‟s,” IEEE Trans.
Electron Devices, 46(8), 1650 (1999).
[7]. W.K. Henson, K.Z. Ahmed, E.M. Vogel, J.R. Hauser, J.J. Wortman, R.D. Venables, M. Xu, and D. Venables, “Estimating Oxide
Thickness of Tunnel Oxides Down to 1.4 nm on MOS Capacitors,” IEEE Electron Device Lett., 20(4), 179 (1999).
[8]. K.J. Yang and C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, 46(7), 1500
(1999).
[9]. E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, “Limitations of Conductance to the Measurement of the Interface State
Density of MOS Capacitors with Tunneling Gate Dielectrics,” IEEE Trans. Electron Devices, 47(3), 601 (2000).
[10]. C. A. Richter, A. R. Hefner, and E. M. Vogel, “A Comparison of Quantum-Mechanical Capacitance Voltage Simulators,” IEEE Electron
Device Lett. 22(1), 35 (2001).
[11]. J.R. Hauser and K. Ahmed, “Characterization of Ultra-Thin Oxides Using Electrical C-V and I-V Measurements,” in
Characterization and Metrology for ULSI Technology: 1998 International Conference, The American Institute of Physics (1998).
[12]. S.-H. Lo, D.A. Buchanan and Y. Taur, “Modeling and Characterization of Quantization, Polysilicon Depletion, and Direct
Tunneling Effects in MOSFETs with Ultrathin Oxides," IBM J. Research and Development, 43, 327 (1999).
7
1994
5
1997
7
1994
5
1997
3 Actual Trend
1999
1 2001
0.8
2003
0.6
0.4
2005
300 100 80 60 40 20
Technology Node
Comparison of EOT projections from the 1994-2005 roadmaps
The extraordinarily rapid decline from 1994-2000 has been replaced with a much slower scaling
Gate leakage of SiO2 dielectric was calculated using the UT-QUANT model over a range of oxide thickness and
power supply voltage as shown in the figure below. Expected oxide leakage was then extracted for the EOT-Vdd
combination for each node and for each application. The leakage of oxynitride was assumed to be 1/30 of the
oxide leakage. Larger reductions have been reported, but the experience base suggests that a reduction by 30 is
as much as can be obtained without sacrificing channel mobility.
108
0.4 nm
6
10
104
102
100
10-2
10-4 2.3 nm
10-6 UTQUANT Simulations
(from NMOS Inversion Layer)
10-8
0 0.2 0.4 0.6 0.8 1 1.2
Voltage (V)
The figure below compares oxide and oxynitride leakage versus the ITRS gate leakage specification for bulk devices
5
10
4
10
3
HP
10
2
10
LOP
1
10
0
10
-1
Requirement
10
LSTP
-2
10 Solid - Oxide (Simulation)
Dash - Oxide/30 (Oxynitride)
-3
10
80 70 60 50 40 30
Technology Node (nm)
(from NMOS Inversion Layer)
-8
10
0 0.2 0.4 0.6 0.8 1 1.2
Voltage (V)
5
10
4
10
3
HP
10
2
10
LOP
1
10
0
10
-1
Requirement
10
LSTP
-2
10 Solid - Oxide (Simulation)
Dash - Oxide/30 (Oxynitride)
-3
10
80 70 60 50 40 30
Technology Node (nm)
When oxides or oxynitrides can meet the leakage specification and are > 1 nm thick, the node was coded white.
When a high k dielectric is needed (i.e., oxynitride cannot meet the leakage spec) or an oxynitrdies would be 1
nm or less, the node was coded red.
or bulk devices
Near-term
Year of Production 2005 2006 2007 2008 2009 2010 2011
MPU Physical Gate
32 28 25 22 20 18 16
Length (nm)
Bulk/FDSOI/DG -
Long channel
1.7 1.8 1.8 1.8 1.8 1.8 1.8
Electron Mobility
Enhancement Factor
Saturation Velocity
1 1 1 1.1 1.1 1.1 1.1
enhancement factor
PIDS Idat
enhancement-BULK
1.09 1.09 1.08 1.1 1.1 1.12 1.11
PIDS Idat
enhancement -FDSOI
1.06 1.06 1.06 1.06
PIDS Idat
enhancement -DG 1.05
1.9 Short Channel Long Channel
1.8 1.15
Bulk DG, kµ=1.8
IDsat improvement
FDSOI
1.1
IDsat improvement due to Mobility
1.7 DG
1.05
1.6 Bulk, kµ=1.7
1
1.5 1 10 100
MPU Gate Length (nm)
1.4
1.3
1.2
Bulk
FDSOI
1.1
DG
1
1 10 100 1000 10000
MPU Gate Length (nm)
Long-term
2012 2013 2014 2015 2016 2017 2018 2019 2020
14 13 11 10 9 8 7 6 5
1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8
1.1 1* 1* 1* 1* 1* 1* 1* 1*
1.05 1.05 1.04 1.04
1.04 1.05 1.04 1.04 1.04 1.03 1.03 1.03 1.03
1.16
Saturation Current Enhancement Factor
Achievable with Silicon
1.14
1.12
1.1
1.08 Bulk, HP2005
1.06
1.04
1.02
DG, HP2020
1
1 1.5 2 2.5
Electron Mobility Enhancement Factor
Driver
MPU
* : from 2013, velocity enhancement factor is included into Ballistic enhancement factor kbal (see PIDS table)
Shallow Trench Isolation
Definition of Terms
width
recess
rtop
depth
rbottom q
wbottom
Geometrical Models:
W bottom > width/2 : the bottom of the trench should be over 50% of the top
rtop = rbottom = 0.1width ; for the example the radii of the top and bottom corners should be ~ 10% of the trench width
q= 90 - arcsin{(width-W bottom)/2depth}
Recess < 0.1 width ; for the example, the recess should be limited to about 10% of the trench width
Mask Layer Thickness (Prior to tranch fill, post CMP) taken as 0.5 x Width
Aspect Ratio (for trench fill) = (Trench Depth + Masking Layer Thickness)/Width
Electrical Models (Bulk):
Trench Depth = {Contact Junction Depth + Depletion region width, for 1e17-doped wel} x Multiplication Factor
Multiplication Factor Chosen (~2) to match depth to current practice, I.e., 400 nm deep for 90 nm technology
Electrical Models (SOI):
Trench Depth = Contact Junction Depth = 1.1 x Lgate
Discussion of Trench Requirements
In the fabrication of shallow trench isolation, the top corner of the active region is generally exposed by HF etching of pad and
sacrificial oxides prior to the growth or deposition of the gate dielectric. The gate conforms to this corner, forming a region of
higher electric field and potential high defectivity. This can be thought of as a transistor in parallel with the bulk transistor, with a
lower threshold voltage and saturation current. This leads to a „hump‟ in the Id/Vg characteristics and higher subthreshold
leakage. For this reason the top corner of the STI trench is rounded, usually by oxidation prior to the deposition of the isolation
oxide. Increasing the radius of curvature of this corner increases the Vt of the parasitic transistor and decreases the magnitude
of this „hump‟. However radius of curvature must be decreased in order to scale the isolation length.
The magnitude of the parasitic drain current also depends on the recession of the field oxide adjacent the active edge, since
that will determine the crossection of the edge „transistor‟. Therefore as the radius of curvature (ROC) is scaled down with the
isolation width, so is the recession of the field oxide, resulting in at least partial mitigation of the degradation expected because
of decrease of the radius of curvature. The recession of this oxide depends on the „hardness‟ of the deposited isolation oxide
against HF dipping, and the thickness of the pad and sacrificial oxide, which are process design choices. Presumably the
current in the parasitic transistor is proportional to the extent of the isolation oxide recess (if it‟s the same as ROC), whereas the
current depends exponentially upon the inverse of ROC, which represents a scaling problem.
The degree to which the subthreshold leakage is affected by the parasitic transistor also depends on the substrate voltage.
For example at Vsub=0, 10 nm radius of curvature of the top STI corner (ROC), and 30 nm recess of the field oxide below the
surface of the silicon, the subthreshold leakage would be affected by less than half an order of magnitude by the corner,
whereas at Vsub = -2V the subthreshold leakage is increased by almost a factor of 1000 from the value without the corner.
Although this problem exists, it can be attacked by processing tricks to make the effective dielectric thickness over the corner
greater than the gate dielectric thickness in order to prevent the parasitic transistor from turning on earlier than the design FET.
For this reason, we think the problem is manageable.
References:
Corner rounding:
1. S.Matsuda, T. Sato, H. Yoshimura, Y. Takegawa, A. Sudo, I. Mizushima, Y. Tsunashima, and Y. Toyoshima, ""Novel Corner
Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Structure Transformation of Silicon", IEDM 1998, p137,
1998
2. M.Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, and I.-C. Chen, "Shallow Trench Isolation for Advanced
ULSI CMOS Technologies, IEDM 1998, p.133, 1998
Recession of field oxide:
1. K. Ohe, S. Odanaka, K. Moriyama, T. Hori, and G. Fuse, "Narrow Width Effects of Shallow Trench-Isolated CMOS with n+-
Polysilicon Gate", IEEE Trans. Electron Devices, Vol.36, No.8, P1110, 1989
2. E.H. Li, K.M. Hong, Y.C. Cheng, and K.Y. Chan, "The Narrow -Channel Effect in MOSFET's with Semi-Recessed Oxide
Structures", IEEE Trans. Electron Devices, Vol.37, N0.3, p.692, 1990
Boron Segregation:
1. J. Kim T. Kim, J. Park, W. Kim, B. Hong, and G. Yoon, "A Shallow Trench Isolation Using Nitric Oxide (NO)-Annealed Wall
Oxide to Suppress Inverse Narrow Width Effect", IEEE Electron DEvice Letters, vol.21, No.12, p.575, 2000
2.F.Arnaud and M.Bidaud, "Gate Oxide Process Impact on RNCE for Advanced CMOS Transistors", ESSDERC 2002, p.107,
2002
F. Nouri, G. Scott, M. Rubin, M. Manley, and P. Stolk, "Narrow Device Issues in Deep-Submicron Technologies-the Influence of
Stress, TED, and Segregation on Device Performance," ESSDERC 2000 pages 112-115
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