High density Thin Film Module by pzk16293

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									     High Density Pixel Detector Module using Flip Chip and Thin Film Technology

                          J. Wolf, P. Gerlach*, E. Beyne**, M. Töpper, L. Dietrich,
                          K.H. Becks*, N. Wermes*** , O. Ehrmann and H. Reichl

                   FhG-IZM, Gustav Meyer Allee 25, 13355 Berlin Germany
*    Bergische Universität-GHS Wuppertal, FB Physik, Gaußstr. 20, 42097 Wuppertal, Germany
                       ** IMEC, Kapeldreef 75, 3001 Leuven, Belgium
       *** Universität Bonn, Physikalisches Institut, Nussallee 12, 53115 Bonn, Germany
                                   e-mail: wolf@izm.fhg.de

                                                      Abstract
    For the ATLAS experiment at the planned Large Hadron Collider LHC at CERN hybrid pixel detectors are be-
ing built as innermost layers of the inner tracking detector system. Modules are the basic building blocks of the
ATLAS pixel detector. A module consists of a sensor tile with an active area of 16.4 mm x 60.4 mm, 16 read out
IC's, each serving 24 x 160 pixel unit cells, a module controller chip, an optical transceiver and the local signal
interconnection and power distribution busses. The dice are attached by flip-chip assembly to the sensor diodes and
the local busses.
In the following a module based on MCM-D technology will be discussed and prototype results will be presented.


Key words: MCM, thin film technology, flip chip, pixel detector

    I. Introduction                                              The focus of the MCM-D technology is to achieve
    In order to build large array pixel detectors one        high integration density with good frequency behavior
needs to construct easy to handle and manufacturable         in a cost effective process.
modules which can be used to put together to big de-            All interconnects between read out chips and sensor
tector systems, i.e. barrel detectors or end cap wheels.     substrate are formed by solder bumps.
Such as the pixel detector of the ATLAS project at the
European Lab for particle physics in Geneva. Diode-              II. Electrical Considerations
pixel-arrays can be fabricated in wafer size dimensions
(currently about 8 cm in length); read out chips have            In the LHC environment we have to deal with "me-
dimensions of about 1 cm². A natural (but not trivial)       dium" frequencies. But even for clock rates of 40 MHz
thing would be to use the silicon diode array as the basic   one has to take care that line capacitances and line
building block for a detector system. Several read out       resistances do not cause RC-line charging which may
                                                             slow down signal speeds quite considerably. In the
chips have to be flip chip bonded onto this module. For
                                                             higher frequency domain the interconnections must be
easy module interconnections the data lines, control
                                                             controlled-impedance transmission lines and should be
lines, and power distributions have to be connected to
                                                             terminated. The line cross sections have to be "large" to
the periphery of the module. To avoid complicated wir-       decrease DC and AC resistive losses. The power and
ing and different interconnection technologies, all lines    ground plane positioning in the layer stack becomes
are integrated onto the detector substrate. The data bus     important. A structure which is favorable for our appli-
as well as the power distribution bus are situated below     cation is a microstrip line configuration where the x-
the end-of-column logic of the FE-chips. Such a mod-         and y-signal lines are imbedded into a dielectric mate-
ule can be made using thin film technology (MCM-D)           rial with reference metal planes on top and/or bottom of
where the interconnections are formed by depositing          the structure. In such a MCM-D structure it is possible
dielectric materials and conductors onto a base substrate    to build a bus system with low cross talk between two
which is high-resistivity, active, fully depleted silicon.   parallel lines with fixed line width, thickness, and line
Photolithography, sputtering, electroplating, wet and        spacing.
dry etching are used to create the interconnections. The        For the ATLAS module a four Cu layer system for a
used conductor materials is copper and as dielectric         signal and power bus is situated below the end-of-
layer benzocyclobutene (BCB) is used.                        column logic of the front end (FE) chips within the
outermost 2 mm on both long sides of the sensor sub-             With this prototype project possible design rules
strate. A cross section of the 2 mm wide bus region is       have been studied. Firstly the resistive and capacitive
sketched in Figure 1. For copper lines of width w =          characteristics of various types of via connections have
20 m, thickness t = 2.2 m, with a line spacing s =           been evaluated. These via connections realize the link
30 m, a BCB dielectric medium with r = 2.7 and               between the silicon pixel cells and the flip-chip contact
thickness h = 8 m one computes for a microstrip line         pad. The various types of via connections that have
configuration a typical line capacitance of 1.2 pF/cm        been investigated may be classified in two basic types,
with a time of flight of about 55 psec/cm. The charac-       staggered and staircase, which are both shown in Fig-
teristic impedance is Zo 50         and the voltage cou-     ure 2.
pling to the neighbored line is estimated to be -20 dB.
For a 7 cm long line the signal attenuation is about
30 % [1].




                                                             Figure 2: Principle via connection test structures (left : stag-
                                                                        gered type, right : staircase type).


                                                                 Using four point measurements, average series re-
Figure 1: Cross section through the 2 mm wide bus region.    sistances of about 80 m and 140 m have been meas-
                                                             ured for the staggered and staircase type respectively.
    A first try towards a multi-chip module with inte-       The average capacitive coupling between adjacent via
grated bus structure for a pixel detector has been carried   structures, which are only 50 m apart, is about 30 fF.
out for the Very Forward Detector for DELPHI [2]. Ref.          The typ. Via-resistance (diam.: 25 µm) between 2
[3] describes in some detail mechanical, thermal, and        metal planes and 3 µm thick dielectric (BCB) layer is
electrical considerations. MCM packaging technology          2,5 m (see figure 3).
is described in [4].

 III. Technology - Results                                                      8

    To qualify the technology, co-operative research                            7
work has been set up in a prototype program with two                            6
                                                                ]




independent research and development centers IMEC in
                                                                Resistance [m




Leuven (Belgium) the Fraunhofer Institute for Reli-                             5

ability and Microintegration IZM in Berlin (Germany)                            4
and the universities in Wuppertal and Bonn.
                                                                                3


   A. Electrical Characterization                                               2


    The substrate used here was a 4 inch diameter sili-                         1

con wafer onto which 4 copper layers and intermediate                           0
                                                                                    10          20            30          40
BCB dielectric layers, with the parameters as used for
the above mentioned calculations, had been deposited.                                    Via diameter (mask) [µm]
Different test structures were implemented to determine
the electrical properties of the bus lines and the optimal   Figure 3: Via-resistance vs. Diameter (Cu: 3µm,
structures for the interconnectivity needed for the                    BCB:3µm)
ATLAS pixel modules. The design of these test struc-             The results show that it is possible to build a MCM
tures for evaluation was a necessary first step in the       even with more than 6000 I/O's per cm2 from the Si-
design process due to the high demanding geometrical         substrate through the deposited BCB/Cu sandwich to
and electrical specifications of the interconnections on     the top metal, the component layer.
the detector.
   The high frequency electrical characteristics of the       C Solder Bumping and Flip Chip Bonding
7 cm long MCM-D interconnections have been deter-
                                                                  The general ATLAS requirements for bump deposi-
mined using microstrip transmission line test structures.
                                                              tion are: spacing of 50 microns, approximately 3800
These structures, have been measured using a HP
                                                              bumps per integrated circuit and high yield (a defect
8510C network analyzer.
                                                              rate of less than 10 -4 is desired).
    The measurement results indicated that in this case a
                                                                  The bump deposition process requires the deposition
characteristic impedance of 50 may be realized with
                                                              of metals on the aluminum pads of either the silicon
28 m wide microstrip lines. The lines of the bus test         sensor wafers or integrated circuit wafers (FE-die) to
structure are 20 m wide, and hence a characteristic           allow good adhesion and soldering of the bump metal
impedance higher than 50 , namely 67 , has been               and to prevent diffusion of this metal. The process used
obtained. The attenuation and cross talk levels along         was electroplating of PbSn60 solder bumps with a
these very long and closely spaced bus lines are very         TiW/Cu under bump metallization (UBM) on the FE-
low. Figure 4 depicts a comparison between an active          wafer and the deposition of the same UBM on the Si
and a coupled bus line. A signal attenuation of 4 dB          sensor wafer (Fig. 5 and Fig 6).
and a far end cross talk level of maximum 2 % for a fast
                                                                  Flip chip assembly is the process of mounting the
step signal of less than 100 psec rise time have been         integrated circuit die face down onto the silicon sensor
measured.                                                     substrate. A large number of different types of commer-
                                                              cial flip chip bonders are available that can provide the
                                                              required few micron placement precision and the pres-
                                                              sure or heat that is needed to form or initiate the bond.
                                                              In the case of using solder bumps, the parts (FE-die
                          -17 dB 2 % cross talk               &substrate) are aligned by a FC-bonder (KSM), re-
                                                              moved from the bonder and then heated (reflowed) in a
                                                              separate oven to make the solder connection. Typical
                                                              reflow cycles peak at a temperature of about 250 deg C
                                                              (eutectic solder melts at about 180 deg C). The number
                                                              of placements required for ATLAS are some 35,000
                                                              good placements. The small bump size implies high
                                                              precision placement and the need to assemble thinned
                                                              parts requires considerable care.


Figure 4: Typical network analyzer measurement results (S21
transmission scattering parameters) for a long active bus
structure line and its coupled neighbor (spacing 20 m). The
measured maximum far end cross talk is –17 dB or less than
2 %.


B. Irradiation Tests
    As the detector elements are located very near to the
circulating beams, all components have to be radiation
tolerant enough to survive the expected detector life
time. A test with samples has shown that the material
has not degraded significantly due to the irradiation.        Figure 5: PbSn60 bumps after electroplating (UBM:Ti:W/Cu)
The effective relative permittivity changes of about 1.5
% to 2.5 %, depending on the sample, have been meas-
ured for both the electron and proton irradiated wafers.
Furthermore, the measured signal attenuation and cross
talk along the 7 cm long bus structures before and after
the irradiation indicated no significant difference.
                                                                upper metal layer to flip-chip assembled dummy read
                                                                out chips. The via openings are 25 m in diameter.
                                                                The figure shows the critical distance between the cen-
                                                                ters of two solder balls in adjacent pixel cells, a distance
                                                                of only 50 m. From more then 1.1 million monitored
                                                                vias a defect rate of less then 10-5 has been determined.
                                                                .




Figure 6: PbSn bumps after reflow (pitch 50 µm, diam.
           25µm)



 D Full Scale Prototypes and Yield
    The mentioned feed through connections from the
sensor pad to a pad in the uppermost Cu layer, to be
used for the bump connection to the FE chip, needs
special care. Four vias are needed for each of these
structures, i.e. for each pixel cell, to connect the cell's     Figure 8: Cu structures from the substrate to the top metal
output pad to a component layer pad. As there are more                    layer, BCB etched for better visualisation.
than 61,000 interconnection structures with nearly
                                                                In the top view of Figure 8 one sees the (free standing)
250,000 vias in a single module, a test program has
                                                                2 m thick and 20 m wide feed through Cu structures
been set up to determine experimentally the via yield of
the thin film multilayer and to study in addition the           from the substrate to the top metal layer. For a better
procedure of flip-chip assembly onto the MCM layers.            visualization the BCB dielectric has been etched away.
Here four 2 m thick Cu layers interleaved with 5 m              On the substrate one recognizes connections between
thick BCB layers have been deposited onto "dummy"               pairs of two adjacent pads and no connection between
sensor substrates. The vias in the uppermost BCB layer          two of such pairs.
(component layer) are opened to allow the solder Join-
ing of the FE chips. Full scale modules with 16 FE
chips bump bonded to the substrate have been built.




                                                                Figure 9: Top view of the 4 metal &dielctric layer

Figure 7: Cross section through the solder balls and the four
         metal & BCB layers of the thin film multilayer         After the flip-chip assembly of dummy FE chips these
                                                                "holes" are closed by appropriate connection paths
Figure 7 shows a cross-section through a module, illus-         within those chips. With such a set-up one builds a
trating the deposit of four 2 m thick copper layers             daisy chain for easy control of the quality of all inter-
separated by four 5 m thick Photo-BCB layers. The               connections including the bump connections. The re-
cut is placed through the solder balls which connect the        sults obtained in this phase confirm that an ATLAS
type pixel module can be built using thin film technol-        III. Conclusions
ogy and solder bump flip chip connections.                      Due to the robust interconnection technology (only
                                                            bump connections, no fragile wire bonds), and the en-
                                                            couraging results obtained so far, the MCM-D type
E Demonstrator Module                                       module implementation appears to be a candidate
    As the last step before a module decision, a demon-     building block for large area pixel detectors. Two metal
strator module with a real sensor fabricated by CiS in      planes separated by BCB dielectric layers allow for fast
Germany and by SEIKO in Japan assembled with real           signal transmission and low cross talk between adjacent
FE chips is being built by IZM. Measurements from this      signal lines on the interconnection bus. The two addi-
demonstrator module should give information on the          tional metal layers below the signal lines offer the pos-
passive components needed for the MCM-D type of             sibility of low resistivity power distribution because of
modules. Due to the space available it is possible to       their larger widths. The metal structures (microstrip
place decoupling capacitors at the beginning and the        lines) result in controlled-impedance transmission sig-
end of the bus structures on both sides of the module.      nal lines. It has been demonstrated that the needed very
Because of the simple and not much disturbed electrical     high feed through density is achievable with present
interconnection from the FE chip to the MCC this de-        available thin film technology to meet the requirements
coupling scheme might be sufficient. If it turns out that   of such a high density module.
capacitors have to be foreseen for each FE chip then one
has to enlarge the module (sensor/substrate) width by
about 1.5 mm.                                                               Acknowledgement
                                                                The authors wish to thank especially Dr. G. Engel-
                                                            mann, Ms. S. Fehlberg, Ms. Ch. Kallmayer and E.
                                                            Busse for their technological advice and the rest of the
                                                            ATLAS-group for technical support and many helpful
                                                            discussions.


                                                                                   References
                                                            [1] K.-H. Becks et al., "A Multi-Chip Module, the
                                                                Basic Building Block for Large Area Pixel Detec-
                                                                tors", Proc. of IEEE Multi-Chip Module Confer-
Figure 10:     Photograph of a detector module with 16 FC
             bonded FE-chips                                    ence (1996) 16.
                                                            [2] DELPHI       Collaboration,     CERN/LEPC-92-12
                                                                (1992).
                                                            [3] M. Pecht, Integrated Circuit, Hybrid, and Multi-
                                                                chip Module Package Design Guidelines -A Focus
                                                                on Reliability, J. Wiley & Sons (1994).
                                                            [4] J.E. Morris, Electronics Packaging Forum -Multi-
                                                                chip Module Technology Issues, IEEE Press
                                                                (1994).

								
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