read_channel_design_spec

Preliminary Revision History Read Channel Design Specification Read Channel Design Orion Design Technologies, Inc. Preliminary Read Channel Design Specification TABLE OF CONTENTS 1.0 Nomenclature.................................................................................................................... 2 2.0 Overview .......................................................................................................................... 4 3.0 Functional Description ....................................................................................................... 5 3.1 Control Block .................................................................................................................... 5 3.2 AGC ................................................................................................................................. 6 3.3 Filter................................................................................................................................. 9 3.4 Servo Demodulator.......................................................................................................... 12 3.5 Pulse Detector ................................................................................................................ 13 3.6 Frequency Synthesizer .................................................................................................... 15 3.7 Data Synchronizer........................................................................................................... 17 4.0 Pin Descriptions .............................................................................................................. 20 4.1 Control............................................................................................................................ 20 4.2 AGC ............................................................................................................................... 20 4.3 Filter............................................................................................................................... 20 4.4 Servo Demodulator.......................................................................................................... 21 4.5 Pulse Detector ................................................................................................................ 21 4.6 Frequency Synthesizer .................................................................................................... 21 4.7 Data Synchronizer........................................................................................................... 21 4.8 Power Supply.................................................................................................................. 22 5.0 Electrical Characteristics ................................................................................................. 22 5.1 Absolute Maximum Ratings.............................................................................................. 22 5.2 Recommended Operating Conditions ............................................................................... 22 5.3 General .......................................................................................................................... 22 5.4 AGC ............................................................................................................................... 24 5.5 Filter............................................................................................................................... 27 5.6 Servo Demodulator.......................................................................................................... 30 5.7 Pulse Detector ................................................................................................................ 31 5.8 Frequency Synthesizer .................................................................................................... 32 5.9 Data Synchronizer........................................................................................................... 32 5.10 Serial Interface Timing ................................................................................................... 34 5.11 Control Timing............................................................................................................... 35 6.0 Programming .................................................................................................................. 36 6.1 Registers ........................................................................................................................ 36 6.2 Power Management Control and Change Pump Test(Address 0) ....................................... 37 6.3 AGC Control (Address 1) ................................................................................................. 37 6.4 Pulse Detector Hysteresis for Data Mode when FMT=0 (Address 2) ................................... 38 6.5 Pulse Detector Hysteresis for Data Mode when FMT=1 (Address 3) ................................... 38 6.6 Pulse Detector Hysteresis for Servo Mode (Address 4) ...................................................... 38 6.7 Filter Cutoff Frequency and Filter Servo Tuning Control (Address 5)................................... 40 6.8 Filter Pulse-Slimming Boost For Data Mode (Address 6).................................................... 40 6.9 Filter Pulse-Slimming Boost For Servo Mode (Address 7) .................................................. 41 6.10 Data Synchronizer PLL Window Adjustment and Test Modes (Address 8)......................... 42 6.11 Frequency Synthesizer Numerator (Address 9) ............................................................... 43 6.12 Frequency Synthesizer Denominator (Address 10) .......................................................... 44 6.13 Frequency Synthesizer DAC&Data Synchronizer PLL Loop Filter Bandwidth (Address 11). 44 6.14 Test Modes (Address 12) ............................................................................................... 45 6.15 Readback (Address 15) ................................................................................................. 46 7.0 Package ......................................................................................................................... 47 8.0 Application Configuration................................................................................................. 48 1.0 Nomenclature Lowercase signal names corresponds to internal signals. Preliminary Read Channel Design Specification Uppercase signal names corresponds to signals accessable through package pins. Register bit abbreviation is RX[ dy] where X = register number and y = bit number. All signals are active high unless shown with b. i.e. signal Preliminary Read Channel Design Specification 2.0 Overview The i20065 is a high performance and low-power single chip read-channel IC developed for diskdrive applications. The chip uses a single power supply which can range from 4.5 to 5.5 volts. The architecture of the chip provides maximum flexibility while minimizing the number of external components required. Function block contains the automatic gain control (AGC), active filter, pulse detector, servo demodulator, data synchronizer, frequency synthesizer, and serial interface control. Low-power operation is achieved by employing low-voltage design techniques, CMOS technology, and a sophisticated power-down scheme. The device accommodates constantdensity recording and embedded servo functions without need for any additional external components. The on-chip synthesizer enables changes in the transfer rate and the on-chip filter has asymmetrical (or symmetrical) pulse slimming. These features, and more, are programmable through the serial interface. RCP DLF1N DLF2N DLF2P DLF1P TEST SRD VCOCLK Data Synchronizer Frequency Synthesizer REFCLK FSLFP FSLFN FLBP FLBN FDBP FDBN AIN AIP CAGCD CAGCS VPK HOLD AGC Filter Pulse Detector SCLK SLOAD SDATA RGT WGT SGT CEN RBIAS Servo Demodulator Control Figure1. Read Channel Block Diagram VEXT SAMPLE SELECT1 SELECT2 VRS SAB SCD ERD FMT Preliminary Read Channel Design Specification 3.0 3.1 Functional Description Control Block The control block shown in Figure 2 includes reference, serial interface, and control logic. The chip interfaces to the controller through a simple serial interface. Data is organized in 16-bit sequences. An 8-bit address is shifted in first, followed by eight bits of data (MSB first). Only 4 bits of the address word are used to support the 13 internal registers, thus leaving the remaining address space to allocate to other circuits sharing the serial control lines. Address and data are clocked in on the rising edge of SCLK and loaded to one of the internal registers on the rising edge of SLOAD . The Readback function can be used to verify register programming. To obtain information from the chip's internal registers, shift in the readback address (0000 1111) followed by the address of the register to be read back in the 8 bit data field as shown in the table in section 6.14. During Readback, eight bits of data are shifted out on the SDATA pin on the falling edge of SCLK. After the eighth rising edge of SCLK, preceded by the first falling edge of SCLK after SLOAD transitions high, the SDATA pin will become high impedance. The timing diagram is shown in Figure 18. The Control-Logic block allows any of seven power modes to be selected through combinations of chip input CEN or by writing to the Mode-Control register through the serial interface. Register 0 defines how the modes are enabled and the circuits activated by thee modes. Table 1 shows the logic equations for the various modes. Some setup time is required when switching modes as specified in section 5.3. In Sleep mode (Sleep) all functions are inactive except the Serial Interface and power-on-reset circuit. This mode could be used when the head is unloaded or the spindle motor is stopped. During this mode the AGC integrator caps, servo detector caps, the filter tuning PLL, the frequency synthesizer PLL, and the data synchronizer PLL are initialized. All programmed internal register values are preserved. One of two Idle modes may be used during a seek or a condition when neither data or servo is being read; however, the read channel is in a state that may be quickly activated. If R0[d2] input is inactive then a low power idle mode (idle) is actived. In this mode only the bias circuits are active. The charge on the AGC integrator caps, the filter tuning, frequency synthesizer, and data synchronizer PLL filters is preserved with minimal leakage. A medium power idle mode (Idle w/PPLs) may be enabled when R0[2d] is active. In this mode the bias circuits, the filter tuning PLL, the frequency synthesizer, and the data synchronizer PLL are active. This mode would be used to minimize the time required from Read/Write mode to the data field. The Servo-Tracking mode (Servo) is used when only servo data is being read. The AGC, Filter, Servo and Pulse Detector are active. A Servo with PLLs active mode (Servo w/PLLs) is available that also keeps the PLLs active. Read/Write mode (Read/Write) is used for either reading or writing data. In this mode, the AGC, Filter, Filter Tuning, Pulse Detector, Data Separator, and Frequency Synthesizer functions are all active. When a servo frame is encountered, Servo with Read/Write mode (Servo w/RW) is used which activates the Servo functions along with the functions listed above. The Reference block generates the reference voltages and currents needed by the rest of the chip. Currents are derived from an external resistor connected to the RBIAS pin. Preliminary Read Channel Design Specification A power-on-reset signal, por is provided to reset registers to the default state shown in Section 6.1. RBIAS References (V & I) por vref ibias SLOAD Serial SCLK SDATA RGT WGT SGT CEN Interface register data pdidle Control Logic pdr pdafp pds Power management control Figure 2. Control Block Diagram Table 1: Control Signal Definition Control Logic pdidle = CENb * R0[d0]b pdr = CENb * R0[d0]b + R0[d3]b * R0[d2] pdafp = CENb * R0[d0]b + R0[d1]b * R0[d3]b pds = CENb * R0[d0]b + R0[d1]b Used By Control Filter tuning, Data synchronizer, Frequency synthesis AGC, Filter, Pulse Detector Servo Demodulator 3.2 AGC The AGC shown in Figure 3 is used to control the input signal level of the Filter. It includes the variable gain amplifier (VGA), the integrator, the peak detector, and input impedance switch. The AGC has special controls selectable through the serial interface, (droop and agc disable) to provide flexibility. The input to the AGC is connected to the ac-coupled output of the external preamplifier. When WGT is active, the AGC's differential inputs are shorted through a low-impedance path to an internally-generated analog ground (vcm) while the AGC control voltage is held constant. This mode will continue after WGT becomes inactive until a programmable time-out occurs. This allows the input signal from the external preamplifier to settle before enabling the AGC, therefore provides for quick recovery between writing and reading. The VGA has a 26dB automatic-gain range and its gain is controlled by the voltage stored on the external capacitors (CAGCD or CAGCS). The VGA may be programmed into an AGC disabled mode in which the VGA is forced to a fixed mid-range gain. Preliminary Read Channel Design Specification The AGC has effectively two control loops. A separate integrating capacitor(CAGCS) is used when SGT is active and a different capacitor(CAGCD) is used when SGT is inactive. This allows the data and servo frames to have independent charging and discharging rates and also reduces the AGC settling time when switching between servo and data frames. The gain of the AGC is adjusted by comparing the differential peak-to-peak voltage at the flpp and flpn outputs of the Filter to an internally-generated reference voltage (vrh). The result is integrated on an external capacitor at either the CAGCS or CAGCD pin. If the peak detector output voltage (VPK) is greater than 140% of vref, the integrator gain is boosted by 3 to provide an AGC fast attack mode. Normal attack and decay of the control voltage for the VGA are symmetrical. The VGA gain changes exponentially with the control voltage. When the HOLD input is active the AGC control voltage will be held constant, permitting the AGC loop to hold its gain during periods of embedded servo bursts. There is a DC offset cancellation circuit inside the VGA stage to remove a differential DC offset voltage. The master-slave peak detector shown in Figure 4 is used to drive the AGC integrator and optionally the hysteresis control circuitry of the Pulse Detector. The output of the peak detector tracks the peak magnitude of the input signal with minimum droop between peaks. The master is a traditional peak detector that has its droop set by an internal current source and capacitor. The slave is also a peak detector that is only allowed to droop when the master is charging. This implementation results in minimum droop during periods of no data or few data transitions while allowing a fast response to actual changes in peak signal levels. Under normal conditions of reading data, the droop of the master cell is controlled to allow a limited amount of droop during the longest permissible string of zeros in the input signal. When the input signal drops suddenly to zero, the master detector doesn't charge and no discharge of the slave detector occurs. The slave detector will hold its level until the master detector has decayed to 10% of vref in which it will be rapidly discharged. The droop time for the master peak detector applies to the condition where the AGC is locked and the signal disappears. For the condition where no signal exists, the AGC gain goes to a maximum limit. When a signal appears, the input to the peak detector is over-driven. While the master peak detector output is driven greater than 140% of the normal AGC level, the droop rate is increased by 3. This gives a droop time less dependent upon the over-driven level. The droop of the master detector is independently programmable for servo and data mode operation. Selection is made by SGT. The waveforms of peak detector are shown in Figure 5. When CEN has been inactive, and then activated, the capacitors on the CAGCD and CAGCS pins are pre-charged to a mid gain condition for faster recovery. The Peak detector is also reset. There are two voltage clamps connected to the CAGCD and CAGCS individually. If voltages on the CAGCD and CAGCS are out of control range (either too large or too small), the clamps will be active to clamp them to improve the recovery time. Preliminary Read Channel Design Specification pdafp pdidle AIP aop vcm AIN VGA aon CAGCS CAGCD WGT HOLD SGT Delay vrh gm flpp flpn Peak Detector x1 VPK droop registers agc disable buffer enable Figure 3. AGC Block Diagram register flpp flpn Full-Wave Rectifier Master Peak Detector CM Mux CS Slave Peak Detector VPK Servo droop Data droop SGT vrh/10 Figure 4. Peak Detector Preliminary Read Channel Design Specification Rectified Signal master droop Master Peak Detector slave droop enabled Slave Peak Detector vrh Droop Time Droop Time Figure 5. AGC Waveforms vrh/10 3.3 Filter th The filter provides amplitude and phase equalization of the read signal. It consists of a 6 -order, linear-phase, 0.05° equiripple, low-pass response with programmable cutoff and asymmetrical pulse slimming. The filter is master-slave tuned to the current set by an external resistor RFILTER. The tuning circuit controls the cutoff frequency. Since the servo-cutoff frequency can be different from that required for reading data, a separate register containing the digital coarse-tuning control value is used by the filter when SGT is active. SGT is also used to select the separate pulseslimming register values for servo and data. The value of the servo coarse-tuning register is set during a servo-tuning mode. The tuning circuit stores the state of the coarse-tuning control at the conclusion of the servo-tuning mode. After the servo tuning mode is finalized, the filter tuning PLL, frequency synthesizer, and frequency scaling settings are not used during the servo mode (SGT active). To block differential offset on the filter input and outputs, DC cancellation circuits are used. This adds 2 high pass poles that are low enough not to distort the group delay. The transfer function of the slave filter is the following: H NORM     s   s      ω 2 1 +      ω 2 1 − p2  p3  ω za    ω zb    ω 21      p =    ω p2 ω p3 ω P1 2  2  s2 + s s +s + ω 2   s2 + s + ω 23  + ω p1 p p 2 QP1 Q QP     P2 3     HDiff = s ⋅ H Norm The poles of the low-pass response are given in the following table: Preliminary Read Channel Design Specification Biquad 1 2 3 ωP 2.074 1.470 0.981 QP 1.686 0.893 0.551 Note: ω c normalized to 1 rad/sec The programmable zeros follows: ω za and ω zb provide the pulse slimming. They are programmed as ω za = 0.58 ⋅ ω zb = 0.58 ⋅ 15 ⋅ω c na 15 ⋅ω c nb n a ∈ ( 0...15) n b ∈ (0...15) Preliminary Read Channel Design Specification pdafp x5 aon aop Pulse Slimming SGT Mux Servo ωza , ωzb Data ωza, ωzb Programable Filter x5 Tuning Mux x1 FLBP FLBN fdp fdn flpp flpn x1 FDBP FDBN Register servo tune control tfb registers freq scaling RGT RFILTER pdr vref Filter Tuning Control Figure 6. Filter Block Diagram 1/ωza out bp aop aon inb B1 out lp ina inb out bp B2 out lp 1/ωzb ina out bp B3 inb outlp fdp fdn flp fln Figure 7. Filter Biquad Configuration ina ++ out bp Kωo/Q ωo/Q + + ωo/Q ωoQ + + + + ωo/Q inb ++ out lp Figure 8. Biquad Preliminary Read Channel Design Specification 3.4 Servo Demodulator The servo detector shown in Figure 10 can be used for either burst-pattern, interlace-pattern, or quadrature detection. The input signal for the Servo Detector block is taken from the low-pass output of the Filter, and is full-wave rectified and peak detected and then gated to any of four hold capacitors. The selection of bursts A, B, C, and D is controlled by external pins, SELECT1 and SELECT2, as shown in the table below. To improve noise rejection, the charging of the internal holding capacitors is current limited. The four internal detected burst levels are provided on the buffered outputs, A, B, C, and D which are referenced to an internally-generated voltage, VRS. The difference of two sequential pairs of bursts, of A and B, C and D, are provided at SAB and SCD respectively, referenced to UEXT. All amplifiers are powered when R0[d1] is activated and remain powered until the srst signal is activated. To properly set the servo gain, the AGC should be enabled during the servo normalization field, SN. Before the end of the servo normalization field, the gain of the AGC should be held by activating the HOLDb pin. The waveforms are shown in Figure 9. A, B, C, D are selected using SELECT1, SELECT2 and the appropriate gate is opened and closed using SAMPLE. The servo is reset by asserting SAMPLE with HOLD deasserted. A level shifter generates VRS (used as the servo-reference voltage) and vrh (used by the AGC and Pulse detector). D A Track n Track n+1 Track n+2 Data Data Data SN B SN A SN B D Track n signal C Data D Data C Data SGT HOLD Figure 9. Quadrature Servo Burst Pattern Preliminary Read Channel Design Specification PkDt S/H A + x2.67 SAB PkDt S/H flpp flpn Full-wave Rectifier B PkDt S/H C + x2.67 SCD PkDt S/H ga gb gc gd D SAMPLE SELECT1 SELECT2 Logic Control srst pds VEXT vref vcm pdidle Level Shifter R Q F/F S VRS vrh Figure 10. Servo Detector SELECT2 0 0 1 1 SELECT1 0 1 0 1 Servo Burst Selected A B C D 3.5 Pulse Detector The pulse detector shown in Figure 11 is used to accurately replicates the time position of the filter output peaks. It consists of a zero-crossing comparator, a hysteresis comparator, qualification logic, and a monostable. Pulses are provided on the encoded read data output, ERD in which the falling edge of the pulse corresponds to the peak of the filtered data signal. Depending on the setting of R13[d0], the ERD signal is available only when SGT is active (thus reducing on-chip noise generation during data mode), or always available (i.e. for test purposes). The zero-crossing detector is driven by the differentiated outputs of the filter (fdp & fdn). Either a Preliminary Read Channel Design Specification maximum or minimum of the filtered-data signal (flpp & flpn) is indicated when the differentiated signal crosses zero. The comparator with hysteresis provides an amplitude qualification of the zero crossings of the differentiated signal to prevent false triggering of the monostable by baseline noise. Separate hysteresis levels may be programmed for servo and data. Servo hysteresis is enabled when SGT is active and data hysteresis is enabled when SGT is inactive. Input pin FMT selects the separae hysteresis levels for data mode during disk format. The hysteresis levels are programmable through the serial interface. The hysteresis levels are scaled to a fixed reference voltage vrh. The qualified-data signal triggers the monostable to generate a pulse for each detected peak. An additional polarity qualification is applied. A qualified peak of one polarity must be followed by a qualified peak of the opposite polarity before another peak of the same polarity is allowed. registers FMT MUX hys data SGT MUX hys servo erdp enable hys control vrh MDAC ERD threshold flpp flpn D D VDD D VDD D MUX Q R Q R Q R Q R fdp fdn O.S. pdafp DELAY erdp Figure 11. Pulse Detector Block Diagram Preliminary Read Channel Design Specification 3.6 Frequency Synthesizer The frequency synthesizer shown in Figure 12 generates clock references that are used in the Data Synchronizer. The input to the frequency synthesizer is the reference clock (REFCLK) and its output is the quadrature encoded-clock (wclk) where: wclk = M x REFCLK N The 5-bit current DAC is programmed through the serial interface. It sets the center frequency of the synthesizer's VCO. Bias outputs, idln1,2,3,4, are used in the Data Synchronizer to set the center frequency of its PLL and to scale the delay in the Delay Cells. The scaling coefficients, M and N, are also programmed through the serial interface with 7-bit precision. The programmability of the frequency synthesizer is useful in zoned recording applications. The phase detector is a type IV detector (detects both phase and frequency). The charge pump current is referenced to the RBIAS resistor. The external loop filter is fully-differential and balanced to suppress common-mode noise. The PLL open-loop gain is: G ( s) = 0.8 ⋅ I RBIAS ⋅ K VCO ⋅ The loop zero is: s+ωZ 1 1 1 ⋅ ⋅ ⋅ 2 M 2π C2 ⋅ s s + ω P ωz = The high frequency pole is: 1 R ⋅ C1 ωp = The natural frequency of the loop is: C1 + C2 R ⋅ C1 ⋅ C2 ω n ≈ 0.8 ⋅ I RBIAS ⋅ K VCO ⋅ 1 ⋅ 1 ⋅ 1 M 2π C1 The damping ratio of the loop is: (if C1 〉〉C2 ) ς= ω n ⋅ R ⋅ C1 2 Preliminary Read Channel Design Specification C2 C1 pdr pdidle REFCLK N OF Detect R FLF1P Charge Pump FLF1N idln1,2,3,4 wclk VCO M registers DAC Figure 12. Frequency Synthesizer Block Diagram Preliminary Read Channel Design Specification 3.7 Data Synchronizer The output (erdp) of the Pulse Detector is fed into the Data Synchronizer block shown in Figure 13, which extracts the clock (rclk ), and uses it to synchronize the data (syncdata). The two delay lines track the Synthesizer's VCO and have a delay nominally one half the window (wclk period). The delay line driven by the rclk is programmable to provide fine window adjustment to four bits resolution plus sign. Programmable selection of early or late outputs from the delay line driven by erdp may be used to extend the window adjust range. Window adjustment does not disturb the PLL, since it is outside the loop. When the window adjustment is bypassed, R8[d5:d0] = all zeros, syncdata is taken from the output of the Pulse Gate. When the window adjustment is enabled, R7[d5:d0] = non-zero, window adjustment may be used to correct for window centering errors. Either mode may be used during a read operation. An external, fully-differential and balanced loop filter are depicted in Figure 14. An external, fullydifferential and balanced loop filter is used to suppress common-mode noise. The loop filter is driven by two separate pairs of charge pump outputs. The programmable charge pump allows the loop characteristics to be optimized for each zone in a zoned-recording application. The first current multiplier, KG, programss the gain of the loop and is used to control the loop parameters when switching between zones. The first two current multipliers are duplicated in the IDLF2 path, which controls the current at the DLF2 pin and are used to scale the loop zero. A constant ratio of loop bandwidth to loop zero is automatically maintained to give a constant damping factor. The charge pump current is scaled by an external resistor connected to the RCP pin, where: I RCP = The current at the IDLF1 output is: 1.25 RCP I RCP 8 I DLF1 = KG ⋅ KG = 1 + And the current at the IDLF2 output is: G 7 G ∈ 0. ..7 I DLF 2 = I DLF1 ⋅ ( KG − 1) The PLL open-loop gain is: G( s ) = I DLF1 ⋅ KVCO ⋅ Where: 1 1 s +ω z 1 ⋅ ⋅ ⋅ 2 2π C2 ⋅ s s + ω P n n= fVCO f DATA ( 2 ≤ n 8 for 1, 7 code) The effective loop zero is: Preliminary Read Channel Design Specification ωz = The high frequency pole is: KG 2 ⋅ R ⋅ C1 ωp = C1 + C2 2 ⋅ R ⋅ C1 ⋅ C2 By approximating the loop as second order, the natural frequency of the loop is: ωn ≈ KG 4 I RCP ⋅ KVCO ⋅ 1 ⋅ 1 ⋅ 1 π C1 n ( if C1 〉〉 C2 ) The damping ratio of the loop is: ς= ω n ⋅ R ⋅ C1 KG The VCO has a linear transfer characteristic, and its center frequency is set by the Frequency Synthesizer. Zero phase restart is used to speed up the acquisition time when switching from the reference clock (wclk) to data (erdp) and back again. The output of the VCO is fed back to the phase detector to close the loop. Preliminary Read Channel Design Specification pdidle registers pdr delayed rclk T/2 + α Data Align 3/8 T wclk erdp /2 T/2 Delay T/2 delayed erdp Mux 5/8 T Mux O/F Detect & Charge Pump Mux Mux Program Delay SRD syncdata rclk TEST VCO Zero Phase Restart PHLCK Pulse Gate /2 Mux DLF1N DLF2N Clock Swap VCOCLK RCP R C1 DLF2P R DLF1P Figure 13. Data Synchronizer Block Diagram C2 RGT l RCP KG lDLF1 DELF1 _ KG registers + lDLF2 DELF2 Figure 14. Charge Pump Block Diagram Preliminary Read Channel Design Specification 4.0 4.1 Pin 2 Pin Descriptions Control Name SLOAD Description Input, Used to latch serial data to internal registers. Data may be shifted in when SLOAD is low. Data is latched when SLOAD transitions high. 3 4 SCLK SDATA Input, Used to clock in serial programming data Bidirectional, Data is clocked in on a low-to-high transition of SCLK. Used for shifting out programming data stored in internal registers. Data changes on a low-to-high transition of SCLK. Ouput is high impedance until after a high transition of SLOAD after writing to the readback address. The output returns to a high impedance state after the 9th clock edge after SLOAD goes high. 14 15 16 31 46 RBIAS SGT WGT RGT CEN External resistor connected to ground provides a current reference for internal use. Input, Active high, Enables servo mode if CEN is active Input, Active high, Enables write mode if CEN is active Input, Active high, Enables read mode if CEN is active Input, Active high, A low level places the chip in a low power sleep mode. A high level combined ith SEN, PEN and RWEN inactive places the chip in a low power idle mode. 4.2 Pin 17 19 20 29 22 23 AGC Name VPK HOLD CAGCS CAGCD AIP AIN Description Peak detector output Input, Active low, Enables AGC hold mode External capacitor for AGC loop filter used for servo mode External capacitor for AGC loop filter used for data mode AGC differential signal inputs 4.3 Pin 26 27 28 29 Filter Name FDBN FDBP FLBN FLBP Description Buffered differential signal from filter differentiated outputs. Normally outputs are in an inactive high impedance condition since these outputs are provided primarily for testing of the filter. Buffered differential signal from filter low-pass outputs. Normally outputs are in an inactive high impedance condition since these outputs are Preliminary Pin Name Description Read Channel Design Specification provided primarily for testing of the filter and AGC. 4.4 Pin 5 6 7 8 9 10 11 Servo Demodulator Name SAMPLE SELECT1 SELECT2 SAB SCD VEXT VRS Description Input, Active high, Set sample time for servo burst and the last pulse reset all sampling capacitances. Input, Selection of burst detectors Input, Selection of burst detectors Buffered output of servo detectors Input, Reference voltage for SAB and SCD outputs. Output, Servo internal reference voltage 4.5 Pin 32 33 Pulse Detector Name ERDb FMT Description Encoded raw data output from pulse detector. Rising edge of pulse corresponds to data transition. Input for setting the hysteresis threshold during disk format. 4.6 Pin 42 43 47 Frequency Synthesizer Name FSLFN FSLPP REFCLK Description Synthesizer differential loop filter pins. Reference input to the synthesizer block. 4.7 Pin 34 35 44 45 38 39 40 41 Data Synchronizer Name RCP TEST VCOCLK SRD DLF2N DLF2P DLF1P DLF1N Description External resister connected to ground provides a current reference for data PLL charge pump. Output pin used to test delayed erd or window adjustment. Reference Clock. Output of the Data Synchronizer’s VCO or Frequency Synthesizer’s VCO, used by the controller to read or write data. Output of synchronized read data. Data Synchronizer, differential loop filter 2 pins. Used for setting loop zero frequency. Data Synchronizer, differential loop filter 1 pins. Used for setting loop bandwidth. Input to VCO. Preliminary Read Channel Design Specification 4.8 Pin 12 13 Power Supply Name VDD1 VSS1 Description Positive supply Ground Used for the AGC, Servo Demod., and Reference. 24 25 VDD2 VSS2 Positive supply Ground Used for the filter. 36 37 VDD3 VSS3 Positive supply Ground Used for the Data Synchronizer and Pulse Detector. 48 1 VDD4 VSS4 Positive supply Ground Used for the Frequency Synthesizer, Serial interface, and all PAD cells. 18 VSUB Substrate connections Important Note: All VSS-type pins and all VSUB-type pins must be connected together externally using short wide traces to individual PCB thru-holes directly to one single ground plane . All VDD-type pins must be connected together externally using short wide traces to individual PCB thru-holes directly to one single power plane . All supplies must be decoupled (typically 0.1µF) as close to the device package pins as physically possible with low-inductance trace layout techniques (typically wide, straight, and short). 5.0 5.1 Electrical Characteristics Absolute Maximum Ratings Conditions VDD-VSS min relative to VSS max relative to VDD Min 0 -0.3 0.3 -65 150 Nom Max 7.0 Units V V V °C Parameter Supply Voltage Voltage on any input Storage temperature 5.2 Recommended Operating Conditions Conditions VDD-VSS Min 4.5 0 Nom 5.0 25 Max 5.5 70 Units V °C Parameter Supply Voltage Ambient operating temperature 5.3 General (RBIAS = 2kΩ unless specified otherwise) Preliminary Parameter Supply Current Conditions VDD=5.0v Read/Write Servo mode Servo mode w/ PLLs Servo mode w/WR Idle mode Idle mode w/ PLLs Sleep mode Upper threshold (VDD increasing) Lower threshold (VDD decreasing) Digital inputs, VDD = 5V Digital inputs, VDD = 5V Digital outputs, VDD = 5V,IOH = -2mA Digital outputs, VDD = 5V, IOL=3.2mA 2.4 1.8 0.2 2.0 Min Read Channel Design Specification Nom Max Units 150 85 135 140 8 55 100 2.2 2.6 1.6 mA mA mA mA mA mA µA V V V Power-on-reset threshold High level input voltage Low level input voltage High level output voltage Low level output voltage Digital output Fall Time (except P1, P2) Digital output Rise Time (except P1, P2) RBIAS Capacitance loading on RBIAS pin Voltage at RBIAS pin CEN active to SEN active SEN active to Servo frame RWEN active to Data frame SGT inactive to RGT active SGT inactive to WGT active RGT inactive to SGT active WGT inactive to SGT 0.8 V V 0.4 2.0V to 0.8V, C <20pF VDD = 5V 0.8V to 2.0V, C <20pF VDD = 5V 10 20 2.375 100 SEN inactive > 1ms SEN inactive < 1ms RWEN inactive > 1ms RWEN inactive < 1ms PEN active 500 10 150 10 10 10 10 10 10 2.5 2.625 5 5 V ns ns kΩ pF V µs µs µs µs µs µs ns ns ns ns Preliminary Parameter active Conditions Min Read Channel Design Specification Nom Max Units 5.4 AGC Conditions Differential Differential -1 9 See figure 24 RGT active Max gain, 3 to 17 MHz Max gain Max gain 0.8 to 17 MHz Over specified input level range 5 MHz (diff out/common in) 5 MHz (diff out/VDD) Differential, WGT inactive WGT active 4 100 kΩ Ω µVRMS µVRMS % % µs 50 40 40 ± 10 1 ±1.5 ±0.6 Min 20 300 25 Nom Max 300 Units mVp-p mVp-p dB dB dB ns Parameter Input signal level range Output signal level Automatic gain control range AGC disabled gain VGA gain tolerance AGC differential group delay AGC -3dB bandwidth AGC output offset AGC THD MHz mV % Input common-mode rejection Power supply rejection Input impedance dB dB Input referred noise Bw = 10 KHz to 16 MHz Min VGA gain Max VGA gain 421 115 ± 20 ± 20 Low input impedance hold time tolerance Peak Detector droop time tolerance Gain decay time From WGT fallingedge CAGCS, CAGCD = 500pF, Input = 8 MHz Peak detect droop = 200ns 50% drop in input level to 90% of final gain 7.5 Preliminary Parameter Gain attack time Conditions CAGCS, CAGCD = 500pF, Input = 8 MHz Peak detect droop = 200ns 200% increase in input level to 110% of final gain DC erase recovery CAGCS, CAGCD = 500pF, Input = 8 MHz Peak detect droop = 200ns No input signal to maximum input level Minimum recommended CAGCS, CAGCD Settling time from switching between servo and data modes Settling time from write to AGC mode CAGC leakage Resistive load on VPK output Capacitive load VPK output data to servo servo to data time interval between WGT goes to low and AGC inputs open During hold mode R to VRS C to VSS 5 2 200 Min Read Channel Design Specification Nom 2.5 Max Units µs 2.5 µs pF 1 1 µs µs µs ±100 nA kΩ 25 pF Preliminary Read Channel Design Specification VGA Gain (db) 14 -6 VCAGCS, VCAGCD (V) Figure 15. VGA Specifications Imput Signal 110% AGC Output Signal 90% VGA Control ( vc) Attack Decay Figure 16. AGC Gain Response Preliminary Read Channel Design Specification DC Erase DC Erase 110% 70% 90% DC Erase Recovery Time Figure 17 AGC DC Erase Recovery 5.5 Filter Conditions Min 3.5 Read mode Servo mode f = 0.1fc f = 0.67 fc Relative to LP gain 15.9 16.9 0 Nom Max 17 ±10 ±10 17.9 ±1 Units MHz % % dB dB Parameter Filter unboosted cutoff frequency (fc ) range Filter cutoff frequency accuracy flpp, flpn gain fdp, fdn gain Phase shift between flpp, flpn and fdp, fdn outputs Programmable boost range at fc Boost accuracy f = 0.67fc 87 90 93 ° 0 Boost = 6.3 dB Boost = 9.3 dB Boost = 12 dB 12 ±0.5 ±0.75 ±1 ±0.6 dB dB dB dB ns Differential group delay without boost RGT active fc = 17 MHz Preliminary Parameter Conditions f =3 to 17 MHz Differential group delay with full boost RGT active fc = 17 MHz f =3 to 17 MHz flpp and flpn harmonic distortion Diff out ≤ 1.5Vp-p, (AGC reference level) No boost, fc /6 < f < fc , 2nd harmonic 3rd harmonic Diff out ≤ 2.25Vp-p, No boost, fc /6 < f < fc , 2nd harmonic 3rd harmonic Diff out ≤ 1.5Vp-p, (AGC reference level) No boost, fc /6 < f < fc , 2nd harmonic 3rd harmonic Diff out ≤ 2.25Vp-p, No boost, fc /6 < f < fc , 2nd harmonic 3rd harmonic Power supply rejection Output noise VDD, 5 MHz, Differential rejection Measurement Bw= 34 MHz, No boost, fc = 17 MHz Filter output differential offset flpp, flpn and fdp, fdn external outputs 35 Min Read Channel Design Specification Nom Max Units ±0.6 ns -40 -40 dB dB -34 -30 dB dB fdp and fdn harmonic distortion -35 -35 dB dB -30 -30 dB dB dB 2.5 mV RMS ± 15 mV Preliminary Parameter Filter common-mode level flpp and flpn output level accuracy Resistive load on buffered filter outputs Capacitive load on buffered filter outputs Refclk feedthrough Settling time from switching filter cutoff data to servo servo to data Differential, measured with AGC in close loop condition Differential C to VSS 2 Conditions Min Read Channel Design Specification Nom 0.5X VDD ±1 Max Units V db kΩ 25 0.5 1 1 pF mVp-p µs µs Preliminary Read Channel Design Specification 5.6 Servo Demodulator Conditions AGC enabled Min 0.89 Nom 1.05 Max 1.21 ±15 Units V mV Parameter Full-scale level on SAB, SCD outputs Differential offset between peak detectors Gain error Gain error matching Non-linearity Minimum width of SAMPLE pulse (tgtw) Minimum dead time between SAMPLE pulses (tgap) Minimum setup time Minimum hold time Slew rate SAB and SCD outputs Droop rate SAB and SCD outputs Minimum width of sample pulse (tsrst ) Resistive load on SAB and SCD outputs Capacitive load on SAB and SCD outputs Detector buffer settling time (ts ) Quiescent output level at the VRS pin. Resistive load on VRS output Capacitive load VRS Input voltage range at VEXT pin input impedance at VEXT pin 25% to 75% relative to full scale ±6 ±2 % % % ns ns 25% to 75% relative to full scale 200 20 ±1 10 10 RBIAS = 10kohm 3.2 ±5 200 R to VEXT C to VSS Settle to 1% 0.48X VDD R to VSS C to VSS from VEXT to VSS 0.45x VDD 5 10 25 .55 VDD 0.5X VDD 5 25 250 0.52X VDD ns ns V/µs V/s ns kΩ pF ns V kΩ pF V kΩ Preliminary Read Channel Design Specification R0[d1] SELECT1 SELECT2 SAMPLE A B C D SAB SCD ts tsetup tgap tgtw thold tsrstw Figure 18. Servo Demodulator Waveforms 5.7 Pulse Detector Conditions Pulse width, CLOAD = 20pF 12MHz sine wave Input Min 8 Nom Max 16 ±0.5 ±10 Relative to VRS 525 1 Units ns ns % mV µs Parameter ERD pulse width Pulse pairing Programmable hysteresis accuracy vrh reference voltage Settling time of hysteresis after SGT changes Settling time of hysteresis after FMT changes ERD 1 µs 12MHz, 100mVpp sine wave input, wclk = 48 Mhz, 1 sigma 1000 ps Preliminary Read Channel Design Specification 5.8 Frequency Synthesizer Conditions Min 16 2 M and N 2 Nom Max 72 72 128 Units MHz MHz Parameter Encoded data frequency, WCLK Reference frequency, FREF Programmable divisors, M and N (wclk adjustment step)/fref VCO Center Frequency accuracy Charge pump current Charge pump leakage Charge pump current accuracy VCO gain constant (K VCO) wclk duty cycle Jitter 0.8 ±17 RBIAS = 4kΩ 0.5 ±100 ±10 16 40 1 sigma, wclk = 55MHz 20 24 60 100 % % mA nA % MHz/V % ps 5.9 Data Synchronizer Conditions (1) Parameter Window shift/Tv c o Window shift resolution/ Tvco Delay cell accuracy Jitter Min Nom ±27.5 1 Max Units % % Relative to T/2 1 sigma, wclk = 55 MHz ±5 100 % ps Window centering accuracy Window width loss Phase detector linear range Charge Pump current Average of window early and window late 0.5 0.25 -2π +2π ns ns With maximum user etting of Ks ,KG Measured at DLF1 Measured at DLF2 0.313 mA Preliminary Parameter Conditions Min Read Channel Design Specification Nom 0.938 Max Units mA ±10 ±100 fVCO = 48MHz Over programmable range 6.4 10 8 9.6 78 ±1 0.95 First erdp pulse edge after dtlck transition 10 20 2.375 2.5 2.625 1.0 1.05 ±3 ns kΩ pF V % nA MHz/V MHz V Programmable charge pump current accuracy Charge pump leakage VCO gain constant (K VCO) VCO frequency range VCO input voltage range fCTR /wclk( 2) VCO restart error RCP Capacitance loading on RCP pin Voltage at RCP pin (1) (2) Tvco is the period of the VCO used to reference the delay line. fCTR is the center frequency of the Data Synchronizer's VCO Preliminary Read Channel Design Specification 5.10 Serial Interface Timing Register Write Tsul T hol SLOAD Tf c SCLK Tmin SDATA Tsud Register Readback Tsuc A7 Thod A6 D1 D0 Trc Tmin Tlmin SLOAD SCLK T hz SDATA D7 D6 D1 D0 Tpd Note: All parameters are speified at VIH min. and VIL max. Figure 19. Serial Interface Timing Diagram Preliminary Read Channel Design Specification Parameter Tsul Thol Trc Tf c Tmin Tsud Thod Tsuc Conditions SLOAD setup time to SLCK SLOAD hold time after SLCK SCLK rise time SCLK fall time SCLK high time and low time SDATA setup time to SCLK SDATA hold time after SCLK SLOAD high to SCLK falling edge 25 15 10 40 15 30 Min Max Units ns ns 10 10 ns ns ns ns ns ns Tlmin Tpd Thz SLOAD high time SDATA delay SDATA hold time after SCLK 50 30 0 ns ns ns 5.11 Control Timing Tc y c Tcl REFCLK Tclh Tchl Tch Note: All parameters are specified at VIH min. and VIL max. Figure 20. FREF Timing Diagram Parameter Tclh Tchl Tch Tcl Tcyc Conditions REFCLK rise time REFCLK fall time REFCLK high time REFCLK low time REFCLK cycle time 5 5 20 Min Max 10 10 Units nS nS nS nS nS Preliminary Read Channel Design Specification 6.0 6.1 Programming Registers Register Address 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 Function Power Management Control and Charge Pump Test AGC Control Pulse Detector Hysteresis for Data Mode when FMT=0 Pulse Detector Hysteresis for Data Mode when FMT=1 Pulse Detector Hysteresis for Servo Mode Filter Cutoff Frequency and Filter Servo Tuning Control Filter Pulse-Slimming Boost for Data Mode (ωza, ωzb) Filter Pulse-Slimming Boost for Servo Mode (ωza, ωzb) Data Synchronizer PLL Window Adjustment and Test Modes Frequency Synthesis Num (M) Frequency Synthesis Den (N) Frequency Synthesis VCO Center Frequency and Data Synchronizer PLL Loop Filter Bandwidth Test modes Readback Bits 3 8 5 5 5 5 8 8 8 7 7 8 Default (1) 0 1 2 3 4 5 6 7 8 9 10 11 0000 0000 0000 0000 0000 1111 0000 1111 0000 1111 0000 0010 0000 0000 0000 0000 0010 0000 0000 0001 0000 0001 0001 1111 12 15 (1) 0000 1100 0000 1111 8 n/a 0000 0000 n/a Power-on-reset forced setting. Underline indicates active bits used. Preliminary Read Channel Design Specification 6.2 d2 0 0 Power Management Control and Change Pump Test(Address 0) d1 0 0 d0*CE N 0 1 Power Management and Circuit Activated Sleep mode (default) Serial Interface and power-on-reset Idle mode Serial Interface and power-on-reset Bias circuits Idle with PLLs active mode Serial interface and poser-on-reset Bias circuits Frequency synthesizer PLL Data sychronizer PLL Servo read mode Serial interface and power-on-reset Bias circuits AGC Filter Pulse Detector Servo Demodulator Servo read with PLLs active mode Serial interface and power-on-reset Bias circuits AGC Filter Pulse Detector Servo Demodulator Frequency synthesizer PlL Data sychronizer PLL Read/Write mode Serial Interface and power-on-reset Bias Circuits AGC Filter Pulse Detector Frequency Synthesizer Data sychronizer Servo with Read/Write circuitry active mode Serial Interface and power-on-reset Bias Circuits AGC Filter Pulse Detector Servo Demodulator Frequency Synthesizer Data sychronizer 0 1 0 0 1 1 01 0 0 1 0 1 1 1 0 6.3 d0 AGC Control (Address 1) AGC Operation Preliminary 0 1 d3 0 0 0 0 1 1 1 1 d6 0 0 0 0 1 1 1 1 (1) Read Channel Design Specification Normal AGC operating mode (default) Disable AGC mode and fix VGA gain d2 0 0 1 1 0 0 1 1 d5 0 0 1 1 0 0 1 1 d1 0 1 0 1 0 1 0 1 d4 0 1 0 1 0 1 0 1 AGC Master Peak Detector Droop for data Mode 154ns 200ns 258ns 334ns 431ns 557ns 719ns 929ns (default) AGC Master Peak Detector Droop for servo mode 154ns 200ns 258ns 334ns 431ns 557ns 719ns 929ns (default) (1) (1) Droop is defined as the nominal time for VPK to hold the peak of an isolated pulse before resetting. d7 0 1 VPK output control Disable VPK output (default) Enable VPK output 6.4 6.5 6.6 d4 Pulse Detector Hysteresis for Data Mode when FMT=0 (Address 2) Pulse Detector Hysteresis for Data Mode when FMT=1 (Address 3) Pulse Detector Hysteresis for Servo Mode (Address 4) d3 d2 d1 d0 Threshold Voltage VTH [V] (2) 0% VH (3) Percent Threshold Level %TH [%] (4) 0 0 0 0 0 0 0 0 0 1 6.1% VH Preliminary d4 d3 d2 d1 d0 Read Channel Design Specification Threshold Voltage VTH [V] (2) 9.1% VH 12.1% VH Percent Threshold Level %TH [%] (4) 0 0 0 0 0 0 1 1 0 1 DHD ) (1 VTH = [x%] VH = [((DHD +1) / 0.33)%] VH % TH = [x%](4V H / Vpp-diff ) 1 1 1 1 (1) (2) (3) (4) 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 87.9% VH 90.9% VH 93.9% VH 97.0% VH DHD is the binary value of the register (default = 48.5%). Absolute threshold voltage derived from reference voltage. VH is either the voltage on the HYS pin or the internal vrh, depending on R0[d4]. Threshold level relative to the filter output amplitude Vpp-diff. For VH = vrh, typically 4vrh = 2.1V. Preliminary Read Channel Design Specification 6.7 d3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 d4 0 1 Filter Cutoff Frequency and Filter Servo Tuning Control (Address 5) d2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Cutoff Frequency 17.0 MHz 13.5 MHz 11.2 MHz 9.6 MHz 8.4 MHz 7.4 MHz 6.7 MHz 6.1 MHz 5.6 MHz 5.1 MHz 4.8 MHz 4.4 MHz 4.2 MHz 3.9 MHz 3.7 MHz 3.5 MHz Cutoff Frequency Servo tuning mode enabled, coarse tuning is enabled Servo tuning mode disabled 6.8 Filter Pulse-Slimming Boost For Data Mode (Address 6) Preliminary Read Channel Design Specification 6.9 d3 Filter Pulse-Slimming Boost For Servo Mode (Address 7) d2 d1 d0 ωza Boost at (1) ω-3dB Boost at (2) Peak Peak Freq. (3) Boosted (4) ω-3dB d7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (1) d6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 d5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ωzb • 8.70 ωc 4.35 ωc 2.90 ωc 2.18 ωc 1.74 ωc 1.45 ωc 1.24 ωc 1.09 ωc 0.97 ωc 0.87 ωc 0.79 ωc 0.73 ωc 0.67 ωc 0.62 ωc 0.58 ωc 0 (default) 0.11 dB 0.45 dB 0.98 dB 1.67 dB 2.48 dB 3.38 dB 4.34 dB 5.32 dB 6.32 dB 7.31 dB 8.29 dB 9.26 dB 10.19 dB 11.10 dB 11.98 dB 0.41 dB 1.37 dB 2.53 dB 3.77 dB 5.01 dB 6.23 dB 7.40 dB 8.53 dB 9.61 dB 10.64 dB 0.87 ωc 1.10 ωc 1.23 ωc 1.31 ωc 1.36 ωc 1.41 ωc 1.42 ωc 1.45 ωc 1.48 ωc 1.50 ωc 1.00 ωc 1.03 ωc 1.08 ωc 1.20 ωc 1.38 ωc 1.63 ωc 1.85 ωc 2.03 ωc 2.16 ωc 2.28 ωc 2.38 ωc 2.47 ωc 2.56 ωc 2.64 ωc 2.72 ωc 2.80 ωc Symmetrical boost. Boost values are relative to the -3dB frequency, ωc . (2) Peak boost values are relative to 0dB. (3) Peak-amplitude frequency values are relative to the -3dB frequency, ωc . (4) Boosted -3dB frequency, ωc-boosted, relative to the unboosted -3dB frequency, ωc . (2) (1) 0dB -3dB (3) 0dB -3dB (4) ωc Figure 21. Filter Frequency Response ωc- boosted Preliminary Read Channel Design Specification 6.10 d5 sign 0 1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Data Synchronizer PLL Window Adjustment and Test Modes (Address 8) d4 range 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 d2 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 d1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 d0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 WIndow Adjustment as a Percentage of the Window 0 (Adjustment bypassed 0 (Adjustment enabled) +/-1% +/-2% +/-3% +/-4% +/-5% +/-6% +/-7% +/-8% +/-9% +/-10% +/-11% +/-12% +/-13% +/-14% +/-15% +/-12.5% +/-13.5% +/-14.5% +/-15.5% +/-16.5% +/-17.5% +/-18.5% +/-19.5% +/-20.5% +/-21.5% +/-22.5% +/-23.5% +/-24.5% +/-25.5% +/-26.5% (1) , default) Preliminary d5 sign 0/1 d6 0 1 d7 0 1 d4 range 1 d3 d2 d1 d0 Read Channel Design Specification WIndow Adjustment as a Percentage of the Window +/-27.5% 1 1 1 1 Data Synchronizer Test Mode disable TEST buffer (default) enable TEST buffer Data Synchronizer Test Mode enable SRD buffer (default) disable SRD buffer 6.11 d6 0 0 0 Frequency Synthesizer Numerator (Address 9) d5 0 0 0 d4 0 0 0 d3 0 0 0 (2) d2 0 0 0 d1 0 0 1 d0 0 1 0 M Not allowed 2 (default) 3 DM DM+1 1 1 1 (2) 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 126 127 128 DM is the binary value of the register. Preliminary Read Channel Design Specification 6.12 d6 0 0 0 Frequency Synthesizer Denominator (Address 10) d5 0 0 0 d4 0 0 0 d3 0 0 0 d2 0 0 0 d1 0 0 1 d0 0 1 0 N Not allowed 2 (default) 3 DN (1) DN +1 1 1 1 (1) 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 126 127 128 DN is the binary value of the register. 6.13 Frequency Synthesizer DAC&Data Synchronizer PLL Loop Filter Bandwidth (Address 11) d4 0 0 d3 0 0 d2 0 0 Ddac 1 1 0 0 1 1 Ddac 1 1 (1) (1) (1) d1 0 0 d0 0 1 wclk 16.0MHz 17.8MHz (16 + Ddac * 56/31) MHz 1 1 0 1 55.7mhz (default) 57.5MHz (24 + Ddac *48/31) MHz 1 1 1 1 1 1 0 1 70.2 72.0MHz Ddac is the binary value of the register. Preliminary Read Channel Design Specification d7 0 0 0 0 1 1 1 1 d6 0 0 1 1 0 0 1 1 d5 0 1 0 1 0 1 0 1 PLL Loop Filter Bandwidth (Programmable Charge Pump Gain Multiplier KG) 1.000 1.143 1.286 1.427 1.571 1.714 1.857 2.000 (default) 6.14 d3 Test Modes (Address 12) d2 d1 d0 Operation Buffer I/O Buffer Enable Filter Bypass AGC Bypas s 0 1 X X 1 Normal operation. (default) AGC bypassed. Filter bypassed. Enable buffer power-up on the filter LP and DIFF outputs. AIN and AIP pin inputs are multiplexed to both the LP and DIFF output buffers for calibrating measurement equipment. Power-up of buffers at the filter LP and DIFF outputs are enabled. Buffers on the filter LP and DIFF outputs are powered down and these pins are now used as inputs to the pulse detector and servo. 0 0 0 0 0 0 X X 1 1 0 X 1 X 1 1 X X X d4 0 1 Pulse detector output control Enable ERD outputs continuously. Enable ERD outputs only when SGT is active (default). d5 0 1 Pulse Detector Operation Normal operation (default) The ERD buffer goes high impedance and the ERD pin is used as an Preliminary d5 Pulse Detector Operation external input to the data synchronizer d6 0 1 d7 0 1 Data Synchronizer Test Mode Read Channel Design Specification SRD pin connects to Data Align cell output (default) SRD pin connects to Pulse Gate cell output Data Synchronizer Test Mode TEST pin connects to T/2 Delay cell output (default) TEST pin connects to Program. Delay cell output. 6.15 Data Readback (Address 15) Function Power Management Control AGC Control Pulse Detector Hysteresis for Data Mode when FMT=0 Pulse Detector Hysteresis for Data Mode when FMT=1 Pulse Detector Hysteresis for Servo Mode Filter Cutoff Frequency and Filter Servo tuning control Filter Pulse-Slimming Boost for Data Mode (ωza, ωzb ) Filter Pulse-Slimming Boost for Servo Mode (ωza, ωzb) Data Synchronizer PLL Window Adjustment and Test Modes Frequency Synthesis Num (M) Frequency Synthesis Den (N) Frequency Synthesis VCO Center Frequency and Data Synchronizer PLL Loop Filter Bandwidth Test Modes Readback 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1111 Preliminary Read Channel Design Specification 7.0 Package 64 pin TQFP Low profile φja : 45 °C/W 48 10mm 37 36 0.5mm <1.6mm 1 10mm 12 13 12mm 24 25 Meets JEDEC specifications MO-136 Figure 22. Package Diagram Preliminary Read Channel Design Specification 8.0 Application Configuration All unused digital input pins must be tied to an appropriate high or low level. 0.1µF VC RE O FL FL DL DL FL DL VS FC VD LK CE SR CL F1 F1 F1 F1 F2 F2 S3 D4 N D K P N N P P N 48 44 40 36 VDD3 TEST RCP FMT ERD RGT VSUB 8 28 FLBP FLBN FDBP FDBN 12 16 20 24 VSS2 0.1µ F VSS4 SLOAD SCLK SDATA SAMPLE SELECT1 SELECT2 SAB SCD VEXT VRS VDD1 4 32 0.1µF VS RB SGW VP H CA CA AI AI VD S1 IA T GT K VS OL G G P N D2 S UB D CS CD 0.1µ F Preamp All unused digital input pins must be tied to an appropriate high or low level. Figure 23. Pinout and Typical External Components