In this homework, you will implement an ALU with the following diagram and given truth table: E Cin E S0 S1 F Cout A F 0 d d 0 0 Cout 1 0 0 A.B* 1 0 1 A+B+Cin** B 1 1 0 2's complement of A 1 1 1 1 1's complement of B 1 S0 S1 * It is not a general multiplication. It is only bitwise multiplication. ** First two bits of the addition is given as output 'F', most significant bit of the addition is given as output 'Cout'. Design and implement different modules for each combinations of selects: S0,S1.During the implementation use only the methods which are shown in P.S. Do not use truth table implementation at any point except multiplexer. Implement your design in VHDL. As homework, give the diagram of your design and VHDL codes. Due to 17/04/2007. But, it is advised to students who take lab section on Monday to finish before the lab.