Sri DantuEE 5325 –Hardware Modeling with VHDLLecture 4VHDL Lexicon, Data TypesSynopsys Simulation Environment3/7/20082VHDL Character Set1. Upper case letters : A -Z2. Digits: 0 1 2 3 4 5 6 7 8 93. Special characters: “ # & ‘ ( ) * + , -. /: ; < = > _ |4. Space character: (20)5. Format effectors:a. Carriage return: (0D)b. Line feed: (0A)c. Form feed: (0C)d. Horizontal tabulation: (09)e. Vertical tabulation: (0B)6. Lower case letters: a -z7. Other special characters: ! $ % @? { \} ^ ‘ { } ~3/7/20083Lexical ElementA sequence of characters that cannot be subdivided, e.g. “end”Along with separatorsform the text descriptionTypes:delimiteridentifiercommentliteral: character, string, bit string, abstract3/7/20084IdentifierName of an object (user defined) or reserved word, e.g. “if”User defined identifiersCharacter sequenceLetters, Digits, Isolated underscore charactersStarts with a letter (VHDL 87)Contains only letters, numbers and isolated underline characters (VHDL 87)Example: ONES_CNT_1ONES_CNT_1 same as ones_CNT_1 (case insensitive)Develop coding stylesUsed to name variables, blocks, procedures, …3/7/20085DelimiterA character that is used to separate lexical elements and has specific meaning in the languageVHDL delimiters:& „ ( ) * + -. /: ; < = > |VHDL compound delimiters: => ** := /= >= <= <> --Meaning of delimiters is context dependent,e.g. A<=B; if(A<=B)3/7/20086SpacingAllowed (some times required) between adjacent lexical elementsTypes:spaceformat effectors (e.g. tab)end of line3/7/20087Comments and LiteralsComment:--Any thing after double dashes is a commentEquivalent to //in C++Character literal -one character between two apostrophe characters„A‟ „&‟String literal -a sequence of characters between two quotation marksExamples: “BLUE” “101011” “ZZZZZZ”Should be in a single lineMulti-line strings should be concatenated with „&‟Similar to „\‟ in C3/7/20088Numeric LiteralsTypes:Abstract -real or integerDecimal LiteralWriting numbers directlyExponents are allowed –use ENegative exponents only with realFirst character should always be a digitBased LiteralSpecify the number along with the baseExponents are allowedBoth the base and the exponent are specified in decimalBit stringString of digits enclosed by quotesInterpreted as a string and not any value3/7/20089Numeric Literal Examples35 --integer, decimal literal35.0 --real, decimal literal3.5e1 --real, decimal literalB"100011" --binary, bit string literalX"23" --hex, bit string literalO"43" --octal, bit string literal16#23# --hex, integer based literal10#3.5#e1 --decimal, real, integer based literal3/7/200810Some Incorrect Cases“1111_1111” –Underscore not allowed in bit type2e-2 –Negative exponent is not allowed on int2,345 –Comma is not valid; use underscore1.1 e1 –No space in specifying a literalCan be interpreted as two lexical elements.25 –First character must always be a number3/7/200811Data TypesSys 1Sys 2bit_vectortype1001integertype9enumerationtypeADDAllow modeling at different levels of abstraction3/7/200812TypeType:a named set of values with a common characteristicAffects the values and the operations that can be doneVHDL is strongly typedUse type conversions for one type to another –typecasting in CSubtype(of a Type): a subset of the values of a type following a constraintType Example:INTEGERset: {…… -3, -2, -1, 0, 1, 2, 3, ……}operations: +, *identities: 0, 1additive inverse: X + -X = 03/7/200813VHDL Type HierarchyTYPESSCALARCOMPOSITEFILEACCESSENUMERATIONPHYSICALARRAYRECORDNUMERICREALINTEGER3/7/200814Numeric TypesINTEGER and REAL allow high level modelingConstrained INTEGER and REAL are a form of error checkingExamples:type INDEX is range 0 to 9; ----an integer typetype VOLTAGE is range 0.0 to 10.0; ----a real typePositive and Natural are pre-defined subtypesCan have ascending and descending ranges3/7/200815Enumerative TypesElements can be either identifiers or character literalsPre-defined attributespos, left, right, low, high, leftof, rightof, pred, succCan have user-defined attributes also3/7/200816BIT: („0‟,‟1‟)BOOLEAN (FALSE,TRUE)BIT and BOOLEAN are not the same type. Implication:if (X) then ----X type BOOLEANif (X = ‘1’) then ---X type BITPredefined Enumerative Types (Package STANDARD)3/7/200817IEEE Standard Logictype STD_ULOGIC ‘U’ --uninitialized‘X’ --forcing unknown‘1’ --forcing 1‘0’ --forcing 0‘H’ --weak 1‘L’ --weak 0‘W’ --weak unknown‘Z’ --high impedance‘-’ --don’t care3/7/200818Physical TypesInteger type with engineering units added,e.g TIME, VOLTAGE,TEMPType TIME in Package Standard, otherwise, user definedRange of type values can be a problem: -2e9 to +2e9 guaranteed by VHDL LRM3/7/200819Type Timetype TIME is unitsfs;ps = 1000 fs;ns = 1000 ps;us = 1000 ns;ms = 1000 us;s = 1000 ms;min = 60 s;hr = 60 min;end units;1.Base unit and derived units may be used in expressions2.‘fs’ is the base unit3.Base unit should be non-fractional4.Other units can be fractional as long as they form integer multiples of base unit3/7/200820ArraysComposite data typeElements are homogenousElements are all of same typeRange of elementsUnconstrained –no specified rangeConstrained –range is constrainedDiscrete rangePre-specified arraysStringsBit VectorsArray of bitsNot the same as INTEGER typeRepresent registers and parallel data paths (linear array of bits)3/7/200821type BIT_VECTOR is array(NATURAL range < > ) of BIT;type STD_LOGIC_VECTOR is array(NATURAL range < >) of STD_LOGIC;Unconstrained NATURAL: indices are from subtype NATURALrange<>: range to be specified3/7/200822Accessing 1D arraysAccess arrays with ()sorted(i)color(1)Array slicesaddress(0 to 15)Slices should be in the same direction as the original array3/7/2008232-D ArraysRepresent RAMs and ROMsApproach 1:type WORD is BIT_VECTOR( 7 downto 0);type TWO_D_ARRAY is array(0 to 255) of WORD;variable MEM: TWO_D_ARRAY;Approach 2:type TWO_D_ARRAY is (0 to 255, 7 downto 0) of BIT;3/7/200824Accessing 2D ArraysApproach 1Use one indexRetrieve a bit vectorApproach 2Use two indicesRetrieve a bit