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Asynchronous Logic Design III \ This Lecture 1. The Final Steps of Asynchronous Circuit Design 2. Asynchronous Examples Asynchronous FSM Design Steps 1. Construct a primitive flow table from the word statement of the problem 2. Derive a minimum-row primitive flow table or reduced primitive flow table by eliminating redundant, stable total-states 3. Convert the resulting table to Mealy form, if necessary, so that the output value is associated with the total state rather than the internal state 4. Derive a minimum-row flow table, or merged flow table, by merging compatible rows of the reduced primitive flow table using a merger diagram. (Note: The solution is not necessarily unique) 5. Perform race-free, or critical race-free, state assignment, adding additional states if necessary 6. Complete the output table to avoid momentary false outputs when switching between stable total states 7. Draw logic diagram that shows ideal combinational next-state and output functions as well as necessary delay elements. Design Example 1 • An asynchronous network has two inputs X1 and one output. X2 Z • The input sequence X1X2=00, 01, 11 causes the output Z to become 1. • The next input change then causes the output to return to 0. • No other input sequence will produce a 1 output. Design Example 1 Step 1: Primitive Flow Table • Primitive flow table: (The final lines…) • Primitive flow table: Only one stable state per row is allowed. Every change in input must cause an internal state change as well as a total state change. X1X2 00 01 11 10 Z State 1(reset) 1 2 - 3 0 State 2(0001) 1 2 4 - 0 State 3(0010) 1 - 5 3 0 State 4(S211) - 6 4 3 1 State 5(S311) - 6 5 3 0 State 6(S311) 1 6 5 - 0 • State 5 & 6 cannot lead to a 1 output without there being a reset first. Class Question 2 • Derivation of Primitive Flow Table Clk G 00 01 11 10 Z State 1 1 3 - 2 0 State 2 1 - 2 0 State 3 3 4 - 0 State 4 - 3 4 1 State 5 1 - - 5 1 State 6 - 3 6 - 0 Class Question 3 (Removal of Redundant States) 00 01 11 10 Z1Z2 • Remove 1 1 7 - 4 1 1 redundant 2 2 5 - 4 0 1 3 - 7 3 11 1 0 states: 4 2 - 3 4 0 0 5 6 5 9 - 1 1 6 6 7 - 11 0 1 7 1 7 14 - 1 0 8 8 12 - 4 0 1 9 - 7 9 13 0 1 10 - 7 10 4 1 0 11 8 - 10 11 0 0 12 6 12 9 - 1 1 13 8 - 14 13 1 1 14 - 12 14 11 0 0 Asynchronous FSM Design Steps 1. Construct a primitive flow table from the word statement of the problem 2. Derive a minimum-row primitive flow table or reduced primitive flow table by eliminating redundant, stable total-states 3. Convert the resulting table to Mealy form, if necessary, so that the output value is associated with the total state rather than the internal state 4. Derive a minimum-row flow table, or merged flow table, by merging compatible rows of the reduced primitive flow table using a merger diagram. (Note: The solution is not necessarily unique) 5. Perform race-free, or critical race-free, state assignment, adding additional states if necessary 6. Complete the output table to avoid momentary false outputs when switching between stable total states 7. Draw logic diagram that shows ideal combinational next-state and output functions as well as necessary delay elements. Design Example 1 Step 3: Convert to Mealy • Expand Output Columns Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State 1(reset) 1 2 - 3 0 - - - State 2(0001) 1 2 4 - - 0 - - State 3(0010) 1 - 5 3 - - - 0 State 4(S211) - 6 4 3 - - 1 - State 5(S311) - 6 5 3 - - 0 - State 6(S311) 1 6 5 - - 0 - - Design Example 1 Step 4: Merger Diagram – Draw a Line From States that can be Written as a Single Row • States in Each Column are the Same • Outputs Don’t Conflict X1X2 2 00 01 11 10 00 01 11 10 State 1(reset) 1 2 - 3 0 - - - 1 State 2(0001) 1 2 4 - - 0 - - X1X2 00 01 11 10 00 01 11 10 State 1,2 1 2 4 3 0 0 - - Design Example 1 Step 4: Merger Diagram 2 Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State 1(reset) 1 2 - 3 0 - - - 1 State 2(0001) 1 2 4 - - 0 - - 3 State 3(0010) 1 - 5 3 - - - 0 State 4(S211) - 6 4 3 - - 1 - 6 State 5(S311) - 6 5 3 - - 0 - State 6(S311) 1 6 5 - - 0 - - 5 4 Design Example 1 Step 4: Merger Diagram 2 Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State 1(reset) 1 2 - 3 0 - - - 1 State 2(0001) 1 2 4 - - 0 - - 3 State 3(0010) 1 - 5 3 - - - 0 State 4(S211) - 6 4 3 - - 1 - 6 State 5(S311) - 6 5 3 - - 0 - State 6(S311) 1 6 5 - - 0 - - 5 4 Circle Groups Where Every Member has a Line to Every Other Member Design Example 1 Step 4: Merger Diagram 2 Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State 1(reset) 1 2 - 3 0 - - - 1 State 2(0001) 1 2 4 - - 0 - - 3 State 3, 5, 6 1 6 5 3 - 0 0 0 State 4(S211) - 6 4 3 - - 1 - 6 5 4 Merge Largest Group First. Then Merge Next Largest NONOVERLAPPING Group Next Until no More States/Groups are Left. Design Example 1 Step 4: Merger Diagram 2 Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State 1, 2 1 2 4 3 0 0 - - 1 State 3, 5, 6 1 6 5 3 - 0 0 0 3 State 4 - 6 4 3 - - 1 - 6 5 4 Merge Largest Group First. Then Merge Next Largest NONOVERLAPPING Group Next Until no More States/Groups are Left. Class Question 1 • Merge the Rows of this Table Inputs: Clk G 00 01 11 10 Z State 1 1 3 - 2 0 State 2 1 - 2 0 State 3 3 4 - 0 State 4 - 3 4 1 State 5 1 - - 5 1 State 6 - 3 6 - 0 Asynchronous FSM Design Steps 1. Construct a primitive flow table from the word statement of the problem 2. Derive a minimum-row primitive flow table or reduced primitive flow table by eliminating redundant, stable total-states 3. Convert the resulting table to Mealy form, if necessary, so that the output value is associated with the total state rather than the internal state 4. Derive a minimum-row flow table, or merged flow table, by merging compatible rows of the reduced primitive flow table using a merger diagram. (Note: The solution is not necessarily unique) 5. Perform race-free, or critical race-free, state assignment, adding additional states if necessary 6. Complete the output table to avoid momentary false outputs when switching between stable total states 7. Draw logic diagram that shows ideal combinational next-state and output functions as well as necessary delay elements. Races • In a feedback sequential circuit, a “race” is said to occur when multiple internal variables change state as a result of a single input variable changing state • If the final state depends on the order in which the variables change, the race is said to be “critical”. Race Free State Assignment • Race-free Means that Only ONE State Value can Change at a Time. If a You are in State 00 and Want to go to State 11, You Must Follow a Path Such as: 000111 OR 0010 11 Design Example 1 Step 5: Critical Race-free State Assignment • Rename States: Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State 1, 2 1 2 4 3 0 0 - - State 3, 5, 6 1 6 5 3 - 0 0 0 State 4 - 6 4 3 - - 1 - Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State a a a c b 0 0 - - State b a b b b - 0 0 0 State c - b c b - - 1 - Design Example 1 Step 5: Critical Race-free State Assignment • With a Single-Bit Input Change How Can the State Change? X1X2 00 01 11 10 00 01 11 10 State a a a c b 0 0 - - State b a b b b - 0 0 0 State c - b c b - - 1 - a c b Design Example 1 Step 5: Critical Race-free State Assignment • Possible State Assignments (What We Called State ID When We Did Sequential Circuit Design): 00 00 a a c b 01 c b 10 11 01 • Race-free Means That Only One Bit Changes Between States… But There is no Assignment That Will Allow This. Design Example 1 Step 5: Critical Race-free State Assignment • Solution: Add a State 00 a c b 01 10 d 11 Design Example 1 Step 5: Critical Race-free State Assignment • Table Derivation – Add State X1X2 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - - State b (01) a b b b - 0 0 0 State d (11) State c (10) - b c b - - 1 - – Add c(d) b Transition Path X1X2 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - - State b (01) a b b b - 0 0 0 State d (11) - b - - State c (10) - d c a - - 1 - Design Example 1 Step 6: Complete Output Table to Remove Glitches • Table Derivation – Fill in Outputs Corresponding to Unstable States to Avoid Momentary False Outputs During Transition Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State a a a c b 0 0 - 0 State b a b b b 0 0 0 0 State d - b - - - 1/0 - - State c - d c a - 1 1 - Shared Row Assignment Example Step 5: Critical Race-free State Assignment • Tool to Help With State Assignment: “Shared Row Assignment” • Random Example: 00 01 11 10 A A B - D B B B C B C - D C D D B D E D E A E E F • Required Transitions: F F D C F – Col 00: E A & D B – Col 01: A B & C, F D – Col 11: B, F C & D E – Col 10: A, CD & E F Shared Row Assignment Example Step 5: Critical Race-free State Assignment • Consider Required Transition: Col 00: E, C A & D B • Could Implement as EA, CA; OR ECA; OR CEA; OR Any One of Many Other Combinations • To Avoid Critical Races, A & C & E State Assignments Must all Only Differ by One Bit. B C A D F E Shared Row Assignment Example Step 5: Critical Race-free State Assignment B • K-maps Again… C A D F E 1 0 • As Many of The Connected States as 00 A E Possible Should be 01 B D Next to Each Other in 11 X C a K-map. 10 Y F Shared Row Assignment Example Class Problem • For the State 1 0 Assignments in the 00 A E K-maps to the right, 01 B D Complete the Table 11 X C Below. 10 Y F 00 01 11 10 A A B - D B B B C B C - D C D D B D E D E A E E F F F D C F Shared Row Assignment Example Class Problem (Don’t Peak!) • Paths That Need to be Looked at: – AD (000101) 000010011111101 – BC (001111) 001011111 – FD (110101) 110 111 101 00 01 11 10 A(000) A B - Y B(001) B B X B C(111) - D C D D(101) B D E D E(100) A E E F F(110) F C C F X(011) - - C C Y(010) - - - X Asynchronous FSM Design Steps 1. Construct a primitive flow table from the word statement of the problem 2. Derive a minimum-row primitive flow table or reduced primitive flow table by eliminating redundant, stable total-states 3. Convert the resulting table to Mealy form, if necessary, so that the output value is associated with the total state rather than the internal state 4. Derive a minimum-row flow table, or merged flow table, by merging compatible rows of the reduced primitive flow table using a merger diagram. (Note: The solution is not necessarily unique) 5. Perform race-free, or critical race-free, state assignment, adding additional states if necessary 6. Complete the output table to avoid momentary false outputs when switching between stable total states 7. Draw logic diagram that shows ideal combinational next-state and output functions as well as necessary delay elements. Design Example 1 Step 6: Complete Output Table to Remove Glitches • Output Derivation Ouput: Z X1X2 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - - State b (01) a b b b - 0 0 0 State d (11) - b - - - - - - State c (10) - d c a - - 1 - Transition 1st State Output Intermediate State Final State Output Output ab 0 0 ba 0 0 cd b 1 0 c a b 1 0 Design Example 1 Step 6: Complete Output Table to Remove Glitches • Table Derivation – Fill in Outputs Corresponding to Unstable States to Avoid Momentary False Outputs During Transition Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - 0 State b (01) a b b b 0 0 0 0 State d (11) - b - - - 1/0 - - State c (10) - d c a - 1/0 1 1/0 Asynchronous FSM Design Steps 1. Construct a primitive flow table from the word statement of the problem 2. Derive a minimum-row primitive flow table or reduced primitive flow table by eliminating redundant, stable total-states 3. Convert the resulting table to Mealy form, if necessary, so that the output value is associated with the total state rather than the internal state 4. Derive a minimum-row flow table, or merged flow table, by merging compatible rows of the reduced primitive flow table using a merger diagram. (Note: The solution is not necessarily unique) 5. Perform race-free, or critical race-free, state assignment, adding additional states if necessary 6. Complete the output table to avoid momentary false outputs when switching between stable total states 7. Draw logic diagram that shows ideal combinational next-state and output functions as well as necessary delay elements. Design Example 1 Step 7: Derive Logic • Logic Derivation Inputs: Ouput: Z X1X2 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - 0 State b (01) a b b b 0 0 0 0 State d (11) - b - - - 0 - - State c (10) - d c a - 1 1 1 • Derivation of Combinational Logic Blocks for Next State and Output. • Delay Placement Design Example 1 Step 7: Derive Logic • Model (I/O) Next PS1 State NS1 PS0 Logic NS0 X1 Output Logic Z X2 Design Example 1 Step 7: Derive Output Logic PS1 X1X2 PS1PS0 Z PS0 X1 Z 0 0 0 0 0 X2 0 0 0 1 0 0 0 1 0 X 0 0 1 1 X 0 1 0 0 0 0 1 0 1 0 Inputs: 0 1 1 0 1 Ouput: Z 0 1 1 1 0 X1X2 1 0 0 0 0 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - 0 1 0 0 1 0 State b (01) a b b b 0 0 0 0 1 0 1 0 1 1 0 1 1 X State d (11) - b - - - 0 - - 1 1 0 0 X State c (10) - d c a - 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 X Design Example 1 Step 7: Derive Output Logic X1X2 PS1PS0 Z 0 0 0 0 0 Z (Output) 0 0 0 1 0 X1X2 0 0 1 0 X PS1 PS0 00 01 11 10 0 0 1 1 X 0 1 0 0 0 00 0 0 X 0 0 1 0 1 0 0 1 1 0 1 01 0 0 0 0 0 1 1 1 0 11 X 0 X X 1 0 0 0 0 1 0 0 1 0 10 X 1 1 1 1 0 1 0 1 1 0 1 1 X 1 1 0 0 X 1 1 0 1 0 ____ 1 1 1 0 1 Z=X1•PS1 + PS1•PS0 1 1 1 1 X Design Example 1 Step 7: Derive Next State Logic PS1 X1X2 PS1PS0 NS1NS0 PS0 NS1 X1 0 0 0 0 0 0 NS0 0 0 0 1 0 0 X2 0 0 1 0 X X 0 0 1 1 X X 0 1 0 0 0 0 0 1 0 1 0 1 Inputs: 0 1 1 0 1 1 Ouput: Z 0 1 1 1 0 1 X1X2 1 0 0 0 0 1 00 01 11 10 00 01 11 10 State a (00) a a c b 0 0 - 0 1 0 0 1 0 1 State b (01) a b b b 0 0 0 0 1 0 1 0 0 0 1 0 1 1 X X State d (11) - b - - - 0 - - 1 1 0 0 1 0 State c (10) - d c a - 1 1 - 1 1 0 1 0 1 1 1 1 0 1 0 PS NS 1 1 1 1 X X Design Example 1 Step 7: Derive Next State Logic X1X2 PS1PS0 NS1NS0 NS1 0 0 0 0 0 0 0 0 0 1 0 0 X1X2 0 0 1 0 X X PS1 PS0 00 01 11 10 0 0 1 1 X X 00 0 0 1 0 0 1 0 0 0 0 0 1 0 1 0 1 01 0 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 11 X 0 X X 1 0 0 0 0 1 1 0 0 1 0 1 10 X 1 1 0 1 0 1 0 0 0 1 0 1 1 X X 1 1 0 0 1 0 1 1 0 1 0 1 ___ ___ 1 1 1 0 1 0 NS1=X1•X2•PS0 + X2•PS1•PS0 1 1 1 1 X X Design Example 1 Step 7: Derive Next State Logic X1X2 PS1PS0 NS1NS0 NS0 0 0 0 0 0 0 0 0 0 1 0 0 X1X2 0 0 1 0 X X PS1 PS0 00 01 11 10 0 0 1 1 X X 0 1 0 0 0 0 00 0 0 0 0 0 1 0 1 0 1 01 0 0 1 0 0 1 1 0 1 1 0 1 1 1 0 1 11 X 0 X X 1 0 0 0 0 1 1 0 0 1 0 1 10 X 1 0 0 1 0 1 0 0 0 1 0 1 1 X X 1 1 0 0 1 0 ___ ____ 1 1 0 1 0 1 NS0=X1•X2•PS0 + X1•PS1•PS0 1 1 1 0 1 0 1 1 1 1 X X Final Circuit ____ PS1•PS0 Z=X1•PS1 + ___ ___ X2•PS1•PS0 NS1=X1•X2•PS0 + ___ ____ NS0=X1•X2•PS0 + X1•PS1•PS0 NS1 PS1 PS0 NS0 X1 X2 Z Class Question Fundamental Mode FB Delay • What feedback delay is required on the last circuit? Completion Signals • How is the done signal generated? Req0 Req1 Req2 Ack0 Handshaking Ack1 Handshaking Ack2 Manager 1 Manager 2 Start1 Done1 Start2 Done2 D1 Q1 Logic1 D2 Q2 Logic2 Start 5ns Start 25ns Completion Signals Delay Elements Logic Block Data Delay Block Done At design time, determine worst case delay from START signal until data is ready and build a block that produces a pulse at completion. Completion Signals Redundant Signal Encoding • Create block such that it has two outputs. While circuit is not stable, output is 0,0. When result is found, output is 0, 1 or 1, 0. Meaning Out 1 Out 2 In Transition 0 0 0 0 1 1 1 0 Illegal 1 1

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posted: | 3/7/2008 |

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