TMS320C6000 McBSP IOM-2 Interface by keara

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									                                                                                                                       Application Report
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          TMS320C6000 McBSP: IOM-2 Interface
Eric Biscondi                                                                                  Digital Signal Processing Solutions

Abstract
This document describes how the multi-channel buffered serial port (McBSP) in the Texas
Instruments (TI™) TMS320C6000 digital signal processor (DSP) is used to communicate to an
ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-compliant device. This document also
describes the usage of McBSP registers and sample code to perform the above function.


                                                                        Contents
Design Problem ...............................................................................................................................................2
IOM-2 Serial Bus..............................................................................................................................................2
McBSP Operation for IOM-2 ............................................................................................................................2
McBSP Register Configuration ........................................................................................................................3
McBSP Initialization .........................................................................................................................................5
Sample Code Setup .........................................................................................................................................6
References.......................................................................................................................................................9


                                                                         Figures
Figure 1.      IOM-2 Simplified Timing Diagram ....................................................................................................2
Figure 2.      Connection Between the McBSP and an IOM-2-Compliant Device .................................................3
Figure 3.      Pin Control Register.........................................................................................................................3
Figure 4.      Sample Rate Generator Register.....................................................................................................4
Figure 5.      Re-Synchronization of CLKG and FSG (When GSYNC = 1) ...........................................................4
Figure 6.      Receive/Transmit Control Register ..................................................................................................5




Digital Signal Processing Solutions                                                                                                              May 1999
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Design Problem
        How do I use the multi-channel buffered serial port to communicate to an IOM-2
        compliant device?


IOM-2 Serial Bus
        The IOM-2 standard defines an industry-standard serial bus for interconnecting
                                 [1]
        telecommunications ICs. The serial bus IOM-2 provides a full-duplex communication
        link containing user control data, control/programming, and status channel.

        The data clock (DCL) is used to clock data and operates at twice the data rate. IOM-2
        frames are delimited by an 8-KHz frame sync signal (FSC). DU/DI (data upstream/data
        downstream) are the up/down serial information streams. The IOM-2 standard defines
        two operating modes:

        H    Line card mode

        H    Terminal mode

        Both modes utilize the same basic frame and clocking structure but differ in the number
        and usage of the channels. The terminal mode consists of three sub-frames. The line
        card mode consists of one to eight sub-frames. The term sub-frame in IOM-2 terminology
        refers to the number of serial words (elements) transferred per frame. A sub-frame
        contains information for an IOM-2 channel.

        Figure 1 shows a simplified timing diagram of an IOM-2 serial bus. The data clock rate is
        16 KHz x N, where N is the number of sub-frames.

Figure 1. IOM-2 Simplified Timing Diagram
                                           Frame n                         Frame n+1

               DCL


               FSC


               DU/DI                                             bit 1   bit 2
                           bit 1   bit 2




McBSP Operation for IOM-2
        The McBSP provides a direct interface to IOM-2-compliant devices. This document
        explains how to interface the McBSP to an IOM-2-compliant device.

        Figure 2 shows the McBSP-to-IOM-2 interface. The IOM-2 clock DCL is used to drive
        McBSP’s CLKS pin. The sample rate generator generates the internal signal (CLKX and
        CLKR). The IOM-2 frame-sync signal is used to drive the McBSP receive frame sync
        (FSR and FSX). The IOM-2 data line, DU and DI, are connected to the McBSP DX and
        DR pins, respectively.




TMS320C6000 McBSP: IOM-2 Interface                                                                  2
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           Figure 2. Connection Between the McBSP and an IOM-2-Compliant Device

                                                     DCL                           CLKS
                                                     FSC                           FSR

                                                                                   FSX
                                                      DU                           DX
                                                       DI                       DR
                                       IO M-2 Com pliant Device              TMS320C6201’s MCSP




           McBSP Register Configuration
                   As shown in Figure 2, FSR, FSX, CLKS, and DR are inputs; DX is an output. To
                   configure the McBSP pins, the pin control register (PCR) must be initialized as shown in
                   Figure 3:

                   H    X/R IOEN = 0. Serial port pins are not general-purpose I/Os.

                   H    FSXM = 0. The frame sync signal (FSX) is derived from the IOM-2 frame sync signal
                        (FSC).

                   H    FSRM = 0. The frame-sync signal (FSR) is derived from the IOM-2 frame-sync signal
                        (FSC).

                   H    CLKX/RM = 1. Receive and transmit clocks (CLKR and CLKX) are driven by the
                        sample rate generator.

                   H    FSX/RP = 0. Frame-sync signal is active high.

                   H    CLKXP = 0. Transmit data is driven on rising edge of CLKX.

                   H    CLKRP = 0. Receive data is sampled on falling edge of CLKR.

           Figure 3. Pin Control Register
31                                                                                                                             16
                                                                  0x0000
                                                                  Reserved

15 14    13       12      11      10          9             8       7          6            5       4     3      2       1          0
 00       0       0        0      0           1             1       0         0            0        0     0      0       0          0
 RSV    XIOEM   RIOEN    FSXM   FSRM       CLKXM      CLKRM       RSV    CLKS_STAT        DX_     DR_    FSXP   FSRP   CLKXP   CLKRP
                                                                                          STAT    STAT

                   As shown in Figure 4, the sample rate generator register (SRGR) is used to configure the
                                                             [4, Chapter 8-5]
                   internal McBSP frame and clock generator:

                   H    GSYNC = 1. Because DCL generates FSC and the internal sample rate generator
                        clock signal (CLKG) is the DCL divided by two, you must synchronize CLKG with the
                        external frame-synchronization signal input (FSR/FSX). This ensures that the McBSP
                        and the external device have the same phase relationship.
                        Figure 5 shows CLKG and the framing signal (FSG). In case 1, the external frame-
                        sync FSC occurs at the rising edge of CLKG; thus, there is no need for




           TMS320C6000 McBSP: IOM-2 Interface                                                                           3
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                 resynchronization. In case 2, however, the rising edge of FSC does not coincide with
                 the rising edge of CLKG. Therefore, resynchronization is necessary.

           H     CLKSP = 0. The rising edge of CLKS generates CLKG and thus CLK(R/X)_int.

           H     CLKSM = 0. The external clock (CLKS) drives the sample rate generator.

           H     CLKGDV = 1. Divide by 2 DCL to determine the bit sample rate CLKG.

           H     The external frame FSC pulse dictates the arrival of a new frame; therefore, the
                 frame period (FPER) and the frame width (FWID) are not programmed.

Figure 4. Sample Rate Generator Register
 31         30           29          28   27                                                                          16
 1           0           0           0                                          0
GSYN      CLKSP         CLKSM    FSGM                                          FPER

 15                                                      8     7                                                      0
                                 0                                                       1
                                FWID                                                   CLKDV


Figure 5. Re-Synchronization of CLKG and FSG (When GSYNC = 1)

       DCL (CLKS)

 FSC (FSR/FSX)

                                               FSC triggers internal frame sync signal FSG
                 FSG
                                                  Rising edge of CLKG coincides with rising edge of FSG

      Case 1: C L K G
  No need to resync                               Synchronized to the rising edge of internal frame sync signal FSG
      Case 2: C L K G
      Needs resync


  DU/DI (DX/DR)                                      bit 1             bit 2              bit 3             bit 4




           As shown in Figure 6, the receive and transmit control registers (RCR and XCR) initialize
           various parameters for the receive and transmit operations:

           H     R/X PHASE = 0. Single-phase frame (R/X FRLEN2 and R/X WDLEN2 are not used.)

           H     R/X WDLEN1 = 101b. 32-bit words

           H     R/X COMPAND = 0. No companding

           H     R/X FIG = 0

           H     R/X DATDLY = 0. No delay between the rising edge of the frame sync and the first
                 data.

           H     R/X FRLEN1 = (N – 1). Depends on which mode is used: one to eight channels when
                                                                                         [1]
                 running in line-card mode; three channels when running in terminal mode.



TMS320C6000 McBSP: IOM-2 Interface                                                                                        4
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Figure 6. Receive/Transmit Control Register
    31        30                        24   23           21      20        19      18      17        16
    0                       0                        0                  0             0          0
R/X PHASE              R/X FRLEN2                R/X WDLEN2       R/X COMPAND     R/X FIG   R/X DATADLY

    15        14                         8   7                5   4                                    0
    0                   (N – 1)                     101                             0
   Rsv                 R/X FRLEN1                R/X WDLEN1                      reserved



McBSP Initialization
         The serial port is configured and initialized via the serial-port control register (SPCR):

         H    /GRST = 1. CLKG is clocking.

         H    R/X INTM = (depends on the application)

         H    R/X RST_ = 1. The transmit/receive operations are enabled.

         H    DLB = 0. The digital loop mode is disabled.

         H    RJUST = 0

         H    CLKSTP = 0. Clock stop mode is disabled.

         Most applications require the DMA (direct memory access) to service the McBSP. In that
         case, the following order in the initialization steps must be respected.

         1)   Initialize all McBSP registers as described in the previous sections.

                             Caution: Do not set /GRST bit in SPCR in this step.

         2)   Select and configure the DMA channel you want to use to service the McBSP.
              Typical settings for the DMA channel would be to use the split mode to service both
              receive and transmit:
              Source address = address of the transmit buffer
              Destination address = address of the receive buffer
              Split-address register = address of the serial port DRR
              Transfer counter = number of elements to be transferred
              Receive or transmit synchronization event, RSYNC = REVT from McBSP
              DMA interrupt bit, TCINT = enabled

         3)   Take the sample rate generator out of reset by setting /GRST=1 in SPCR.

         4)   Enable the CPU interrupt that corresponds to the DMA channel used. (You must set
              the global interrupt enable (GIE) and non-maskable interrupt (NMIE) bits, plus the bit
              corresponding to the DMA channel interrupt you want to use in the IER.)

         5)   Start the DMA.




TMS320C6000 McBSP: IOM-2 Interface                                                                     5
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        6)    The very first frame sync that arrives must wake up the serial port. This is performed
              with the new frame-sync interrupt that can be programmed on the McBSP. (RINTM
              bit field must be set up with 10b, that is, RINT generated by a new frame
              synchronization.)
              The corresponding ISR (interrupt service routine) must wake up the serial port (by
              setting /RRST=1 and /XRST=1 in SPCR) and then disable the new frame sync
              interrupt so that subsequent frame syncs do not cause unnecessary enabling of the
              receiver.

        Depending on the application the user wants to implement, the McBSP multi-channel
                               [4, Chapter 8-6]
        mode may also be used.


Sample Code Setup
        The code included below describes how to initialize the C6000 McBSP to communicate
        with an IOM-2-compliant device operating in the line-card mode. DMA channel 0 is used
        the in split mode to service McBSP 0 receive and transmit operations. For this example,
        consider the terminal mode operation (each frame contains three sub-frames of 32 bits
        each). To simplify the example, a single frame is transferred/received.

        #define FALSE         0
        #define TRUE          1
        #define N             3           /*set up the number of sub-frames */

        volatile int new_fsr;
        volatile int receive_done;

        void
        main(void)
        {
        unsigned int      dma_pri_ctrl         =   0;
        unsigned int      dma_sec_ctrl         =   0;
        unsigned int      dma_src_addr         =   0;
        unsigned int      dma_dst_addr         =   0;
        unsigned int      dma_tcnt             =   0;
        unsigned int      dma_gcr              =   0;
        unsigned int      dma_gcra             =   0;
        unsigned int      dma_gcrb             =   0;
        unsigned int      dma_gndxa            =   0;
        unsigned int      dma_gndxb            =   0;
        unsigned int      dma_gaddra           =   0;
        unsigned int      dma_gaddrb           =   0;
        unsigned int      dma_gaddrc           =   0;
        unsigned int      dma_gaddrd           =   0;
        unsigned int      count_reload         =   0;

             new_fsr = FALSE;
             receive_done =FALSE;

             /* Set up SRGR values as needed */
             InitMcBSP();

             set_interrupts();

             /* Reset DMA control register */
             dma_reset();


TMS320C6000 McBSP: IOM-2 Interface                                                                 6
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            /* Set up Global Configuration Registers for the DMA */
            LOAD_FIELD(&dma_gcra, XFER_SIXE, ELEMENT_COUNT, ELEMENT_COUNT_SZ);
            dma_gaddra = MCBSP_DRR_ADDR(0);
            dma_global_init(dma_gcr, dma_gcra, dma_gcrb, dma_gndxa, dma_gndxb,
                             dma_gaddra, dma_gaddrb, dma_gaddrc, dma_gaddrd);


            /* Initialize DMA channel 0 to service McBSP */
            /* Set up DMA primary control register */
            LOAD_FIELD(&dma_pri_ctrl, DMA_RELOAD_NONE,
                                                   DST_RELOAD,DST_RELOAD_SZ);
            LOAD_FIELD(&dma_pri_ctrl, DMA_RELOAD_NONE,
                                                   SRC_RELOAD,SRC_RELOAD_SZ);
            LOAD_FIELD(&dma_pri_ctrl, DMA_NO_EM_HALT, EMOD,        1);
            LOAD_FIELD(&dma_pri_ctrl, DMA_CPU_PRI,     PRI,        1);
            LOAD_FIELD(&dma_pri_ctrl, SEN_XEVT0,       WSYNC,      WSYNC_SZ);
            LOAD_FIELD(&dma_pri_ctrl, SEN_REVT0,       RSYNC,      RSYNC_SZ);
            LOAD_FIELD(&dma_pri_ctrl, DMA_CNT_RELOADA,CNT_RELOAD, 1);
            LOAD_FIELD(&dma_pri_ctrl, DMA_SPLIT_GARA, SPLIT,       SPLIT_SZ);
            LOAD_FIELD(&dma_pri_ctrl, DMA_ESIZE32,     ESIZE,      ESIZE_SZ);
            LOAD_FIELD(&dma_pri_ctrl, DMA_ADDR_INC,    DST_SRC,    DST_SRC_SZ);
            LOAD_FIELD(&dma_pri_ctrl, DMA_ADDR_INC,    SRC_SRC,    SRC_SRC_SZ);
            SET_BIT(&dma_pri_ctrl, TCINT);


            /* Set up the secondary control register */
            LOAD_FIELD(&dma_sec_ctrl, 1,              FRAME_IE,    1);

            /* Set up Source and Destination Address Register */
            dma_src_addr = (unsigned int) TransmitBuffer;
            dma_dst_addr = (unsigned int) ReceiveBuffer;

            dma_init( DMA_CH0,
                      dma_pri_ctrl,
                      dma_sec_ctrl,
                      dma_src_addr,
                      dma_dst_addr,
                      dma_tcnt);

            DMA_START(DMA_CH0);

            /* Enable sample rate generator; /GRST=1 and frame sync generator*/
            MCBSP_SAMPLE_RATE_ENABLE(0);
            SET_BIT(MCBSP_SPCR_ADDR(0), FRST);

            /* wait for first frame sync to enable receiver */
            while (!new_fsr);

            /* wait until all data is received */
            while (!receive_done);

            while(1);

        }


        void



TMS320C6000 McBSP: IOM-2 Interface                                               7
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        InitMcBSP(void)
        {
        /* PCR setup*/
        LOAD_FIELD(MCBSP_PCR_ADDR(0),1, CLKRM, 1);
        LOAD_FIELD(MCBSP_PCR_ADDR(0),1, CLKXM, 1);

        /* RCR setup */
        LOAD_FIELD (MCBSP_RCR_ADDR(0),   SINGLE_PHASE, RPHASE, 1);
        LOAD_FIELD (MCBSP_RCR_ADDR(0),   WORD_LENGTH_32, RWDLEN1, RWDLEN1_SZ);
        LOAD_FIELD (MCBSP_RCR_ADDR(0),   (N-1), RFRLEN1, RFRLEN1_SZ);
        LOAD_FIELD (MCBSP_RCR_ADDR(0),   DATA_DELAY0, RDATDLY, RDATDLY_SZ);
        LOAD_FIELD (MCBSP_RCR_ADDR(0),   NO_COMPAND_MSB_1ST, RCOMPAND,
                                                               RCOMPAND_SZ);


        /* XCR setup */
        LOAD_FIELD (MCBSP_XCR_ADDR(0),   SINGLE_PHASE, XPHASE, 1);
        LOAD_FIELD (MCBSP_XCR_ADDR(0),   WORD_LENGTH_32, XWDLEN1, XWDLEN1_SZ);
        LOAD_FIELD (MCBSP_XCR_ADDR(0),   (N-1), XFRLEN1, XFRLEN1_SZ);
        LOAD_FIELD (MCBSP_XCR_ADDR(0),   DATA_DELAY0, XDATDLY, XDATDLY_SZ);
        LOAD_FIELD (MCBSP_XCR_ADDR(0),   NO_COMPAND_MSB_1ST, XCOMPAND,
                                                               XCOMPAND_SZ);
        /* SRGR setup */
        LOAD_FIELD (MCBSP_SRGR_ADDR(0), 1, CLKGDV, CLKGDV_SZ);
        LOAD_FIELD (MCBSP_SRGR_ADDR(0), GSYNC_ON, GSYNC, 1);

        /* SPCR setup */
        LOAD_FIELD (MCBSP_SPCR_ADDR(0), INTM_FRAME, RINTM, RINTM_SZ);
        }


        void
        set_interrupts(void)
        {
          intr_init();
          INTR_MAP_RESET;
          intr_map(CPU_INT13, ISN_RINT0);

            /* Hook interrupt service routine to an interrupt */
            intr_hook (c_int08, CPU_INT8);
            intr_hook (c_int13, CPU_INT13);

            /* Enable NMIE and GIE */
            INTR_ENABLE(CPU_INT_NMI);
            INTR_GLOBAL_ENABLE;

            /* default CPU interrrupt & correponding to DMA channel 0 */
            INTR_ENABLE(8);

            /* enable new frame sync interrupt in McBSP1) */
            INTR_ENABLE(13);
        }


        /* DMA DATA TRANSFER COMPLETION ISRS */
        interrupt void
        c_int08(void) /* DMA ch0 */
        {



TMS320C6000 McBSP: IOM-2 Interface                                               8
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            receive_done = TRUE;
            return;
        }

        /* new frame sync interrupt wakes up receive & transmit */
        interrupt void
        c_int13(void)
        {
          new_fsr=TRUE;
          SET_BIT (MCBSP_SPCR_ADDR(0), RRST);
          SET_BIT (MCBSP_SPCR_ADDR(0), XRST);
          INTR_DISABLE(13);
          return;
        }


References
        [1] “ICs for Communications,” IOM-2 Internal Reference Guide, Siemens AG, 1991
        [2] IOM-2 Interfacing on TMS320C54x, Literature number BPRA074, February 1998,
                         Texas Instruments
        [3] ICs for Communications, ISDN Subscriber Access Controller for Terminals, ISAC-
                        STE, PSB2186 User’s Manual, 1994, Siemans AG
        [4] TMS320C6000 Peripherals Reference Guide, Literature number SPRU190, March
                     1999, Texas Instruments




TMS320C6000 McBSP: IOM-2 Interface                                                           9
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TMS320C6000 McBSP: IOM-2 Interface                                                         10
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TMS320C6000 McBSP: IOM-2 Interface                                                                 11

								
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