Monolithic Active Pixel Sensor for Dosimetry Application

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					                          Monolithic Active Pixel Sensor
                           for Dosimetry Application
                                         F.Cannillo, G. Deptuch*, W. Dulinski

                          LEPSI, IN2P3/ULP, 23 Rue du Loess, BP 20 67037 Strasbourg, France
                                           E-mail: cannillo@lepsi.in2p3.fr
                                 *UMM, Al. A. Mickiewicza 30, 30-059 Krakow, Poland




Abstract                                                       back to the gate of M1 via the source follower transistor
                                                               M2. M2 determines also the operation region of the
A Monolithic Active Pixel Sensor (MAPS) prototype              PMOS transistor.
device for real-time dosimetry in brachytherapy
application is presented. A novel charge sensitive                                   I_sf                                                   vdd_sf      vdd_ph
                                                                   gnd                                           M2         vdd_sf
element is used for pixel design. It features a built-in
charge-to-current conversion and allows operation                             I_ph            M1        vdd_ph
                                                                                                                                            M2
mode with charge integration. The two 32ä32 pixel                        +p          +p                   +p           +n                                   M1
arrays prototype design in a standard CMOS process is                                              D2
                                                                                     n-well
presented.
                                                                                                   D1          Ileak                 I_sf
                                                                                                                                                          I_ph
1.     Introduction                                                                                                p-substrate
                                                                         particle track                                                           gnd

This paper focuses on the development of a MAPS for
a 3-D dosimeter1. The sensor will be able to reconstruct       Fig.1: PhotoFET pixel structure.
the 2-D spatial distribution of energy deposited by a
continuous flow of particles springing off an extended
radioactive source. The third dimension will be                Fig.2 shows measurement results on the single cell
provided by rotating the sensor around the source.             photoFET prototype of the Mimosa-IV [2] chip.
Table I shows the main characteristics required on the
sensor.

    Sensitive Area                   70x30 mm2
    Granularity                      50x50 µm2
    Dynamic Range          ≈ 1 MIP /pixel/100 µs (mean)
                                   2

    Radiation Tolerance               2-22 rad/s
    Radioactive source     β emitters (144Ce, 32P, 90Sr/90Y)
                                                                                            (a)                                             (b)
Table I: Brachyteherapy requirements on the detector.
                                                               Fig.2: (a) I_sf vs I_ph for constant photon flux; (b)
                                                               I_ph response to red light LED.
The pixel adopts a novel charge sensitive element
based on a standard PMOS transistor M1 located in a
                                                               There are shown the photoFET current dependence on
floating n-well implanted in the p-type substrate. It
                                                               the source follower bias current, for a given constant
provides a built-in signal amplification achieved by
                                                               photon flux3, and the photoFET current response to the
charge-to-current conversion. The device is called
                                                               varied intensity of the red light from a LED.
photoFET. It was originally proposed for charged
                                                               Section 2 investigates the choice of possible operation
relativistic particle tracking, in the form shown in Fig.1
                                                               modes of the photoFET suited for dosimetry
[2], where the charge-collecting diode is continuously
                                                               application. Section 3 presents a new pixel design, and
reverse biased. The collected charge affects the
                                                               the last Section describes the SUCCESSOR4 2 (S-2)
threshold voltage of M1 through the n-well voltage
potential and hence modulates the output drain current.        chip submitted in 0.35 µm technology process.
The sensitivity is increased applying the n-well voltage

1                                                              3
  Work supported by the European Contract GIRD-CT2001-00561-     Assuming linear dependence between the current and the light
SUCIMA [1].                                                    intensity of the adopted red light LED.
2
  Minimum Ionising Particleº 80 e--h+/µm in silicon.           4
                                                                 SUcima Cmos ChargE SenSOR
                                                                                              µ p W1
2.    PhotoFET for dosimetry application
                                                                                   ID ≈ −
                                                                                               2 L1
                                                                                                              (
                                                                                                        Cox − VGS2 + aVBS1 − VT 0 p        )
                                                                                                                                           2
                                                                                                                                                                     (5)
The operation mode of the photoFET pixel depends on
region in which the PMOS transistor is biased, weak or                             where
                                                                                                  γp
strong inversion.                                                                  a = 1+                                                                            (6)
A linear flux-to-output current sensor response can be                                       2 2Φ F p
obtained combining the logarithmic5 dependence of the
n-well potential VB1 on the intensity of the flux of                               From (5), the relative non-linearity error8, eNL decreases
impinging continuous particles, with the weak                                      when the operation of the device is shifted to higher
inversion exponential current dependence on the bulk                               bias currents that imply larger output current swings. A
voltage VB1. The major drawback of such a solution is                              non-linearity error of 0.56% w.r.t the end point straight
the slow response to flux variations. Collected charge                             line is obtained according to simulation for the input
can be evacuated only through the high value non-                                  signal of 1-10ä103 e-/100 µs/pixel, at the bias condition
linear resistance (order of GΩ) of the lightly forward                             shown in Fig.3. Since a collected charge corresponds to
biased D2 diode. Real time monitoring requires fast                                the variation of the VBS1 voltage, the end point non-
and precise operation, thus the pixel architecture                                 linearity eNL can be derived from relation (5):
adopted in S-2 chip performs charge integration and
                                                                                                          1
has a reset transistor. The linearity of the sensor                                e NL % =                           ⋅ 100
response is achieved biasing the PMOS transistor deep                                                  8 KI BIAS                                                     (7)
in strong inversion, so that the bias point variations due                                      4+
                                                                                                       Ka∆V BS 1
to the physical signal can be considered small w.r.t. the
dc-bias condition. The non-linear dc-relation between
                                                                                   where IBIAS is the bias current of the PMOS transistor
the PMOS drain current and its bulk voltage is
                                                                                   and K = 0.5µ p C ox (W1 / L1 ) .
expressed by equations:
                                                                                   The non-linearity error estimated by (7) using the
             µ p W1                                                                adopted 0.35 µm process parameters, is 1.2% for
I DS1 = −
               2 L1
                             (
                        C ox VGS1 − VT1      )2
                                                                             (1)   ∆VBS1= -55 mV corresponding to the collection of
                                                                                   10ä103 e-.
VT1 = VT 0 p − γ p  2Φ Fp + V BS1 −
                                                   2Φ F p 
                                                                            (2)
                                                          
VGS1 = −VGS 2 + VBS1                                                         (3)                           eNL=0.33%
                                                                                                                                                 Bias conditions
                                                                                                                                               Vdd_sf         3.3V
                                                                                                                                               Vdd_ph         2.8V
                                                                                                                                                I_sf         10µΑ
where VGS26 is the source follower gate-to-source                                                                                               VDM1          1V


voltage shift. Since, the junction capacitance of the n-
well/substrate diode is typically of a few fF the VBS
voltage variation for 10ä103 collected electrons does
not exceed a few tens of mV (neglecting leakage
current). Thus (2), can be approximated7 to:

                          V                  
                          1 BS1              
VT1 = VT 0 p − γ p 2Φ Fp                                                 (4)
                          2 2Φ Fp            
                                                                                 Fig.3: Least squares best fit straight line non-linearity
                                                                                   error for simulated data.
A quadratic dc-relation between the bulk-to-source
voltage and the output current of the PMOS transistor                              The smaller value, obtained from simulation, results
is obtained to a first approximation substituting (3) and                          from taking into account the mobility degradation of
(4) in (1).                                                                        the PMOS with its |VGS| voltage. The use of the end
                                                                                   point straight line overestimates of 40% the non-
5                                                                                  linearity error w.r.t. a least squares best fit straight line
 With reference to Fig.1:
                                                                                   (Fig.3). The achieved linearity is satisfactory for
VDD − V B1      I Φ + I S D1 
           ≅ ln                                                                  dosimetry application.
   VT           IS           
                     D2      
where ISDx term represent the reverse saturation current of diode Dx
(x=1,2), IΦ is the current generated by a flux Φ of MIPs per time unit             8
                                                                                    Relative non-linearity error:
and per area unit that impinges on a pixel sensor area AS:
                                                                                                    max           { I OUT − I OUT }
                                                                                                                      act     lin

 I Φ = Φ ⋅ MIP ⋅ t epi ⋅ q ⋅ AS , where q is the electron charge and tepi is the   e NL % =
                                                                                            input _ signal _ range
                                                                                                                                    ⋅100
epitaxial layer thickness determining the thickness of the active                                      I OUTmax − I OUTmin
                                                                                                         act           act


volume.                                                                            where I OUT is the actual (Spice simulated or based on a calculated
                                                                                           act
6
    VGS2 assumed constant for the rest of the analysis because
dependent in first approximation on the fixed bias current.                        non-linear relation) output current and I OUT is the linear
                                                                                                                                    lin

7
  Taylor expansion of the square root term in (3) limited to the linear            approximation (end point straight line or least squares best fit straight
term.                                                                              line).
3.        Pixel Design                                                                                           source/drain n+ diffusions: this avoids a thick oxide
                                                                                                                 around the n+ diffusions and allows a rectangular-like
              vdd                                     vdd             vdd_ph                                     layout at the same time (Fig.5(b)).
                                                                              M3              reset_b            Fig.4(b) shows the basic timing diagram used to drive
  MR1                     MB4
                                                      M2
                                pwr_on_sf                             M1                    C1
                                                                                                                 the pixel. After the integration period the pixel is
                                                                                                                 activated in two phases: first the source follower is
                                                                                   C2         pwr_on
                    MB3
                                          V_bias_sw
                                                        M4          MS1
                                                                                                                 turned on by connecting the gate of M4 to the gate of
                                   MB1
            I_sf                                                                                                 MB3 through the switches MB1 and MB2 and then turning
                      pwr_on_sf_b               MB2                                     Basic Timing Diagram
                                                            pixel            (b)
                                                                                           Integration period
                                                                                                                 on the PMOS transistor M1 through the switch MS1
             gnd                                                    I_ph         Clk

    current_ref           sf_bias_switches
                                                                            read-out
                                                                             reset_b
                                                                                                       …
                                                                                                       …         (read-out phase). In the implementation of the pixel
                                                                           pwr_on_sf                   …         matrix, the cell sf_bias_switches (Fig.4) is common for
                                          (a)                                pwr_on                    …
                                                                                                                 all pixels in a row. Thus, the source follower M2 needs
                                                                                                                 to be turned on a few clock cycles before M1 because
Fig.4: (a) Pixel and external (w.r.t. the pixel) bias                                                            of time required by the gate of M4 to charge up.The
circuitry schematic diagram; (b) basic timing diagram.                                                           transient simulation results in Fig.6 show the charge
                                                                                                                 integration performed by the n-well and the resulting
                                                                                                                 variation of the photoFET current.
Fig.4(a) shows the pixel and its bias circuitry schematic
diagram as they are implemented in the S-2 chip. The                                                                      Ι1                       ∆IOUT=I2-I1=340nA                 Ι2
pixel operates in switched mode, i.e. it is biased only
when being addressed closing the switch MS1 and the
external switches (w.r.t. the pixel) MB1-MB2. The new
element w.r.t schematic shown in Fig.1 is the PMOS
reset transistor M3. It is placed in the same n-well as M1
not to spoil charge collection performances (100% fill                                                                             2 injections of 1000e-
                                                                                                                                                            Integration period
factor). The connection drain-bulk of M3 reduces its
threshold voltage because of bulk effect. This                                                                                                                                   )




guarantees efficient reset operation.
The capacitors C1 and C2 are used to increase the                                                                Fig.6: Transient simulation: charge collection on the n-
dynamic range of the n-well potential variation and to                                                           well.
compensate for the unwanted VDM1/n-well coupling
when the pixel turns on, respectively. The capacitive
couplings are achieved with polysilicon extended on                                                              4.     SUCCESSOR 2 chip
the n-well surface as shown in Fig.5.
                                                                                                                 4.1.    Chip design
          V_bias_sw          gnd
                                                                                                                 Two photoFET-based matrices are implemented in the
                                                                                               ELT
                                                                vdd_sf                                           S-2 chip, i.e. matrix_single and matrix_ganged.
                                                                                          D
                                                M2                                            G                  Matrix_single is made up of 32ä32 basic pixels with
                    M4
                                                                                                   S
                                                                                                                 40 µm pitch. Matrix_ganged (Fig. 7) is made up of
                                                                                                                 32ä32 super-pixels laid out with a pitch of 40 µm.
12.5 µm




                                                C1                   reset
                                                                                    Polysilicon ELT              Each super-pixel consists of 3ä3 basic photoFET pixels
                                                  M3
                                                                vdd_ph
                                                                                                    G D
                                                                                                                 with current outputs ganged together (wired OR).
                                                                                              S

                    MS1                           M1
                                                                                                  n+ diffusion
                                                                                                  polysilicon
                                                C2

                                                      N-well                                       (b)
                      pwr_on                                         I_ph
                                    (a)
                                                                                                                           40 µm




Fig.5: (a) Pixel layout; (b) ELT and PELT principle.

The activity of the monitored radioactive source is in
the GBq range, imposing high radiation tolerance
requirement on the circuit. Special layout techniques
are used to increase the radiation hardness (Fig.5(a)).
P+ guard rings disable leakage paths between NMOS
transistors. Enclosed Layout Transistors (ELTs) [3] are
                                                                                                                                              Ganged current
used for M4 and MS1 to eliminate any parasitic path
between n+ diffusions of the same NMOS devices. Due                                                              Fig. 7: Super-pixel layout (3ä3 basic pixels).
to the aspect ratio smaller than unity required for the
                                                                                                                 The analogue information is read out in successive
source follower a new Polysilicon ELT (PELT) layout
                                                                                                                 clock cycles, selecting a row and then reading each
is adopted. The polysilicon gate is placed around the
column by turning on sequentially the column switches                                       fixed in closed loop. The amplifier is built with a
at the bottom of the matrix (Fig.8). A pipeline approach                                    source follower input stage MA1, that drives a telescopic
has been adopted to increase the effective read-out                                         cascode gain stage MA4-MA7. In order to increase the
speed: all odd columns are multiplexed on the first                                         output resistance, a gain boosting MA3 is applied to the
read-out line and all the even columns onto the second                                      NMOS cascode transistor MA5.
one. As shown in Fig.8, two read-out lines go to two
transimpedance amplifiers. The most part of the pixel                                                              vdd
                                                                                                                          v_p1         MA8 v_p1     MA7
dc-bias current is subtracted by a constant currents
ICOMP1,2, so that the dynamic range of the current-to-                                                                                     v_p2     MA6
voltage converters is not wasted. Their output lines are
                                                                                                                                                          output
switched alternatively to the output amplifier (A=2) by                                              input               MA1                        MA5
means of two transmission gates.
                                                                                                                                 MA3

                                       (31,31)
                                                 pixel                                                       v_n         MA2                        MA4

                                                              reset_b<xx>                                          gnd
                                                              pwr_on<xx>
                                                              row_select_b<xx>
                                                              V_bias_sw<xx>                 Fig.9: Single ended input amplifier.
                                                              column_select_b<xx>
           …
                 …

                       …

                           …


                                   …




                               …                             clk
                                                                                            The stability, during resetting, is provided by the load
                                                               CF
                                                                          clk_b             of the column line common to all the pixels in each
               (0,0)                               ICOMP1
sf_bias_switches               …                            clk_b                     out
                                                                                            matrix column.
                                                                    clk           A
                                                               CF

Column switches                                    ICOMP2
                                                                          clk_b             Conclusions

Fig.8: Pixel matrix read-out schematic in S-2 chip.                                         A MAPS device dedicated to the real-time dosimetry
                                                                                            application has been presented. Taking into account the
                                                                                            dosimetry requirements, a new pixel design has been
The digital circuitry allows the use of two different                                       developed. Characteristics of the submitted S-2 chip
read-out timings: frame and shutter mode. In the frame                                      are summarized in Table II.
mode the matrix is read-out completely before being
reset, while in the shutter mode, each row is reset after                                                    Matrix_single                                   32ä32 pixels
                                                                                            Matrix size
it has been read. Shutter read-out mode allows a                                                             Matrix_ganged              32ä32 super-pixels (96ä96 pixels)
constant integration time for each pixel row.                                               Pixel Size                                                     12.5ä12.5µm2
                                                                                            N-well area                                                         28.7 µm2
4.2.       Transimpedance amplifier                                                         N-well perimeter                                                      20 µm
                                                                                            Total n-well node capacitance              ~30 fF @ 3 V (10ä103 e-Ø55 mV)
                                                                                            Read-out frequency                                                   10 MHz
The simplest way to convert an input current to an                                          Transimpedance Amp. Gain                                             250 KΩ
output voltage avoiding the use of a large value resistor                                                                              Gain                        73 dB
                                                                                            Single Ended Input Amplifier
is an integrating transimpedance amplifier. The                                                                                        ω0     400 MHz w/ 2 pF col. load
integrating transimpedance amplifier converts an input                                      Table II: Characteristics of the S-2 chip.
current to an output voltage by integrating the current
on the feedback capacitor, CF. The effective                                                Acknowledgments
transimpedance gain is TINT/CF, where TINT is the
integration time.                                                                           We thank M. Szelezniak for help in measurements.
The linearity of the integration depends on the
bandwidth of the amplifier. Considering a single pole                                       References
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integrating a constant current IIN, is equal to:                                            [1]       M. Alemi et al., “SUCIMA: a Silicon Ultra
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                                    −
                                        t
                                                                                          Applications”, 8th Topical Seminar on Innovative
             I
vOUT (t ) ≅ − IN       t − 1   1 − e ω 0                                          (8)   Particle and Radiation Detectors, Siena, Oct. 2002.
             CF         ω0                         
                                                                                        [2]       G. Deptuch, “New Generation of Monolithic
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This is a self-referenced circuit with the input voltage                                    [4]       F. Cannillo, “Design of a 12-bit Successive
                                                                                            Approximation Analog-to-Digital Converter”, Diploma
9
 ω0≈A0|s1|à|s1|, where A0 is the amplifier dc gain.                                         thesis, Politecnico di Bari, Bari, Italy, 2001.