sales increase

Document Sample
sales increase Powered By Docstoc
					Increase Sales
Target Your Marketing to Power Users in the $4.0 Billion Advanced IC Design Market

The ONLY Media Network Dedicated to the IC Design Market
Affiliate Sponsors:

2007 Media Kit
Published by

Editorial Focused Entirely on the Advanced Design Market
Editorial Leadership
The editorial team focused on Chip Design’s media network includes the most respected editors in the technical community. Every issue offers timely staff written articles and contributed pieces from industry experts and analysts.

Chip Design, published bimonthly, covers all of the technical challenges and implementation options that engineers face in the development and manufacture of today’s complex integrated circuits (IC). Key focus areas includes the Electronic Design Automation (EDA) tools and semiconductor industry development processes used in the creation of System-on-Chip (SOC) devices. Chip Design enables architectural, design and verification engineers and their managers to better navigate the challenges that await them in the modern IC (digital and analog) design environment. 2007 Chip Design Editorial Calendar

John Blyler, Editor-in-Chief
As the chief editorial visionary for all of the Chip Design properties, John Blyler is a leading authority on the technological issues that drive today’s advanced EDA and semiconductor industries. John has worked in the electronics industry for over 23 years, most recently holding editorial positions on Chip Design Magazine and Wireless Systems Design. He has written a book (Wiley-IEEE) on systems-level design. John remains an affiliate professor in Systems Engineering at Portland State University.

Dec/Jan (2007)

Focus Report
• Buyers’ Guide Issue • DFM/DFY and Litho

Key Editorial Topics
• FPGA Prototyping • Power Systems • IP Issues • Wireless-RF • Architectural Design • Multicore-Multiprocessors • Encryption • IP Integration • Cadence/ Partners Interoperability Guide • Power Systems • RF Design • Interface Issues • Security • IP Solutions Guide

Show Ad Materials Distribution Close Deadline
• Embedded World 2/22 • DesignCon • DVCon • Multicore Expo • ESC Silicon Valley Dec 6, 2006 Dec 13, 2006

Clive “Max” Maxfield, Executive Editor, Chip Design / iDesign
Clive is a well-known writer and speaker in the EDA community. He is the President of TechBites Interactive ( Max is the author of numerous books, including “EDA: Where Electronics Begins,” “Bebop to the Boolean Boogie,” and “How Computers Do Math.”


Feb 12

Feb 16

Cheryl Ajluni, Senior Editor
Cheryl is a contributing editor and freelance technical writer. She has over 12 years experience covering the high-tech industry for such publications as Electronic Design and Embedded Systems Development and served as Editor in Chief of Wireless Systems Design.

• Special Guide Insert April/May • AnalogRF and Wireless • Special Guide Insert June/July


Mar 24

Mar 28

Pallab Chatterjee, Senior Editor
Pallab is an independent consultant (www. in the EDA, Mixed Signal and custom design space since 1985. In addition to several hundred tapeouts, he has participated on industry and user group conference committees and the technical board for several EDA & Semiconductor companies.

Jim Kobylecky, Technology Editor
Jim has worked as a technical writer and copy editor for such high-tech firms as Mentor Graphics, Tektronix, Credence, Merix, Intel and Atmel. He has received national awards for his training materials and copywriting.

• IP • Hardware Implementations Integration • System Language • Nanotechnology • Analog Mixed Signal • Special Insert Annual Product & Service Resource Catalog


May 11 May 15

Nicole Freeman, Technology Editor
Nicole’s editorial experiences include technologyfocused websites and e-newsletters for AlwaysOn, IBDNetworks, GameSpot (CNET Networks), and ZDNet. She worked 10 years for Miller Freeman publications in the high-tech division. Nicole was also managing editor for Embedded Systems Programming magazine.


• Processors • Analog Design • Power Management • IP Issues • Lithography • Special Guide Insert •Mentor Graphics/ Partners Interoperability Guide

• ESC Boston • ARM Conference

Aug 30

Sept 5

Editorial Board
Tom Anderson, Consultant Cheryl Ajluni, Consultant, Custom Media Solns Karen Bartleson, Stds Manager, Synopsys Chuck Byers, Director Communications, TSMC Pallab Chatterjee, Consultant, Silicon Map Rich Faris, Vice President Marketing, Real Intent Kathryn Kranen, CEO, Jasper Design Automation Barry Marsh, Vice President Marketing, Actel Tom Moxon, Consultant, Moxon Design Walter Ng, Senior Director, Design Services, Chartered Semiconductor Scott Sandler, CEO, Novas Software Steve Schulz, President, Si2 Adam Traidman, President, ChipEstimate


• Verification • Founday issues • IP Integration • Implementation Strategies • Programmable hardware • Special Guide Insert • Synopsys/ Partners Interoperability Guide • ESL • DFY • Verification • Analog-RF-Wireless


Oct 2

Oct 5


• Buyer’s Guide Issue

• DesignCon 2008

Dec 3

Dec 7

Contact Karen Popp for information @ 415-255-0390 xt. 19

Email Newsletters – Reach Targeted Audiences with Relevant Content and News
Chip Designer e-Newsletter 30,000+ Subscribers Email Newsletter Calendar 2007
Chip Designer newsletter
Nov’06 Dec’06 Jan’07 Feb’07 Mar’07 Apr’07 May’07 Jun’07 Jul’07 Aug’07 Sep’07 Oct’07 Nov’07 Dec’07

System-on-Chip (SoC) digital and analog designers, system architects, IP integrators, DFM and verification engineers will benefit from the latest news, industry viewpoints and technical articles. Covers such timely topics as ESL, IP, analog mixed signal, power, DFM-DFY, nanotechnology and more.

Feature Topic

Ad Close Nov 15 Dec 6 Jan 17 Feb 14 Mar 14 Apr 11 May 9 Jun 13 Jul 18 Aug 15 Sep 12 Oct 17 Nov 14 Dec 12

Materials Nov 24 Dec 15 Jan 19 Feb 16 Mar 16 Apr 13 May 11 Jun 15 Jul 20 Aug 17 Sep 14 Oct 19 Nov 16 Dec 14

Performances Challenges Future Trends IP Integration

FPGA Developer e-Newsletter 45,000+ Subscribers

SoC Design
Programmable HW Analog-RF-Wireless Virtual Platforms

Keeps design and test engineers updated on the latest products and technology advances in the growing world of FPGAs, PLDs and Structured ASICs. All aspects of hardware implementation, EDA software and IP design-test issues are covered.

Prototyping ASICs IP Challenges Advanced Chip Verification Design-for-Manufacturability Performances Challenges

Wireless Chip Designer e-Newsletter 25,000+ Subscribers

FPGA Developer newsletter
Issue Nov’06 Dec’06 Jan’07 Feb’07 Mar’07 Apr’07 May’07 Jun’07 Jul’07 Aug’07 Sep’07 Oct’07 Nov’07 Dec’07 Feature Topic Design for Advanced Verification Year in Review
Design/Verf in Consumer Electronics

Both analog and digital engineers need the latest in mixed signal and analog-RF-Wireless news, industry insight pieces and technical guides. The Wireless Chip Designer e-newsletter provides essential content to help in the integration of analog designs into digital SoCs.

Ad Close Oct 25 Nov 22 Jan 10 Feb 7 Mar 7 May 2 Jun 6 Jul 11 Aug 8 Sep 5 Oct 10 Nov 7 Dec 5

Materials Nov 3 Dec 1 Jan 12 Feb 9 Mar 9 Apr 6 May 4 Jun 8 Jul 13 Aug 10 Sep 7 Oct 12 Nov 9 Dec 7

Optimizing FPGA Design Process FPGA/PCB Integration IP/Reuse Trends
RF-Wireless Apps

Using FPGAs with embedded DSPs Apr 4

Sponsoring Chip Design email newsletters offers unique and measurable ways to get in front of targeted audiences of influencers and decision makers. Newsletter marketing options:
n Platinum—468x60 banner at top center position and first 100 word text ad
position and two trackable headline links within the newsletter. and one trackable headline links within the newsletter. and one trackable headline links within the newsletter. text ad position

Development Tools Prototyping with FPGAs High-Speed I/O Issues Design/Verification Issues in Automotive Apps Advanced Verification High-Speed Computing

n Gold—Top 125x125 side banner position, second 75 word text ad position n Silver—Top 125x125 side banner position, second 75 word text ad position n Bronze—Third from top 125x125 side banner position and fourth 30 word
Wireless Chip Designer newsletter
Issue Nov’06 Dec’06 Jan’07 Feb’07 Mar’07 Apr’07 May’07 Jun’07 Jul’07 Aug’07 Sep’07 Oct’07 Nov’07 Dec’07 Feature Topic Basestation Design Emerging Design Trends
Wireless SoC

Ad Close Nov 1 Nov 29 Jan 24 Feb 21 Mar 21 Apr 18 May 16 Jun 20 Jul 25 Aug 22 Sep 19 Oct 24 Nov 16 Dec 14

Materials Nov 10 Dec 9 Jan 26 Feb 23 Mar 23 Apr 20 May 18 Jun 22 Jul 27 Aug 24 Sep 21 Oct 26 Nov 20 Dec 18

Customized Email Newsletter Program – Our teams do it all! Chip Design’s editors will help customize your content, while our web design team places your banners and announcements, all of which goes to our subscriber list to reach your target markets. Optional Bonus: Additional distribution to email list you provide (up to 20,000) Custom email newsletter program: $9,500 single edition rate $7,500/4x rate

Power Amp Design Wireless PCB
IP Integration RF-Wireless Designs

Emerging Architectures

Antenna Design Low Power (mobile)
Analog-RF-Wireless Testing Emerging Mobile Protocols FPGAs/PLDs for Wireless

Targeted Online Advertising, Lead Generation Programs and Resource Catalogs
Chip Design Website
Stay on top of the latest technical product news, read about today’s technology trends, find detailed technical articles, enjoy techie-style blogs and more at www. This dynamic site is also the home of iDesign, the popular subscription publication that provides engineers with weekly insights into the world of EDA and semiconductor chip development.

Online Advertising Generates Targeted Awareness provides online marketers with efficient, effective and low-cost opportunities to capitalize on extremely targeted traffic.

n Basic Site Membership—Members post unlimited product announcements, case studies
and white papers across All articles will also be showcased in appropriate Chip Design email newsletter issues. $3,950 per year, $2,500 for 6 months. 125x125 banners on $7,500 per year, $4,500 for 6 months.

n Gold Site Sponsorship—Supplement your annual membership privileges with rotating n Platinum Site Sponsorship—annual membership privileges plus a rotating leaderboard banner on
PLUS a quarterly dedicated email broadcast to 30,000 subscribers. $19,500 per year, $11,950 for 6 months. multiple white papers, case studies and high value editorial to a targeted audience

n Custom Sponsorships and Microsites—Own a prominent position on the home page of and present n Targeted banner options—Maximum exposure across with banners including:
• Leaderboards (728x90)	 • Tiles (125x125)	


• Banner (468x60) • Skyscrapers (160x600)

High Quality Lead Generation
Chip Design now offers the most targeted lead generation programs for reaching design engineers and engineering managers developing advanced semiconductor designs including:

n Chip Design White Paper Program—An effective lead-generation vehicle that delivers your message via streaming audio and
PowerPoint® presentations for a content-rich experience. contact information and demographics.

n Contest Sponsorship and Surveys—Sponsor a contest, create a survey of up to 10 questions and generate leads including

Don’t Be Left Out of these Important Resource Catalogs
Resource Catalogs include valuable application articles, industry perspectives and comprehensive details on products, services and technologies in an easy to use data sheet format. Distributed in print, online and email newsletter formats each Resource Catalog is designed to help over 60,000 well-qualified engineers, embedded developers and chip designers make design trade-offs and purchasing decisions all year long.

2007 Resource Catalogs
MIPS Embedded Resource Catalog IP Solutions Resource Catalog Chip Design Resource Catalog
Intellectual property for IC Design and Verification

Pub Date
February April June

Space Deadline
February 9 April 3 May 16

Materials Deadline
February 14 April 7 May 18

Targeted Reach
Engineers, designers and embedded developers using the MIPS architecture SoC designers, verification, engineers and system architects Advanced IC designers

FPGA and PLD Solutions Resource Catalog


August 1

August 8

System architects, embedded developers, field engineers, ASIC prototypers and project engineers

Reach Powerful Buyers with Targeted Distribution
40,000 Important Readers
Chip Design is distributed in print to over 25,000 design engineers and engineering managers working on advanced SoC designs. Each issue is also distributed electronically to an additional 15,000 design engineers/managers. Chip Design’s readers are chip, programmable logic device and IPrelated architects, designers, and testers. The readership also includes software protocol-application engineers and technical program managers. These architect-design-test engineers and managers are responsible for creating the latest generations of ASICs, structured ASIC, ASSPs , FPGAs, memory cores and SoC devices.

Powerful Purchasing Influence
System architect, design and test engineers and engineering managers working on advanced SoC designs—Chip Design readers—account for a third of all design engineers. These key enablers influence the purchase of nearly 80% of the total EDA market—or about $4 billion.
*Source: Dataquest/Gartner

Circulation Breakdown by Job Responsibility

8% 11.5% 55.6% 24.9%

Engineering 55.6% Engineering Management 24.9% Executive and other Management 11.9% Other (R&D etc.) 8%

Over 30% of Chip Design readers influence, specify or authorize the purchasing at companies with revenues of over $500 million.

Circulation Breakdown by Purchasing Responsibility

Specify/Authorize/ Influence the purchase of Design Automation tools and software

Specify/Authorize/ Influence the purchase of ASICs, FPGAs and PLDs

Specify/Authorize/ Influence the purchase of Intellectual Property

Specify/Authorize/ Influence the purchase of Standard ICs Services

Specify/Authorize/ Influence the purchase of Test Equipment/ Development Tools

Participate on a regular basis with premium display advertising, online advertising, inserts, advertorials and sponsorships
EDA Consortium, FSA, OCP-IP, Si2 and VSI Alliance Members Save 20%­—place your order before December 31, 2006

Chip Design Magazine
1 x RATE 3 x RATE 6 x RATE

Solution Provider Advertorials / White papers
Showcase your company as an important solutions provider with articles, case studies, and white papers positioned in the special Solution Provider section of Chip Design magazine, on and in the email newsletters.
1 x RATE 3 x RATE 6 x RATE

Full Page 2-Page Spread 1/2 Page (horiz. or vertical) 1/3 Page (vertical only) 1/4 Page

$4,500 $6,500 $3,050 $2,150 $1,625

$4,125 $5,800 $2,775 $1,900 $1,440

$3,750 $5,000 $2,500 $1,700 $1,275

Add this percentage for Premium Positions
Back Cover - 20% Inside Front Cover - 15% Inside Front Cover Spread - 15% Opposite Inside Front Cover (1st right page) - 10% Inside Back Cover - 5% Opposite ToC - 5% Opposite Editorial Page - 5% Center Fold 2-Page Spread - 5%

1-Page Article 2-Page Article (spread w/Ad okay)

$2,500 $4,500
1 x RATE

$2,000 $3,500
3 x RATE

$1,500 $2,500
6 x RATE

Product Showcase
Full Page Data Sheet 1/2 Page 1/4 Page

$3,000 $2,000 $950
1 x RATE

$2,250 $1,500 $855
3 x RATE

$1.500 $750 $750
6 x RATE

Recruitment Advertising
1/2 Page Classified Ad 1/4 Page Classified Ad 1/8 Page Classified Ad

$895 $495 $275

$670 $370 $250

$500 $300 $200

Internet Advertising and Lead Generation Programs
Banners and Links Lead Generation Programs
Chip Design White Paper Program Custom Microsites - 3 mon min.
OnlInE Only W/ PRInT AD

	 			$3,000 per year/ $2,000 six months Gold Site Sponsorship	 	 	 	 $7,500 per year/ $5,000 six months Platinum Site Sponsorship	 $15,000 per year/ $10,000 six months
See program details within Media Kit

Annual Site Membership	

per month

per month

per month

per month

Leaderboards (728x90) Skyscrapers (125x600) Banners (468x60) Panels (125x125)

$200 cpm $225 cpm $175 cpm $100 cpm

$160 cpm $180 cpm $150 cpm $75 cpm

Contest/Survey Sponsorship - 3 mon min $2,000
per month

per month

E-Mail Newsletters

Annual Resource Catalog
Product / Service Data Sheets
Full Page Data Sheet Additional Data Sheet Matrix Page 1/2 Page Data Sheet

Roadblock/exclusive Limited to one sponsor

468x60 banner at top center position; side banner 125 x up to 728; up to three text ads; up to five industry announcements. Optional bonus: additional distribution to your email lists (up to 20,000)



$1,495 $1,175 $2,000 $995

Platinum Sponsor Gold Sponsor

468x90 banner at top center position and first text ad Top 125x125 banner position and second text ad

$3,000/issue $2,000/issue $1,500/issue

$2,600/issue $1,750/issue $1,250/issue

Display Advertising or Advertorials
2-Page Spread Full Page 1/2 Page $3,750 $2,750 $2,000 $5,000– 10,000

Silver Sponsor

Second from top 125x125 banner position and third text ad Third from top 125x125 banner position fourth text ad

$1,000/issue $850/issue

Bronze Sponsor

Various levels that put your logo on the cover and include multiple pages within the Catalog. Contact Karen Popp for more information.

About Extension Media Extension Media is a publisher of business-to-business magazines, resource catalogs and web sites that address high-technology industry platforms and emerging technologies such as embedded systems, chip design, intellectual property, software and infrastructure, architectures and operating systems.

Advertising / Marketing Karen Popp Associate Publisher, Sales Director +1 (415) 255-0390 ext. 19 Article / Abstract Submission John Blyler Editor-in-Chief +1 (503) 614-1082

1786 18th Street San Francisco, CA 94107 Tel: +1 415.255.0390 Fax: +1 415.255.9214