Senior Design Project Title (20pt)

Document Sample
Senior Design Project Title (20pt) Powered By Docstoc
					    Fuzz Box

Project Design Report

    Design Team #3

     John DeBacco

      James Kunc

     Eric Marinucci

      Paul Smith

   Dr. Oke C. Ugweje

   December 5, 2005
Table of Contents

Table of Contents                                            2
List of Figures                                              3
List of Tables                                               4
List of Equations                                            5
Table of Listings                                            6
Abstract                                                     7
Introduction                                                 8
    Problem Definition: Goals, Objectives, and Constraints   8
    Design Requirements                                      9
Alternative Design                                           10
    Microcontroller                                          10
    Graphical User Interface                                 11
    Controller Unit                                          11
    Pedal                                                    12
Accepted Technical Design                                    13
    Power                                                    15
    Microcontroller                                          16
    Wireless                                                 21
    Digital Signal Processor                                 22
    Pedal                                                    37
    Software                                                 46
Testing Procedures: Validation and Verification              52
    Hardware                                                 52
    Software                                                 52
Financial Budget                                             53
    Team Labor Cost                                          53
    Material Cost                                            54
    Team Funding                                             54
Project Schedule                                             54
Design Team Information                                      57
Conclusions and Recommendations                              58
References                                                   59
Appendix                                                     60

List of Figures

Figure 1 – High Level Block Diagram                  7
Figure 2 – Main Unit Block Diagram                   8
Figure 3 – Regulator Connections – 5 V Output        9
Figure 4 – Regulator Connections – 3.3 V Output      10
Figure 5 – Regulator Connections 1.8 V Output        10
Figure 6 – Lab X-1 Schematic                         12
Figure 7 – Lab X-1 Power                             13
Figure 8 – PIC18F452 Pin Diagram                     14
Figure 9 – In-Circuit Programming of the PIC18F452   14
Figure 10 – LCD Connections                          16
Figure 11 – Keypad Layout                            18
Figure 12 – Receiver and Antenna                     19
Figure 13 – Audio Codec                              23
Figure 14 – Connection to DSP                        24
Figure 15 – EEPROM Connections                       25
Figure 16 – EEPROM Pseudocode                        27
Figure 17 – EEPROM Layout                            28
Figure 18 – Oscillator Connections                   29
Figure 19 – DSP Schematic                            30
Figure 20 – Analog Audio Signal                      32
Figure 21 – Digital Audio Signal                     32
Figure 22 – DSP Flowchart                            33
Figure 23 – Pseudocode for DSP in Time Domain        34
Figure 24 – Volume Pseudocode                        35
Figure 25 – Code for Tremolo                         36
Figure 26 – Code for Alternative Tremolo Function    37
Figure 27 – Comb Filter                              38
Figure 28 – Code for Indefinitely Fading Echo        38
Figure 29 – Code for Reverberation                   39
Figure 30 – Distortion Pseudocode                    40
Figure 31 – FIR Code                                 41
Figure 32 – FIR Filter Summation                     41
Figure 33 – MATLAB FDATool                           42
Figure 34 – Battery Charger Schematic                44
Figure 35 – 3.3 V Regulator                          46
Figure 36 – 5V Regulator                             47
Figure 37 – Voltage Divider Circuit                  47
Figure 38 – ADC Schematic                            48
Figure 39 – Transmitter and Antenna                  49
Figure 40 – Potentiometer usage                      51
Figure 41 – Rotary Potentiometer                     51
Figure 42 – Crystal Oscillator                       52
Figure 43 – Pedal Schematic                          53
Figure 44 – Main Unit                                55

Figure 45 – Mixer Circuit                                55
Figure 46 – Full System Schematic                        56
Figure 47 – GUI Application Flowchart                    58
Figure 48 – Sketch of GUI Menu                           59
Figure 49 – Example File Browser                         59
Figure 50 – GUI Pseudocode                               61
Figure 51 – Microcontroller Application Flowchart        62
Figure 52 – Pseudocode for Microcontroller Application   63
Figure 53 – Design Gantt Chart Timeline View             72
Figure 54 – Implementation Gantt Chart Timeline View     74
Figure 55 – DSP Starter Kit Schematic                    78

List of Tables

Table 1 – Microcontroller Model Summary           4
Table 2 – PIC18FXXX Memory Area                   15
Table 3 – DM2023 Pins and Functions               16
Table 4 – Instruction Syntax for DM2023           17
Table 5 – 6 AA Cell Ni-MH 1500 mAh Charging       44
Table 6 – Maxim-IC MAX 712 Battery Charger Pins   45
Table 7 – ADC Pins                                49
Table 8 – Linx TXE-433-KH Pins                    50
Table 9 – Calculated Potentiometer Positions      52
Table 10 – Estimated Labor Cost                   68
Table 11 – Estimated Material Cost                68
Table 12 – Design Gantt Chart                     71
Table 13 – Implementation Gantt Chart             73

List of Equations

Equation 1 – Volume                             35
Equation 2 – Tremolo                            36
Equation 3 – Comb Filter                        38
Equation 4 – N-Tap Filter                       41
Equation 5 – Z-Transform of N-Tap Filter   41


        Though technology has improved by leaps and bounds, most modern distortion
pedals are still nearly in the same form as they were in the 60’s and 70’s. Our project
intends to remedy this situation by providing a technologically advanced and modernized
distortion pedal. The limitations of current pedals include distortions that can not be
updated, and can only be modified within the hardwired parameters of the pedal. The few
pedals that are advanced enough to overcome some of these errors are bulky, confusing,
and are not user friendly. We intend to allow our user to connect the pedal to a PC via a
graphical interface to upload new user-selected distortions, and modify existing
distortions. Our interface will also be as simplified as possible, both on the pedal and the
PC. The pedal will contain an LCD to display both the status of the pedal, and a menu
simple enough to modify and select distortions, even while performing. Also, as many
parts of our pedal as possible will be wireless in order to cut back on cable clutter and
confusing connections. Our primary objective is to make a technologically advanced
pedal, without adding any new complexities for the consumer.


Statement of Need

        This project will address the problem of overly expensive and complex devices
for guitar sound modification. This “box” will be designed to make the process simpler
by eliminating cluttered wires, providing a simple user interface, reducing cost, and
providing a large amount of versatility.

Problem Definition

          • To create a guitar effects box that allows computer updates and has
              wireless controls.

          • There should be a simple, accessible GUI for the user to update the box.
          • There should be an easy to use interface for the box to connect to the PC.
          • The PIC should be programmed to communicate with the PC and the DSP
              as well as the remote control and pedal and provide any other necessary
              controls. It should have sufficient Flash RAM for a few effects to be
              stored on the box.
          • The DSP should be programmable on the box and should communicate
              with the PIC to accept programs. It should also have sufficient memory to
              allow complicated effects.
          • The A/D and D/A converters should retain signal quality without being
              too costly.
          • There should be a transmitter and receiver each for the pedal and any
          • The control and pedal should be easy to use and have sufficient battery
              power as well as a transmitter and receiver to communicate with the box.
          • There should be input and output for the guitar and the amplifier.
          • There should be sufficient and correctly utilized power for each device in
              the box.

          • Require no modification to existing hardware of PC, Guitar, or amplifiers.
          • Can be comfortably transported and stored, no more than half of a cubic
              foot and under 15 pounds.
          • Stay within departmental budget.

Design Specifications

   •   The main unit should run off of either a standard 120 volt AC power outlet or off
       of internal rechargeable batteries, and the pedal will run off of internal
       rechargeable batteries.
           o Each system must have an uninterrupted uptime of 5 hours on battery
           o The battery power will come from 1.2 volt rechargeable AA batteries.
           o The external power supply must be capable of delivering 1 amp.
   •   The microprocessor must control the entire unit
           o The microprocessor must be powerful enough to control multiple time
               sensitive tasks.
           o It must allow updates from a serial port.
           o It must allow interrupts generated by user actions.
   •   The graphical user interface (GUI) must be user friendly and run on any
       Microsoft Windows XP computer with a serial port.
           o The interface must allow the user to navigate their PC in search of files to
           o The interface will allow the user to modify certain parameters of the files
               that they have selected.
           o The interface will program the microprocessor and any external memory
               with the newly selected files.
   •   The main unit will have a Liquid Crystal Display (LCD) that will serve as a status
       display and user interface.
           o The LCD will display the current filename being used
           o The LCD will allow the user to view and select the other effects
               programmed on the box.
   •   There will be a pedal that controls the severity of the distortion.
           o The pedal will not be connected to the main unit, it will be wireless and
               have a range of 30 feet.
           o The pedal will be pressure sensitive.
           o The pedal must be rugged enough to withstand being stepped on, or
               roughly 20 pounds of pressure.
   •   The unit will utilize a digital signal processor (DSP) that will be used to distort
       the audio signal.
           o The audio signal must be processed without any noticeable delay.
           o The DSP must have enough memory, internal or external, to allow
               complex effects that require large amounts of storage, such as an “echo”
           o The ADC and DAC must retain signal quality and speed.
           o The effects that will be implemented to present the DSP portion of the
               project will be tremolo, distortion, several echo forms, and an FIR filter.
               Several other effects may be implemented, but the focus is not on effect
               design but the flexible hardware that allows effects to be programmed.

Alternative Design Analysis

        The design of the project went through many changes and alterations through the
semester, including many ideas for alternative designs. These decisions may have been as
simple as picking a different part number, to as severe as redoing the entire design. Each
of these alternative design decisions that were encountered will be discussed in the
following. In the end, the team finalized what they believe, through scientific analysis, to
be the best possible design for this device.


        The microcontroller in the device is the heart of the project. It controls all the
other subsystems in the box. The functionality and quality of the project depend utmost
on the speed and versatility of the microcontroller chosen. The PIC family of
microcontrollers, manufactured by MicroChip, was always the outstanding choice due to
ease-of-use, familiarity, and portability. However, their line of microcontrollers is very
diverse, as seen in Table 1, so there were many options to choose from when selecting a
part that was perfect for the application.

                       Table 1. Microcontroller Model Summary
    Model            Speed Memory          Power       Cost         Other
PIC18F7XX            8 MHz External Up to 5.5 V          $4 Enhanced low power
RfPIC12F675X        20 MHz       ~2 K Up to 5.5 V        $2 Low I/O pins, built in
                                                                RF capabilities
PIC18F8627          40 MHz       96 K Up to 5.5 V        $7   No advanced power
                                                                saving modes
PIC18F452           40 MHz       32 K Up to 5.5 V        $6        Generic

        The cost of the microcontroller ended up being the characteristic that the least
emphasis was on. The prices are all low enough and similar enough that it is nearly
negligible. All of the selected chips are very fast, so this was only a minor consideration.
The most emphasis was placed on power consumption and additional features included
with the selected microprocessor.
        The PIC18F8627 is a highly powerful chip. It has plenty of onboard memory and
runs at a standard 5.5 volts. It also has an onboard 10-bit analog to digital converter. The
drawback of this chip is that it is a power hog when compared to the other chips, and it
also lacks any sort of advanced power management features. Due to the constraint of
battery life in the project, having little control over power consumption was the only
drawback of using this microprocessor.
        The group also considered using an rfPIC, namely the rfPIC12F675X, because of
the built in wireless capabilities. This was the cheapest product the group considered. The
memory areas are small, but would be handle a modest application. External memory
would most likely have to be used. This model also lacked advanced power management

options. This particular option was weak in all areas, and only attractive because of the
wireless capabilities.
         The PIC18F7XX line of microprocessors also looked very suitable at first. It was
the most attractive in terms of power consumption. The features of this family include
“nanoWatt” technology that ensures consumption of just a few nanowatts of power
during sleep modes and periods of low activity. It also features low power timers, and an
enhanced watchdog and brownout mode. The drawbacks to this selection, though, are
that it would require external memory, and the speed was not impressive.

Graphical User Interface

        The graphical user interface running on the PC has only a few details that are set.
It must allow the user to select which effects files to use off of the PC, and it must allow
the user to update the device. This left a lot of freedom in the design of the application.
        One idea was to have a full design suite that allows the user to design their own
effects files. The interface for this suite would be simple and intuitive, to allow a novice
user that has limited or no knowledge of digital signal processing, microcontrollers, or
programming languages, to be able to, in essence, “play around” with the interface and
design their own distortion files. This suite would also allow the user to test the files on
the PC through software emulation, without use of the device itself. When realistically
analyzed, the sheer complexity of this software project was too great, and the
programming experience and knowledge of the group was too little for this to be
considered for the final design.
        Another consideration was to allow the user to connect their guitar to the PC to
allow the user to test the effects files through software emulation, so that they could
modify their files without having to update the device for every change to hear the final
sound produced. This was, again, considered too monumental of a task for the time

Controller Unit


       This was a very direct choice. The decision was merely whether or not the unit
should function solely off of an external power supply, or if it should allow internal
rechargeable batteries as a backup means of power. Since the goal of this device is to
reduce wire clutter, and allow as much freedom of use as possible, not including battery
power would be an obvious mistake. The only other consideration was whether or not to
include internal rechargeable batteries and a subsystem for charging them.


        The human interface with the project must allow the user the change to a different
effect stored in memory with only the press of a button. This could be either a rotary dial,
or buttons. The rotary dial would rotate through a list of effects, or the buttons would be

used to navigate a similar list. These controls could either be on the main unit of the
project, or included on the wireless pedal.


        The pedal, which was designated to be separate from the main unit, also had a few
design considerations. It would not necessarily have to be wireless, and instead could
have a direct cable connection to the main unit, or be included on the main unit itself.
However, adding a cable obviously goes against the design goal of reducing the amount
of cables, and including the pedal on the main unit means less freedom of movement. The
cables that the main unit must have connected to it would anchor the pedal.
        The function of the pedal was also debated. For the sake of simplicity, it was
suggested that the pedal simply be a large on/off switch instead of controlling the amount
of distortion. Losing this functionality was considered too disabling to include in the

Accepted Technical Design: Overview

        The group performed painstaking review of each alternative until arriving at the
decision to use the following design. It will include a microcontroller, a wireless
interface, an LCD screen, a digital signal processor, and rechargeable battery system, a
pressure sensitive pedal, an analog-to-digital converter, a digital-to-analog converter, and
a graphical user interface that runs on a PC. This section will discuss in detail all of the
components chosen, and convey how they will all function together.
        From viewing Figure 1 below and Figure 2 on the next page, a greater
understanding of the overall design is gained. The project is divided in to three distinctly
separate parts: the PC application, the main controller unit, and the pedal.
        The PC interface allows the user to select and modify their effects files, and then
to update the memory on the main unit, or “fuzz box.” The main unit takes in the guitar
signal, then performs all of the distortion, and outputs the audio signal to the amplifier.
The pedal allows the user to control the amount of distortion by applying pressure.


                 Guitar                 Fuzz Box                  Amplifier


                           Figure 1. High Level Block Diagram.

                  Main Unit

                                      DC Volts                                                    Batteries
Power Supply

                                                                DC Voltage Busses

                                               Wireless                                  Keypad/LCD
                       Wireless Receiver                           Microcontroller                            Keypad / LCD
                                              Control Bus                                Control Bus

                                                                                            Gain                        Audio Out
                    External Memory                    DSP Chipset and CODEC

      Guitar In

                                           Figure 2. Main Unit Block Diagram

        After exploring various design ideas, the chosen design for the main unit power
system was to allow all necessary components to be battery powered, therefore allowing
the unit to remain portable. In addition to this, the design would provide a rechargeable
system so that the user would be able to use rechargeable Nickel-Metal Hydride batteries
and simply plug the whole unit into the wall to recharge the batteries or take the batteries
out of the unit and charge them using a separate charger. The advantage of being able to
charge the batteries while in the unit is that the user can continue to use the fuzz box as
long as there is an AC outlet somewhere close. A low battery indicator will be included
on the main unit in a clearly visible place to alert the user when it is time for the batteries
to be charged. The power system for the main unit must be able to supply a number of
electrical components and provide stable operation when the unit is being powered by the
batteries and while charging with the AC adapter. The batteries must also provide at least
5 hours continuous operation on a single charge because it was concluded that anything
less than that could prove to be an inconvenience for the user. The main unit will use the
same main power supply and rechargeable system as the pedal and the detail on that
design can be found with the explanation of the pedal.

Voltage Regulator

        The ADM663A voltage regulators made by Analog Devices were chosen to
supply power to the various components in the main unit. The 7.2V supply voltage from
the 6 Ni-MH batteries was converted to a 3.3V output to power the DSP and the receiver
and also to 5V to power the two Log Trimmer Potentiometers. The PIC and LCD are
part of the X1 board which will be supplied by the 7.2V main power supply from the
batteries. A voltage regulator was also used to achieve the additional 1.8V supply needed
for the DSP. Voltage regulators were chosen to ensure that the voltages supplied to each
component remained constant so that everything will operate consistently and as desired
and also because they required no external components for the voltages that are being
used in this design except for the 1.8V supply. These regulators come in an 8-pin DIP
package which allows for good connections and they also provide an additional 3.3V
output. The voltage regulators are connected slightly differently to achieve the 5V output
than the 3.3V output and these connections can be seen in the main schematic, Figure X.

                                     U2 ADM663A

               7.2V input        8                     3
                                     VIN+    VOUT1     2
                                 1           VOUT2         5V output To Log Trimmer Pots
                                 5   SENSE             7
                                 6   SHDN        VTC


                        Figure 3. 5 V Output Regulator Connections.

                                          U1 ADM663A

             7.2V input               8                        3               3.3V output To DSP
                                          VIN+       VOUT1     2
                                      1              VOUT2                     3.3V output To Rx
                                      5   SENSE                7
                                      6   SHDN           VTC


                  Figure 4. 3.3 V Output Regulator Connections

                              U7 ADM663A

7.2V input                8                      3
                              VIN+    VOUT1      2                        1.8V output to DSP
                          1           VOUT2
                          5   SENSE              7                 R8
                          6   SHDN        VTC                      385k



                 Figure 5. 1.8 V Output Regulator Connections.

Lab X-1 Board

        The Lab X-1 board is a development board for the PIC family of products. It
includes many different options, utilities, and peripherals that will be utilized. A
schematic of the X-1 board showing all of the portions that will be used in the unit is
show in Figure 6 below. This board was chosen because it is well documented, and will
speed up the development of the project immensely. The selected microcontroller, which
is discussed in the next section, is simply plugged in to a socket on the board. The
development board will actually be inside of the main unit, since it is so small and

Figure . 6 Lab X-1 Schematic.


         Power to the Lab X-1 board is supplied by the circuit in Figure 7 below. The
standard voltage regulator takes a ranged voltage input and supplies the necessary 5 VDC
to all the places on the board it is needed. The ZIF socket, which will contain the
PIC18F452, is connected to the regulator through pin 11, and pin 12 is connected to
ground. All of these power connections are reflected in the X-1 schematic, shown in
Figure 6.

                                  Figure 7. Lab X-1 Power.

        The powered components of the X-1 board will consume an estimated 260 mA
maximum at any time. This is derived from the PIC18F452 consuming 250 mA
maximum, and the LCD components consuming 4 mA maximum, and then rounding up
to be safe.


         The microcontroller in this project is the heart of the design. In explaining the rest
of the design, it is useful to think of the microcontroller as the center of the project, and
all other parts as subsystems of the microcontroller. The microcontroller selected for the
final design was the PIC18F452, which is produced by MicroChip. This particular
product was selected because of the outstanding power management features, and the
extreme versatility of the onboard options and capabilities.
         This package is a 40-pin Dual In Line PIC18F452. It has a lifetime cycle
capability of over a million EEPROM erase/writes, and 100,000 FLASH erase/writes. It
has a data retention of over 40 years. The microcontroller supports In-Circuit Serial
Programming (ICSP) via only two pins and 5V. The package includes 3 timers modules.
It is capable of operating from 2.0V to 5.0V. This model can also handle up to 10 MIPS
(millions of instructions per second) when operating at 40 MHz clock frequency. A pin
diagram of the PIC18F452 is shown below in Figure 8.

                          Figure 8. PIC18F452 Pin Diagram.

        The PIC18F452 will be placed in to the Zero Insertion Force (ZIF) socket of the
Lab X-1 board, and all the connections are pre-wired to their proper destinations from
there. Access to any pins needed outside of the X-1 board is then gained by blocks of
headers next to the ZIF socket.
        The Lab X-1 board allows in-circuit programming of the PIC18F452. The USB
port of a PC is connected to a MicroChip MPLAB ICD2 device, which is then connected
to area J3A of the X-1 board by an RJ11 connector. These connections are shown in
Figure 9 below, and on the schematic in Figure 6 above, denoted by area J3A, which is
where the RJ11 cable plugs in to the X-1 board.

                  Figure 9. In-Circuit Programming of the PIC18F452.

        The MicroChip MPLAB software suite allows the user to both debug programs,
and to program the PIC device. The MPLAB suite will be used extensively in the testing
of the microcontroller software, and to program the final software design to the PIC. As
can be seen on the X-1 schematic, the RJ11 connections from the MPLAB ICD connects
to pins 1, 39, and 40 on the PIC19F452.


       The microcontroller must have enough memory to store the program it will be
running, which controls the entire project. The program size is assumed to be roughly 10
K, based on similar control programs that monitor and initialize similar amounts and
types of hardware. As shown in Table 2, the PIC18F452 has 32K of onboard FLASH
memory. This is more than sufficient.

                         Table 2. PIC18FXXX Memory Areas.
                           On-Chip Program Memory On-Chip              Data
              Device       FLASH # Single Word        RAM            EEPROM
                            (Bytes)     Instructions (bytes)          (bytes)
           PIC18F242          16 K           8192           768         256
           PIC18F252          32 K          16384          1536         256
           PIC18F442          16 K           8192           768         256
           PIC18F452          32 K          16384          1536         256

        The PIC18F452 only has 256 bytes of data EEPROM, though. The storage of 3
effects files with a maximum compiled file size of 64K will require roughly 192 K of
data EEPROM. The onboard memory of the microcontroller is insufficient for this, and
therefore, an external EEPROM memory unit of at least 192K is required for storage of
the effects files. The group decided that this memory would best be over-estimated,
because if the memory was not used now, it could surely be utilized later for more
complex effects, and greater amounts of them. The EEPROM selection and use will be
discussed in depth later in the report.

Liquid Crystal Display

        The liquid crystal display (LCD) on the X-1 board is a Sanyo DM2023, which is a
20 character, 2 line display. The controller paired with the display is a Hitachi
HD44780U. The controller integrates the control circuitry, data RAM, and character
generator ROM that are required to utilize the display properly. The package allows both
4-bit and 8-bit parallel interfaces, so that a microcontroller can read and write data
directly. The PIC will provide control of the entire LCD module through PORTE and
PORTD. These connections to the DM2023 are shown below in Figure 10, along with
power connections.

                               Figure 10. LCD Connections.

        Interfacing with this combination is fairly simple. The only real issue is timing the
circuit well. In Table 3, the pin numbers and functions are all given for the DM2023. In
Table 4, the instruction syntax that the controller must use to communicate is given,
along with the timing requirements. The controller handles the character code
conversions, so the programmer does not need to know the codes for each letter to
display them.

                               Table 3. DM2023 Pins and Functions.
   Pin #     Symbol                                   Function
   1        VSS           Ground
   2        VDD           +5 VDC
   3        VD            LCD drive supply
                          Register select pin
                          0: Instruction register {write}
   4        RS
                          Busy flag and address counter {read}
                          1: Data register {read/write}
                          Read/write pin
   5        RW            0: Write: MPU → LCD module
                          1: Read: LCD module → MPU
   6        E             Enable flag
                          Data bus {tristate bidirectional pins}
   7-10     DB0-DB3       Used as the lower 4 bit pins when an 8-bit interface is used.
                          Unused when the 4-bit interface is used.
                          Data bus {tristate bidirectional pins}
                          Used as the upper 4 bit pins when an 8-bit interface is used.
   11-14    DB4-DB7
                          Used as the 4 data bits when a 4-bit interface is used.
                          DB7 is also used as the busy flag.

                                       Table 4. Instruction Syntax for DM2023.
  Instruction                                                                  Description                        Execution Time
                RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
                                                                Clears the whole display and then
Display Clear   0   0   0    0    0      0    0     0   0     1 returns the cursor to the home position           82 us to 1.54 ms
                                                                (location 0)
                                                                Returns the cursor to the home
                                                                position. Also restores a shifted
Cursor Home     0   0   0    0    0      0    0     0   0     *                                                    40 us to 1.6 ms
                                                                display. The contents of the DD RAM
                                                                are not changed.
                                                                Sets the cursor advance position and
                                                                whether the display shifts. These
Entry Mode Set 0    0   0    0    0      0    0     1   I/D   S                                                        40 us
                                                                operations are performed when data is
                                                                read or written.
                                                                Sets the display on/off state (D), the
                                                                cursor on/off state (C), and the
Display On/Off 0    0   0    0    0      0    1     D   C     B                                                        40 us
                                                                blinking state (B) of the character at
                                                                the cursor position
                                                                Performs cursor motion and display
Display Shift   0   0   0    0    0      1   S/C R/L    *     * shift without changing the contents of                 40 us
                                                                the DD RAM
                                                                Sets the interface data length (DL), the
Function Set    0   0   0    0    1     DL    N     F   *     * number of display lines (N), and the                   40 us
                                                                character font (F)
                                                                Sets the CG RAM address. The next
                0   0   0    1                ACG               data transmitted will be the CG RAM                    40 us
                                                                Sets the DD RAM address. The next
                0   0   1                    ADD                data transmitted will be the DD RAM                    40 us
                                                                Reads out the busy flag (BF), which
Busy Flag /
                                                                indicated the internal operation in
Address         0   1   BF                   AC                                                                         1 us
                                                                progress state, and the contents of the
                                                                address register.
CG RAM / DD                                                     Writes to DD RAM or CG RAM
RAM Data     1 0                       Write Data                                                                      40 us
CG RAM / DD                                                      Reads data from DD RAM or CG
RAM Data     1 1                       Read Data                 RAM                                                   40 us
     Notes  I/D = 1:     Increment                               DD RAM: Display data RAM                  These execution times are
            I/D = 0:     Decrement                               CG RAM: Character generator RAM           assumed for a FOSC = 250 kHz,
            S = 1:       Display shift at the same time          ACG: A CG RAM address                     and will change if this
            S/C = 1:     Display shift                           ADD: Corresponds to a DD RAM              frequency is changed.
            S/C = 0:     Cursor Move                             address
            R/L = 1:     Right shift                             AC: The address counter, which is
            R/L = 0:     Left shift                              used for both DD and CG RAM
            DL = 1:      8 bits      DL = 0: 4 bits
            N = 1:       2 lines     N = 0:     1 line
            F = 1:       5x10 dots F = 0:       5x7 dots
            BF = 1:      Internal operation in progress
            BF = 0:      Instructions accepted
            *:           Invalid (don’t care)


        A keypad is included on the X-1 board. This will be utilized to provide all user
controls of the unit. The keys will have to be extended slightly to be accessible to the
user. This will be done when the X-1 board is assembled. This will be done by attaching
wires to the switches and opting not to mount them directly to the X-1 board as is
normally done. Using these wire extensions, the keys can be mounted where they are
needed. The keypad layout and connections to PORTB of the PIC18F452 is shown below
in Figure 11.

                              Figure 11. Keypad Layout.


        The final decision was that the main unit and the pedal that controls the magnitude of
the distortion should not be connected to each other physically. Instead, it seemed more
useful to design the pedal as a separate component that could transmit and receive
information wirelessly with the main unit to allow the user to place the pedal anywhere they
desired as long as it was within approximately 30 feet of the main unit. This distance can be
larger but for the intended purpose of this design 30 feet is a sufficient range. This design led
the group to select a compatible transmitter and receiver pair for use in the pedal and the
main unit, respectively. Selection of the receiver was based on a combination of things such
as cost, ease of implementation (something that was not too far beyond the scope of this
design), the transmitting frequency, required supply voltage, and the features that could be
implemented. After considering these areas, the Linx Technologies RXD-433-KH receiver
was selected. This particular receiver operates at 433MHz. It has an integrated decoder, and
when paired with the matching TXE-433-KH transmitter, that has an integrated encoder, a
highly reliable wireless link is formed. When transmitted data from the pedal is received, the
data is presented to the on-board decoder in the receiver. If the incoming address data
matches with the local address settings, the decoder outputs are set to replicate the state of
the transmitter data lines. Because both the receiver and transmitter involve the use of
Surface Acoustic Wave (SAW) devices, the receiver’s pass opening is quite narrow,
therefore reducing the possibility of near-band interference and also increasing sensitivity.
No external RF components were needed with this receiver other than an antenna.
    The antenna that will be used is also made by Linx Technologies, part number ANT-433-
SP, and was selected because it is optimized for the frequency at which this particular
transmitter and receiver pair operates. It can also be mounted on the printed circuit board.
Although higher performance would be possible with a whip style antenna, for the short
range that is required in this project and the physical design of the main unit itself, both the
performance and compatibility of the chosen antenna will be more than sufficient.
    In the case of this design, batteries will supply the necessary 2.7 volts to power the
receiver. A diagram of this receiver and antenna can be seen below in Figure 12.

                                 Figure 12. Receiver and Antenna.

        The pins that are important for implementation of this design are as follows: Pins
4 and 24 must be connected to ground. 2.7 volts must be applied to the VCC Pin 5. This
voltage will not need any supply filters, since it will be coming from “clean” batteries.
Pin 11 goes high when a transmission is received and the address pins match that of the
transmitter, and pins labeled D0 – D7 are the data lines that will output whatever data is
sent by the transmitter, providing the addresses match. As can be seen in the figure, pin
28 connects to the antenna and it has an impedance of 50Ω, and is capacitively isolated
from the internal circuitry. There is also an option to connect pin 6, which puts the
receiver into sleep mode for conserving power. This will most likely be used when
implementing this design next semester to conserve power during periods of inactivity.

Digital Signal Processing

Digital Signal Processing (DSP) Overview

       The DSP selected for this project is Texas Instruments’ TMS320VC33. This
processor is ideal for this application. The main reasons for selecting this processor are:

   -   It is capable of 150 MFLOPS (Millions of Floating Point Operations Per Second).
       This high speed floating point manipulation is necessary to maintain the
       requirement of no noticeable delay when performing operations on signals in real
   -   It includes 1 MB of SRAM. This memory is needed to store large array buffers
       which are necessary for many audio effects.
   -   It consumes a low amount of power. This is significant because the system must
       be capable of running on battery power.
   -   It is inexpensive for its capabilities. The budget only allows so much room to
       work with and “the most bang for buck” is desired.
   -   It is well supported by TI. There is a large amount of documentation and sample
       code available on their site.
   -   It can be programmed from memory or a host processor quickly and efficiently
       using its boot loader.
   -   Availability of an affordable University Starter Kit that is well supported by its
       creator from TI. The developer of the DSK (Development Starter Kit) posts
       regularly on a forum on which users have posted many questions that have been
       of great help in the design. If necessary, the group can also post there and receive
       a response directly from the developer of the processor and DSK.

        In order to process the analog audio signals, an Analog to Digital Converter
(ADC) is necessary to convert them into digital audio signals useable by a processor and
a Digital to Analog Converter (DAC) is necessary to convert the processed digital audio
signal back into a processed analog audio signal. An audio codec is a single chip that
handles both of these conversion processes and is designed to interface with a processor
such as a DSP. The audio codec which will be used for this project is the TI PCM3003.
This codec’s capabilities include:

   -   A small package size. The chip’s small profile is an important consideration to
       gauge how well it will fit into the box.
   -   Low cost. This is important for all components in the project.
   -   20-bit resolution and 48 kHz sampling frequency. Humans can perceive sounds
       up to 20 kHz. In order to reproduce a sound wave it must be sampled twice as fast
       as the signal that is being reproduced, this is why CD’s are sampled at 44 kHz.
       Also, the sampling resolution used by CD’s is 16-bit. Both of the above
       parameters for the PCM3003 audio codec are greater than that of an audio CD,
       which will be used as the bar for acceptable sound quality.
   -   It is available, tested, and wired properly in conjunction with the TMS320VC33
       on the DSK.

        The final factor that clenched the decision to use the TMS320VC33 DSP and the
PCM3003 is that they are both included with the TMSVC33 DSK. The starter kit will
greatly enhance our ability to implement the design effectively within time constraints.
The capabilities of the TMS320VC33 DSP Starter Kit and TI’s software support include:

   -   Audio input and output ports.
   -   Eight user I/O pins. These can be configured to provide additional control over
       the DSP or over the current DSP application by the PIC, although we currently do
       not plan to use them for our applications.
   -   Parallel port connection to a PC. This allows testing and implementing of the
       software for the DSP while the hardware for the box is still being constructed.
   -   TI’s optimizing C compiler, assembler, and linker. This allows for development in
       C, which is much more natural to me than assembly.
   -   A large selection of applications and demos.
   -   It is inexpensive. This is a universal theme; several other DSK’s and processor /
       codec packages were considered but were 2 to 4 times as expensive as the one
       chosen although significantly more powerful.

DSP Related Hardware

        There are several hardware components that interface with the DSP which must
be discussed before getting into the software that operates on the sound samples. There is
the audio codec which includes an ADC and DAC, an external EEPROM to store effects,
the interface between the DSP and PIC, and the interface between the PC, PIC, and
EEPROM which includes 4 serial to parallel shift registers and two 2 multiplexers.
        See figure 19 for the full DSP schematic with its related hardware interconnects.
This section will be divided into several sub sections each explaining the different pieces
of hardware, their function, and their interconnections.

Audio Codec

                                                                     15                       12
                                                                          DIN          DOUT
     Net Name                                                        6                        19
                                                                     3    VINL      VOUTL     20
                                                                          VINR      VOUTR
       Analog Input                                                  21
                                                                      4   VCOM
                                                                HI        VREFL
                                                           0         11
                                                                     10   BCKIN
                                                                      9   LRCIN
                                                                          SY SCLK
     Net Name
                                                                     18   20BIT
       ADC Power Down (activ e low)                                  17   DEM0
                                                                      7   DEM1
                                                                      8   PDAD
     Net Name                                                             PDDA

       DAC Power Down (activ e low)                                   1   VDD
                                                                      2   VCC1
                                                                     24   VCC1
                                      HI                                  VCC2



                                           Figure 13. Audio Codec

         Figures 13 provides a zoomed in drawing of the PCM3003 audio codec while
Figure 14 displays its serial interconnection with the DSP. Each pin will be explained
         The DIN (15) and DOUT (12) pins are the digital data input and output pins for
the ADC and DAC. These are connected to DR0 (104) and DX0 (111) which are the
serial data receive and data transmit pins on the DSP.
         Since the input from the guitar is not stereo, only the left channel of the ADC or
pin VINL (6) will be used. Subsequently, the output of the DAC will be on the left
channel pin VOUTL (19). Of note here is that the Vpp output for electric guitars is
designed to be 1.8 volts. The audio codec optimally runs with an analog input of 1.8
volts, so the raw analog signal from an electric guitar requires no modification.
         The reference voltages for both the left and right channels VREFL (4) and
VREFR (5) are hard wired to 3.3 volts. VCOM (21) is connected to ground.
         The bit clock BCKIN (11) is used for each bit of serial data transmission and is
connected to CLKR0 (107) on the DSP which is the serial receive clock output. The
serial ports will both receive and transmit at the same frequency so CLKX0 could also
have been used.
         The objective is for the codec to operate at 44 kHz sampling frequency (fs) with
20-bit sampling resolution. 20BIT (16) is hardwired to 3.3 volts for 20-bit resolution. In
order to achieve the desired fs, LRCIN (10) must have a 44 kHz clock while the
SYSCLK (9) input must be 256, 384, or 512 x fs. TCLK0 (114) will be initialized in
software to a 44 kHz clock and connected to LRCIN (10). TCLK1 (113) will be
initialized to a 512 x 44 kHz = 22.5792 mHz clock and connected to SYSCLK (9) which
will satisfy the required conditions.
         The codec includes digital de-emphasis which will be set to 44.1 kHz by setting
DEM0 (18) to 3.3 volts and DEM1 (17) to 0 volts. PDDA (7) and PDAD (8) are the

power down DAC and ADC control pins controlled by the PIC to turn the codec on or
         Nominal power for the codec is 3 volts but can range between 2.7 and 3.6 volts so
it will be connected to 3.3 volts. The Cadence drawing does not have a ground connect,
but rest assured that the data sheet does and that it will be properly grounded.

                                 Figure 14. Connection to DSP.

EEPROM and Parallel PC Interface

        Earlier in the report, the EEPROM is mentioned, but not in detail. The Fuzz Box
needs to be able to store several effects. To accomplish this external memory is required
because neither the PIC nor the DSP has enough. The original specifications called for 3
effects but it has been expanded to 4.
        The FIR filter implemented by the DSK designer is 10 kilobytes. The FIR filter
that will be implemented by the group should be of similar size, or smaller. The
EEPROM will store the opcode to be used by the DSP. The opcode for the designer’s
FIR filter, including documentation, is 25 kilobytes.
        The most complex effect that will be implemented is an FIR filter and it is not
intended on putting documented opcode onto the EEPROM for this effect. With this in
mind, a 1 M parallel EEPROM with 128 K words by 8 bits was chosen. The upper bound
for each file was assumed to be 32 kilobytes to simplify the file selection, which will be
explained later, so that allows for 4 total effects. A parallel EEPROM was chosen
because the serial ports are already in use on the DSP and the DSP has a boot loader,
which will be explained later, and address and data lines designed for interfacing, in
parallel, with external memory.


                                                12                 13
                                                11   A0     I/O0   14
                                                10   A1     I/O1   15
                                                 9   A2     I/O2   17
                                                 8   A3     I/O3   18
                                                 7   A4     I/O4   19
                                                 6   A5     I/O5   20
                                                 5   A6     I/O6   21
                                                27   A7     I/O7
                                                26   A8
                                                23   A9
                                                25   A10
                                                 4   A11
                                                28   A12
                                                29   A13
                                                 3   A14
                                                 2   A15
                                                31   OE
                                                22   WE


                                 Figure 15. EEPROM Connections.

        Figure 15 is a close up view of the EEPROM. A0 – A16 are the address pins, I/O0
– I/O7 are the data pins, OE is the output enable pin, WE is the write enable pin, and CE
is the chip enable pin hard wired to GND. Vcc is connected to 3.3 volts and the ground is
not on the schematic but it is on the data sheet and will be properly grounded.
        The EEPROM is programmed directly by the PC via a parallel printer port. It is
read from by the DSP whenever a new effect needs to be loaded. The DSP is told where
to look on the EEPROM by the PIC.
        In order to better explain how the EEPROM is controlled, a few important
observations must be stated. The EEPROM data lines are either being written to by the
PC or read from by the DSP, the PIC is not connected to the data lines. When the PC is
connected, neither the DSP nor the PIC will assert or read anything on the address lines.
The DSP will be programmed only when the PC is disconnected. Essentially, when the
PC is connected the DSP is completely off and the PIC is not doing anything with the
lines. With these things in mind, it is assumed that the parallel PC interface can be
connected to the data and address lines of the EEPROM at the same time as the DSP and
PIC with no further controls.
        The EEPROM is programmed by the PC with 4 different effect files, each of
which always starts at the same location in memory 32 kilobytes from the last. The fixed

address locations are at approximately decimal 0, 32000, 64000, and 96000. An example
of code in C for programming an EEPROM via the parallel printer port very similar to
the one used on this project will be modified to fit the needs of the project. Pseudocode
for this operation can be found below. The modified code for the project only uses a write
operation so the amount of data lines required was able to be condensed to 8, which is the
limit for the DB25 port on the PC.
         It is important to note that writing to the EEPROM is very slow, but it can be sped
up by using the 128 byte page write operation. With a maximum page write time of 10
ms, if 1 byte is used per page then it will take approximately 128 minutes (worst case) to
finish the write. If the 128 byte page is used then it should take approximately 1 minute
(worst case).

 void delay(float time){
       //delay function used for timing

 void Load_Registers(int data, int address){
       //load first shift register with byte of data
       //load second shift register with 8 bits of address
       //load third shift register with 8 bits of address
       //load fourth shift register with last address bit
       for(int x=0; x<8; x++){
             //the registers are loaded in parallel 1 bit at at time
             //by imposing the desired value on their data
             //lines and then shifting the data in when they are loaded
             //uses the delay function after each loop

 void burn(int* data, int length, int filenumber){
       int address = 0x00;
       if(filenumber == 1)
             address = ;//starting address for first file
       if(filenumber == 2)
             address = ;//starting address for second file
       if(filenumber == 3)
             address = ;//starting address for third file
       if(filenumber == 4)
             address = ;//starting address for fourth file
       //initialize the EEPROM, loading values into it
       //using the Load_Registers() function call
       //load 0xAA to address 0x5555
       //load 0x55 to address 0x2AAA
       //load 0xA0 to address 0x5555
       for(int x=0; x<length; x++){
             //load the data, up to 128 bytes
             //incrementing the address counter
             //and data pointer after each load
       //begin the burning prcess for 128-byte page-write
       //10 ms delay

 int main(){
       //open the files with opcode to be programmed
       //store opcode to be burned in 4 arrays
       for(x=1; x<5; x++){ //load all 4 files
                   data_array = file_1;
                   data_array = file_2;
                   data_array = file_3;
                   data_array = file_4;
             //data pointer points to current array
             //get the length of the array
             while(length > 128){ //128 byte page write
                   length = length-128;
                   burn(data_array, 128, x);
             burn(data_array, length, x); //burn the last bytes

                            Figure 16. EEPROM Pseudocode.

         This configuration makes use of 4 8-bit shift registers for the 17 address lines and
8 data lines. Figure 17 provides a close up view of the configuration. The shift registers
operate between 2 volts and 6 volts. The EEPROM is rated up to 6.5 volts on its inputs, is
powered by a 3.3 volt supply, and outputs at 3.3 volts. This means that the PC parallel
port interface of 5 volts will work with the EEPROM and shift registers. Since the DSP
has its lines set to high impedance when being kept in the hold state by the PIC, it will be
shielded from the 5 volts coming from the shift registers.


                6                 1
                        OUT IN0   3
                            IN1             HI

                             EN   8
                            SEL                                       Net Name
                            +VS   5                              SELECT WE MUX



                6                 1
                        OUT IN0   3
                             EN   8
                            SEL                                       Net Name
                            +VS   5                              SELECT OE MUX


            U7                         HI

 3                  1
 4   Q0     A       2
 5   Q1     B                                                    J1
 6   Q2             8
10   Q3   CLK
11   Q4             9                                      1
12   Q5   CLR                                                         14
13   Q6                                                    2
     Q7                                                               15
     CD74HC164                                                        16
            U5                                             4
 3                  1                                      5
 4   Q0     A       2                                                 18
 5   Q1     B                                              6
 6   Q2             8                                                 19
10   Q3   CLK                                              7
11   Q4             9                                                 20
12   Q5   CLR                                              8
13   Q6                                                               21
     Q7                                                    9
     CD74HC164                                            10
            U6                                                        23
 3                  1                                                 24
 4   Q0     A       2                                     12
 5   Q1     B                                                         25
 6   Q2             8                                     13
10   Q3   CLK
11   Q4             9
12   Q5   CLR
13   Q6                                              CONN DSUB 25-P


 3                  1
 4   Q0     A       2
 5   Q1     B
 6   Q2             8
10   Q3   CLK
11   Q4             9
12   Q5   CLR
13   Q6


                                  Figure 17. EEPROM Layout.

         Once the EEPROM is programmed and the PC is disconnected the DSP must be
programmed with the current effect. The PIC controls the top 2 bits of the address lines
along with the two multiplexers. The multiplexers control whether the PC is controlling
the OE and WE pin or if they are hard wired to GND and 3.3 volts respectively (OE on,
WE off). The top 2 bits control what the DSP sees, if the first effect is to be programmed
it is 00, the second effect is 01, third is 10 and fourth is 11. The DSP controls the rest of
the address lines.
         The DSP has a protected section of memory which contains its boot loader. What
is relevant to this project about the boot loader is that when the MCBL/MP pin is held
high when the DSP is reset and the interrupt pins INT0, INT1, INT2 and INT3 are set to
0111 then the DSP will search for its program in external memory starting at address
4096. Once it reaches a block of memory of size 0 it completes its load and begins
program execution. The fact that it begins searching the EEPROM at 4096 means that the
final program stored in the EEPROM must be less than 32 kbytes – 4 kbytes = 28 kbytes.
According to the data sheet that is all there is to it. A new program can be loaded by
resetting the DSP and telling it where to go.
         The interrupt pins are hard wired to GND, 3.3 volts, 3.3 volts and 3.3 volts. The
MCBL/MP pin is connected to the PIC as well as the RESET and HOLD pins.

DSP Hardware Conclusion

       The final piece of hardware connected to the DSP is a 20 megahertz oscillator. It
is connected to the 3.3 volt supply, GND, and the EXTCLK pin on the DSP. A close up
view of it can be seen in Figure 18.


                                             1                        3

                                                  EOH           OUT



                                Figure 18. Oscillator Connections.

        The internal 5 x PLL (Phase Lock Loop) is used by the DSP and is activated by
setting CLKMD0 and CLKMD1 to 3.3 volts. This is the highest power consuming mode
of the DSP, but is necessary in order to effectively implement the effects.
        See Figure 19 below for the complete schematic of the DSP and related hardware.

                                                                                      15                       12
                                                                                           DIN          DOUT
Net Name                                                                              6
                                                                                           VINL      VOUTL
                                                                                                               19                                                                                                                     Net Name
                                                                                      3                        20
                                                                                           VINR      VOUTR
  Analog Input                                                                        21                                                                                                                                        Analog Output
                                                                                       4   VCOM
                                                                      HI                   VREFL
                                                                 0                    11
                                                                                      10   BCKIN
                                                                                       9   LRCIN
                                                                                           SY SCLK
Net Name
                                                                                      18   20BIT
  ADC Power Down (activ e low)                                                        17   DEM0
                                                                                       7   DEM1
Net Name                                                                               8
  DAC Power Down (activ e low)                                                         1   VDD
                                                                                       2   VCC1
                                                                                      24   VCC1
                                          HI                                               VCC2





                                 1                           3

                                     EOH               OUT                       U1
                                                                                                                                                                                                                                      Net Name
                                                                           93                                               71

                                                       20MHZ               92    D0                                   D16   70
                                                                           91    D1                                   D17   68                                                                                                  A0
                                                                           90    D2                                   D18   67
                                                   0                       88    D3                                   D19   65
                                                                           87    D4                                   D20   64
                                                                                 D5                                   D21
                                                                                                                                                                                                                                      Net Name
                                                                           85                                               62
                                                                           84    D6                                   D22   61
                                                                           82    D7                                   D23   59                                                                                                  A1
                                                                           81    D8                                   D24   58
                                                                           79    D9                                   D25   57
                                                                           78    D10                                  D26   55
                                                                           76    D11                                  D27   54
                                                                           75    D12                                  D28   52
                                                                           74    D13                                  D29   51
                                                                           73    D14                                  D30   50                            U10
                                                                                 D15                                  D31
                                                                           100                                              99                       12                 13
                                                                                 TDI                                  TDO                            11   A0     I/O0   14
                                                                           139                                              30                       10   A1     I/O1   15
                                                                           138   RSV0                                  A0   29                        9   A2     I/O2   17
                                                                                 RSV1                                  A1   27                        8   A3     I/O3   18
                                                                           133                                         A2   26                        7   A4     I/O4   19                                U8
                                                                           132   XIN                                   A3   24                        6   A5     I/O5   20
                                                                                 XOUT                                  A4   22                        5   A6     I/O6   21                   6                 1
                                                                           130                                         A5   21                       27   A7     I/O7                                OUT IN0   3
                                                                                 EXTCLK                                A6                                 A8                                             IN1            HI
                                                                            98                                              20                       26
                                                                                 TCK                                   A7   19                       23   A9                                                   7
                                                                           122                                         A8   17                       25   A10                                             EN   8
                                                                                 INT0                                  A9                                 A11                                            SEL
                                                                                                                                                                                                                                                 Net Name
                                                                           121                                              16                        4
                                                                           120   INT1                                 A10   14                       28   A12                                                  4
                                                                           119   INT2                                 A11   13                       29   A13                                            +VS   5                           SELECT WE MUX
                                                                                 INT3                                 A12   11                        3   A14                                            -VS
                                                                           136                                        A13   10                        2   A15
                                                                           135   CLKMD0                               A14   8                             A16                                    AD8180
                                                                                 CLKMD1                               A15                   HI
                                                                           124                                              7                        24
                                                                            47   EDGEMODE                             A16   5                        31   OE                                              U9
                                                                           125   HOLD                                 A17   4                        22   WE
                                                                            45   MCBL/MP                              A18   3                             CE                                 6                 1
                                     0                                     127   RDY                                  A19   1                        32                                              OUT IN0   3
                                                                           128   RST                                  A20   144                           VCC                                            IN1
                                                                           102   SHZ                                  A21   142                                                                                7
                                                                                 TMS                                  A22                                                                                 EN
Net Name                                                                   103
                                                                                 TRST                                 A23
                                                                                                                            141                           AT28LV010
                                                                                                                                                                                                               8                                 Net Name
                                                                            12                                              104                                                                                4
                                                                            28   CVDD                                 DR0   111                  0                                                       +VS   5                           SELECT OE MUX
                                                                            46   CVDD                                 DX0   106                                                                          -VS
                                                                            66   CVDD                                FSR0   110
                                                                                 CVDD                                FSX0
Net Name                                                                    83
                                                                           101                                              96
                                                                           123   CVDD                                EMU0   95
  MCBL/MP                                                                  137   CVDD                                EMU1
                                                                             6   CVDD                                       38
                                                                 HI              DVDD                                  H1
                                                                            15                                              39                                                           U7                        HI
                                                                                 DVDD                                  H3
Net Name                                                                    23
                                                                                 DVDD                               CLKR0
                                                                            31                                              109                                               3                  1
                                                                            37   DVDD                               CLKX0   114                                               4   Q0     A       2
  RESET                                                                     43   DVDD                               TCLK0   113                                               5   Q1     B                                                 J1
                                                                            53   DVDD                               TCLK1                                                     6   Q2             8
                                                                            60   DVDD                                       48                                               10   Q3   CLK
                                                                            69   DVDD                               HOLDA   44                                               11   Q4             9                                   1
                                                                            77   DVDD                                IACK   36                                               12   Q5   CLR                                                       14
                                                                            86   DVDD                               PAGE0   35                                               13   Q6                                                 2
                                                                            94   DVDD                               PAGE1   33                                                    Q7                                                             15
                                                                           108   DVDD                               PAGE2   32                                                                                                       3
                                                                           115   DVDD                               PAGE3   42                                                    CD74HC164                                                      16
                                                                           129   DVDD                                 R/W   41                                                           U5                                          4
                                                                           143   DVDD                                STRB                                                                                                                        17
                                                                           131   DVDD                                       117                                               3                  1                                   5
                                                                           134   PLLVDD                               XF0   116                                               4   Q0     A       2                                               18
                                                                                 PLLVSS                               XF1                                                     5   Q1     B                                           6
                                                                                                                                                                              6   Q2             8                                               19
                                                                                 TMS320VC33                                                                                  10   Q3   CLK                                           7
                                                                      0                                                                                                      11   Q4             9                                               20
                                                                                                                                                                             12   Q5   CLR                                           8
                                                                                                                                                                             13   Q6                                                             21
                                                                                                                                                                                  Q7                                                 9
                                                                                                                                                                                  CD74HC164                                          10
                                                                                                                                                                                         U6                                                      23
                                                                                                                                                                              3                  1                                               24
                                                                                                                                                                              4   Q0     A       2                                   12
                                                                                                                                                                              5   Q1     B                                                       25
                                                                                                                                                                              6   Q2             8                                   13
                                                                                                                                                                             10   Q3   CLK
                                                                                                                                                                             11   Q4             9
                                                                                                                                                                             12   Q5   CLR
                                                                                                                                                                             13   Q6                                         CONN DSUB 25-P


                                                                                                                                                                              3                  1
                                                                                                                                                                              4   Q0     A       2
                                                                                                                                                                              5   Q1     B
                                                                                                                                                                              6   Q2             8
                                                                                                                                                                             10   Q3   CLK
                                                                                                                                                                             11   Q4             9
                                                                                                                                                                             12   Q5   CLR
                                                                                                                                                                             13   Q6


                                                                                                                       Figure 19. DSP Schematic.
Making Effects

        When the DSP is on it is continuously running its most recently programmed
application. After initialization an endless loop takes in audio samples from the codec,
processes them, and outputs them back to the codec. There are two main categories of
effects, those involving the time domain and those involving the frequency domain.
        Effect applications involving only the time domain can perform operations
directly on the digital sound sample and output the result. Effects which do true
frequency domain manipulation would require a Fourier Transform to be performed on a
set of samples before they can be operated upon in the frequency domain, the Fourier
Transform must then be performed again on the set before they can be output.
        Processors today can be incredibly fast and the Discrete Fourier Transform (DFT)
can be approximated very efficiently in code using a Fast Fourier Transform (FFT).
Even with these considerations, most real-time sound DSP is done in the time domain.
After careful consideration, it was concluded that the processor used for this project is not
fast enough to perform a real time FFT without significant sound degradation.
        The effects to be implemented are tremolo, distortion, echoes, and an FIR filter.
Several samples have been created and distributed that show the results of some sound
effects implemented with MATLAB. There are limitless effects that can potentially be
implemented on the Fuzz Box. This project only seeks to prove that the building blocks
for those effects can be implemented and that it is expandable.
        The samples were created using MATLAB. The equations are not the same as the
real time filtering performed by the DSP due to the nature of MATLAB. It does,
however, provide a good platform to quickly test and implement the effects before
actually programming them into the DSP.

Time Domain Effects

        An analog audio signal is a “wave” of voltages corresponding directly to the air
pressure waveform of a real sound (Figure 20). The digital audio signal is a sample set of
those voltages that represents the original signal (Figure 21). The resolution (how many
bits) determines how accurate the voltage reading is while the frequency determines how
many samples are taken per time unit. As explained before, humans can perceive up to 22
kHz, in order to reproduce a signal it is necessary to sample at least twice its frequency,
so a frequency of 44 kHz is required for the full range of human hearing without any
perceptible loss. It has been experimentally shown that 16-bit resolution is necessary to
create a high fidelity sound signal.

                            Figure 20. Analog Audio Signal.

                             Figure 21. Digital Audio Signal.

        The flow of information in the DSP for processing a time domain signal can be
seen in Figure 13.

Figure 22. DSP Flowchart.

 int n = size;     //size of a samples array
 float samples[n]; //any other variables particular to a function are
                   //to be initialized here

 void InitDSP(void){
       //set up the stack
       //initialize any needed I/O ports

 void InitCodec(void){
       //set the receiving serial port to input
       //set the transmitting serial port to output
       //set the serial clock
       //set the Timer0 and Timer1 clocks
       //enable send and receive interrupts
       //kick start the serial port

 float ReceiveSample(void){
       while(!sample_ready){}; //wait for the sample
       float sample = serial_input; //input from codec
       return sample;

 void TransmitSample(float sample){
       serial_output = sample; //put the current sample into the serial
                   //buffer to be sent out to the codec on the next
       return;     //serial clock cycle

 float ProcessSample(float input){
       //Perform the desired operation to create the effect
       return output;

 int main(void){
       for(int x=0; x<n-1; x++){
             samples[x] = 0;    //initialize the samples array
       }                        //before processing begins
       while(){     //endless loop
       } //Continue Receiving, Processing, and Transmitting.
                   Figure 23. Pseudocode for DSP in Time Domain.

      The ProcessSample( ) function is where the samples are modified and is changed
depending on which effect is currently programmed. Not all of the effects will use the
samples[] array.

Timing Concerns

        In order to retain signal quality, a 44.1 kHz input and output sampling frequency
must be maintained. The DSP clocked to its capacity is capable of 75 MFLOPS (75
million floating point operations per second) and can perform a multiply and add at the
same time. This equates to 1/7500000 seconds per floating point operation or about 1
floating point operation every 13.3 nanoseconds. 44 kHz equates to about 1/44000
seconds per sample or 1 sample every 23000 nanoseconds. This tells us that in order to
retain signal quality we have at the most 23000/13.3 ≅ 1730 FLOPS (floating point
operations) between sample receipts to process the signal with the output signal being
delayed by only one sample cycle. This assumes that we are processing one sample on
each pass.

Volume Control

        The volume of a sound is directly proportional to the magnitude of the sound’s
waveform. In other words, increasing the magnitude will increase the volume while
decreasing the magnitude will decrease the volume. Volume is the most natural effect
that can be performed on a digital audio signal. Each individual sample represents the
magnitude of the waveform at a given point in time. To increase or decrease the overall
volume, each sample is multiplied by a constant V.

                                Output (t ) = V * Input (t )
                                   Equation 1. Volume.

   o If V is less than 1, the volume is decreased.
   o If V equals 1, the volume remains the same.
   o If V is greater than 1, the volume is increased.

                  float Volume(float input){
                        float V = volume; //volume modifier
                        output = V * input;
                        return output;
                             Figure 24. Volume Pseudocode.

        Volume control can be efficiently implemented in conjunction with any effect
because it involves only a single floating point multiply operation. It has constant time
complexity, or O(1). It will be used as the first implemented effect and should be of great
aide in testing the software.


       The Tremolo effect causes the sound to pulse between loud and soft. It is a
modification of the Volume effect. The volume is adjusted in a sinusoidal or linear
fashion between increased and decreased volume. The parameters for this effect are the
frequency F, amplitude A, phase P, and position M of the volume modulation.

                                          ⎡ sin( F * P ) + 1     ⎤
                        Output (t ) = A * ⎢                  + M ⎥ * Input (t )
                                          ⎣        2             ⎦
                                       Equation 2. Tremolo.

   o Adding 1 makes the sine wave completely positive and dividing the result by 2
     causes it to fluctuate between 0 and 1.
   o P goes from 0 to 2π once every second linearly. Assuming the sample rate is 44
     kHz, there will be 44000 samples per second. This means that P must range
     between 0 and 2π over 44000 steps to approximate a one second interval. Each
     step will be 2π / 44000 ≅ .000143.
   o The magnitude of the volume modification is directly proportional to A.
   o The frequency of the function is F.
   o M shifts the sine wave to a different volume level.

   #include <math.h>

   float   P   =   0;               //ranges from 0 to 2*pi every second
   float   A   =   amplitude;       //determines the height of the sine wave
   float   F   =   frequency;       //determines the frequency of the sine wave
   float   M   =   position;        //determines the position of the sine wave

   float Tremolo(float input){
         output = (A*((sine(F*P)+1)/2)+M)*input;
         P += .000143;
         P %= 6.28319;
         return output;
                                 Figure 25. Code for Tremolo.

         The Tremolo( ) function is very similar to the Volume( ) function in that it
involves no loops and has a constant number of floating point operations, 8 plus the
sine( ) function. It therefore has constant complexity O(1).
         An alternative version of the Tremolo( ) function involves specifying the
maximum and minimum volume, the current volume, the rate of increase, and the
direction of increase. This will oscillate the volume in a linear fashion. It is not well
suited to be defined as an equation and is more naturally expressed in code form.

       float V = volume;                    //volume modifier
       float Max = maximum volume;          //upper volume bound
       float Min = minimum volume;          //lower volume bound
       float R = rate;                      //rate at which volume increases
       bool increase = true;                //direction of volume change

       float WahWah(float input){
             output = V * input;
             if(increase == true)
                   V = V + R;
                   V = V - R;
             if(V > Max){
                   increase = false;
                   V = V - R;
             if(V < Min){
                   increase = true;
                   V = V + R;
                    Figure 26. Code for Alternative Tremolo Function.

         This alternative Tremolo( ) function is linear, so it is not as elegant or smooth as
the function involving the sine wave. The benefit is that it doesn’t require the inclusion of
the “math.h” file and it will execute slightly faster. This speed increase is unnecessary
however as both functions are well below the calculated maximum of 1700 FLOPS.
         The resulting difference between the two effects is quite interesting, feel free to
listen to them on the included CD to see the result.


        An echo is defined as a reflection of sound, arriving at the listener some time after
the direct sound. Echoes can take many forms especially in digital signal processing. A
single echo will repeat the input sound once after a specified delay. Repeated echoes can
repeat the original echo any number of times. Repeated echoes can even save information
from the output to repeat the initial sound forever; this echo requires a reduction in the
volume of the echoed sound so that it will decline over time, otherwise the output will
quickly saturate (example of saturation on the included CD).
        An echo is implemented as a comb filter. A comb filter adds a delayed version of
a signal to itself, causing phase cancellations. The frequency response of a comb filter
consists of a series of regularly-spaced spikes, so that it looks like a comb.
        The echo effect saves information from previous samples in a large sample buffer.
At 44 kHz, or 44000 samples per second, in order to create a delay of 1 second a buffer
size of 44000 would be required. A double is 8 bytes while a float is 4 bytes, so a 1
second delay array of doubles would require 44000*8 bytes or 352 Kbytes of memory
while an array of floats would require 352/2 or 176 Kbytes of memory. Recall that the
TMS320VC33 DSP has 1 MB of memory useable as SRAM, so it is well within its
bounds. Delays over 1 second are feasible, according to the calculations a delay of up to

5 seconds is possible using floats; however I don’t foresee users desiring much over 1
        Manipulating an array of this size each cycle is not realistic. In order to
effectively use the array, an integer that tracks the current location in the array as well as
an integer that tracks the location of the desired echo or echoes will be used. These values
are then incremented and wrapped around using the modulus operator to reflect their
location in the array.

                                  Figure 27. Comb Filter.

                                  Equation 3. Comb Filter

   o The input is added to a delayed version of itself and then feeds back into the delay
   o The output is a combination of the delayed signal plus the combined input and fed
     back delay of the input.
   o This creates an echo that continues indefinitely because of the feedback.
 int n = ;                //size of the echo buffer
 float echo_buffer[n];   //initialized in main
 int echo = ;            //the location of the current echo
 int current = 0;        //location of the most recent sample
 float volume = ;        //rate of reduction of the echo
 float Echo(float input){
       //add the echo to the output
       output = input + echo_buffer[echo]*volume;
       echo_buffer[current] = output;       //update the echo buffer
       current++;                           //update the location
       current%=n;                          //location's bounds
       echo++;                              //update the echo
       echo%=n;                             //echo's bounds
       return output;
                       Figure 28. Code for Indefinitely Fading Echo.

   o The echo_buffer[] is initialized in main before the endless loop, so the clock
     cycles required for initializing 44000 values in the array to 0 are done before any
     sampling takes place.
   o The echo_buffer[] saves the current output each sample cycle, so the echoes can
     be repeated with only one addition to the input sample.

   o A volume value of 1 means the volume of the echo will not reduce, which will
     eventually destroy the sound signal. The smaller the fractional value of the
     volume, the quicker the signal fades.

        Technically, the time for this program to execute is a function of the array buffer
size because of its initialization in main so it is O(n). This occurs only once though and it
occurs before any samples are taken so the time for the actual echo function to execute is
a constant O(1).


        Reverberation is defined as so many sound reflections arriving at the same time
that the listener is unable to distinguish between them. Reverberation can greatly enhance
the sound of music. Different music types sound better with different reverberation times.
Reverberation is commonly used in conjunction with several other effects involving the
frequency domain to simulate different room sizes and types as well as to enhance the
overall sound.
        Reverberation is created by adding several echoes to a sound that are so closely
spaced that they cannot be distinguished. The main parameters of simple reverberation
are the number of echoes, the delays of each echo, and the volume reduction of the

int n = ;                      //size of the echo buffer
float echo_buffer[n];          //initialized in main
int reverb[2];                 //array containing reverb locations
                               //initialized in main
int current = 0;               //location of the most recent sample
float volume = ;               //rate of decay of the echo

float Reverb(float input){
      output = input + (echo_buffer[reverb[0]] + echo_buffer[reverb[1]]
+ echo_buffer[reverb[2]]) * volume; //add the reverbs to the output
      echo_buffer[current] = output;      //update the echo buffer
      current++;                          //update the location
      current%=n;                         //location's bounds
      for(int i=1; i<3; i++){
            reverb[i]++;                  //update the reverb
            reverb[i]%=n;                 //reverb’s bounds
      return output;
                            Figure 29. Code for Reverberation.

   o The number of reverbs can be varied. Their delays are selected pseudo randomly
     and are initialized in main.
   o See the Code for Echo section for more information, as it is very similar.
   o Oftentimes, each reverb has a different volume and is added in separately so that
     they fade at different rates.

         The reverberation application has the same features as the echo function, so the
overall program is O(n) while the Reverb( ) function is O(1).
         Modifications to Reverb( ) can be made to implement many other effects. The
most obvious spin off of Reverb( ) is Flanging. Flanging is a single reverberation whose
delay gradually varies between two small periods of time. This can be thought of as an
artificial duet, as two instruments playing the same tune will never be perfectly in sync.
Multiple Flanging delays can be mixed together to create a Chorus of reverbs.


         Distortion can come in many different forms. It takes the signal and adds
harmonic frequencies to it which distort the sound. The type of distortion that will be
implemented in the design uses a threshold value to create a distorted signal whose
amplitude is either -1, 0, or 1. The distorted signal (wet signal) and original signal (dry
signal) are then added back together. This distorted signal can also be filtered with a low
pass or band pass filter before it is added back to the original signal. The threshold for the
filter can also be modified to change the resulting distortion.

       float Distortion(float input){
             float output;
             if(input > UpperThreshold)
                   output = 1; //force everything over upper to 1
             if(input < LowerThreshold)
                   output = -1; //force everything below lower to -1
                   output = 0; //force everything else to 0
             return output;

             distorted = Distortion(input);
             //at this point, the FIR filters are invoked on the
             //distorted signal
             output = X*input + Y*distorted; //mix the signals
             //keeping in mind the delay involved with the filter
                             Figure 30. Distortion Pseudocode.

   o X and Y determine how much of either the input or distorted signals are added
     back into the output.
   o The FIR filter in the last section effect section can have its coefficients configured
     to create the desired filter to be applied to the distorted signal.

Finite Impulse Response Filter

        The time domain implementation of the FIR filter averages n/2 number of the
most recent outputs with n/2 number of the most recent inputs and sets that value as the
most recent output with n being the total number of samples stored in the buffer. It is
commonly referred to as a moving average filter. The catch of the filter is that each of the
most recent inputs and outputs are multiplied by a different coefficient before they are
averaged. The controlling factors in the function are how many “taps” (n/2) and the
coefficients. At 44 kHz the output signal will be delayed by n/2 / 44000 seconds, so for a
buffer of size 100 the delay will be .001136 seconds or 1.136 mS. The more taps there
are, the more accurately the signal can be controlled, but the greater the delay will be. For
an N-tap FIR filter with coefficients h(k), the output is described by Equation 4. The Z
transform of the filter is Equation 5.

          y ( n) = h(0) x ( n) + h(1) x( n − 1) + h( 2) x ( n − 2) + K + h( N − 1) x ( n − N − 1)
                                       Equation 4. N-Tap Filter.

             H ( z ) = h(0) z − 0 + h(1) z − 1 + h( 2) z − 2 + K + h( N − 1) z − ( N − 1)
                           Equation 5. Z Transform of N-Tap Filter.

   int n = ;         //size of the tap and coefficient buffers (even)
   float FIR_buffer[n];    //initialized in main
   float coefficients[n]; //initialized in main

   float FIR(float input){
         float output = 0;
         for(int x=0; x<n; x++){ //add and multiply by coefficients
         output = output / n;    //divide by n to get average
         for(x=n-1; x>=0; x--){ //shift the buffer over by 1
               FIR_buffer[x] = FIR_buffer[x-1];
         FIR_buffer[0] = input; //insert the most recent input
         FIR_buffer[n/2] = output;     //insert the most recent output
         return output;
                                        Figure 31. FIR Code.

                                Figure 32. FIR Filter Summation.

o The FIR_buffer array keeps track of all of the most recent inputs and outputs.
o The coefficients array is initialized in main and determines what type of filter is
  created. For example, if every coefficient is 1.0, the result is a Boxcar filter.
o The timing for this filter is O(n), n is usually a small value though so it stays well
  within the required 1700 FLOP limit.
o MATLAB’s FDAtool (Figure 33) will be used to determine coefficients for

                         Figure 33. MATLAB FDATool.


Pedal Design

         First, the pedals components must be sectioned off and examined. Through
various research and preliminary testing the best idea for the pedal was formulated. The
pedal will have one rechargeable battery supply. This power supply will allow the system
to be detachable from all wires and be rechargeable. In the case where the battery system
becomes completely discharged the option of a direct connection by an adapter will also
be possible.
         Next, the pedal will contain a rotary potentiometer that will be used to control the
amount of distortion. The potentiometer will allow the user to have complete control of
the distortion. The amount of distortion needed will be a direct representation of the
depressed pedal. The foot pedal will also contain an Analog to Digital Converter. The
output from the potentiometer will pass through the A/D Converter. The A/D Converter
will in turn generate an 8-bit code representing the voltage received from the
potentiometer. The voltage received from the potentiometer will be varying in real time
due to the depression of the pedal. Also, the pedal will contain a RF transmitter
W/integrated Encoder. The transmitter will communicate to the receiver in the box. The
transmitter will relay the 8-bit code received from the A/D Converter to the box. The
transmitter will be connected to the antenna and allow for a transmission range of up to
300ft. The antenna will be a 50 Ohm antenna and be operating at 433 MHz.

Power Supply

        The power supply used for the pedal will consist of a rechargeable battery system.
The battery system will consist of 6 rechargeable 1.2V AA NiMH batteries. These
batteries will have a rating of 1500mAH. The batteries will be discharging at 300mAH,
allowing them to supply approximately 1.2V or better for up to 5 hours.
         The rechargeable battery supply system will also be connected to the direct
power supply. The wall transformer will be supplied by CUI Inc. The transformer will
produce the needed the 9V source for the battery charger circuit.
        The Battery Charger will consist of MAX712 chip distributed by Dallas
Semiconductor. The charger will be connected by using 5 resistors, a PNP transistor, a
blocking diode, and 5 capacitors. The resistor values were calculated by the given
information on the data sheets for the battery charger. The circuit produced will hold and
charge 6AA Ni-MH batteries. The batteries will be placed in a series battery holder
during there charge state as well as there operational state. The total voltage created will
be varying between 6.6V and 8.4V. This will be assumed do to overcharging and
discharging factors. The schematic of the battery charger is viewable below in Figure 34.

                     9V       Battery Charger                             C4
                                                        R2        P1
                                                             6                           14            D1
                                                             5    TLO             DRV
                                              .01uF               THI                    8    GND
                                                             11            FASTCHG
             +                                               16
           Wall                                                                               B1
                                              C2              3                                        B4
       Transformer                                                PGM0                        1.2V
                                     R3                       4
             _                                                9   PGM1                                 1.2V
                          10uF      68K                           PGM2
                                                             10                               B2                    C3
                          C3                                      PGM3                                 B5           10uF
                                     R4                           TEMP                                 1.2V
                                                                                              B3       B6
                                    22K                       2
                                                                  BATT+                       1.2V
                                                             12                                        1.2V
                                                             15   BATT-


                          0                                                                                     0

                                    Figure 34. Battery Charger Schematic.

        The pins labeled PGM0, PGM1, PGM2 and PGM3 relate to the amount of cells
being charged. The pins labeled PGM0 and PGM1 will be set to open. This in turn allows
the chip to recognize that there are 6 batteries being charged. This charger is capable of
charging up to 16 Ni-MH batteries. The pin Ifast is used to determine the charge rate.
Since there is no constraints on the time needed for charge that pin will be set to open.
This creates the maximum charge time of 264 minutes at a charge rate of C/4. (Assume
all pins not shown are connected to ground)
                The charge rate will be set according to the need of the design. The
charger is configured to operate at 500mA and have a fast charge time of approximately 3
hrs. The chip used for this charging circuit will give us the ability of varying the charging
current. There are temperature sensors programmed on the chip to allow us monitor the
charging batteries. The various charging currents and there time approximations can be
seen below in Table 5.

                 Table 5. 6 AA cell Ni-MH 1500 mAH Charging.
Charge Rate (mA) Full Charge – 20% Loss(Hours) Full Charge – No Loss (Hours)
      500                       3.6                           3
      450                        4                           3.3
      400                       4.5                         3.75
      350                      5.14                         4.28
      300                        6                            5

              Table 6. Maxim-IC MAX 712 Battery Charger Pins.
Pin    Name     Function
1      Vlimit   Sets the maximum cell voltage
2      BATT+    Positive terminal of battery
3      PGM0     Sets number of NiMH cells
4      PGM1     Sets number of NiMH cells
5      THI      Trip point of over-temperature comparator
6      TLO      Trip point of under-temperature comparator
7      TEMP     Sense input for temperature-dependant voltage from thermistors (NA)
8      FSTCHRG Open drain, fast charge status output
9      PGM2     Sets number of NiMH cells
10     PGM3     Sets number of NiMH cells
11     CC       Compensation input
12     BATT-    Negative terminal
13     GND      System ground
14     DRV      Current sink for draining pnp transistor
15     V+       Shunt regulator
16     REF      2v reference output

Power Consumption

        The design specifications for this project stated that both the main unit and the
pedal must be able to remain active for a minimum of 5 hours on a single full charge.
After analyzing the power usage of the various components, the results show that the
whole design should be able to function for at least 10 hours. Calculating the power
consumption was approached by using the maximum ratings that this design could
possibly use and assuming that every component was operating at full power all of the
time. This obviously would not be the case in the actual usage of this device so the actual
battery life should be higher than that found here. From the data sheets on the various
components, it was found that in the main unit the power consumption was as follows:

       DSP – 200mW             EEPROM – 49.5mW                2 MUX – 25.1mW
       Codec – 54mW            LCD – 15mW                     LCD Controller – 13.2mW
       PIC – 45mW              Receiver – 23.1mW              Shift Registers – Negligible

These ratings yield a total of 0.4249W of power used by the components which will
account for nearly all of the power usage. To take into account all losses due to heat and
other factors it was decided to use the figure of 0.8W as the total power used by this
design for the calculation of battery life. This is higher than needed but it will give a good
idea of how this design performs when compared to the design specifications. By
following the same approach with the pedal components it was found that the transmitter
will use approximately 5mW of power and the ADC will use 325mW. To again take into
account losses in the design, 0.6W will be used to calculate the expected battery life of

the pedal. The six Ni-MH batteries that are used are rated at 1.2V and 1500mAh, yielding
10.8Wh. Using this value and the results found for the power used by the main unit and
pedal, the battery life is expected to be approximately 13.5 hours for the main unit and 18
hours for the pedal, therefore greatly exceeding the 5 hour minimum set in the design

Voltage Regulators

       The voltage regulator will play a key role in the supply of power throughout the
system. The voltage regulator will provide much needed stability to the system. The
battery power will be fluctuating during charging in turn producing greater voltages than
anticipated. The regulator will take these varying voltages and output the correct needed
voltage. The main components needed for power supply are the A/D Converter,
Transmitter, Crystal Oscillator and the Potentiometer.
       There will be two voltage regulators used in the production of this circuit. The
voltage regulators used will be provided by Analog Devices. The first voltage regulator
will be set to 3.3 V. The two outputs on this voltage regulator will be used to supply
voltage to the transmitter, crystal oscillator, and the potentiometer. The overall
configuration of the 3.3 V voltage regulator can be seen below in Figure 35.

                  7.2V              V3                         To Transmitter
                                8                   3
                                    VIN+    VOUT1   2
                                1           VOUT2
                                    SENSE               3.3V
                                5                   7
                                6   SHDN     VTC
                                    VSET     GND 4             To Potentiometer

                                    ADM663A              To Crystall Oscillator


                               Figure 35. 3.3 V Regulator.

         The second voltage regulator will be used to supply the Analog to Digital
Encoder. The A/D Converter will need a stable 5.0V from the power supply. The voltage
regulator used will be the same as the one used for the transmitter and the oscillator. The
pin assignments will be different in order to produce the 5.0V fixed voltage output. The
configuration of the 5.0V fixed voltage regulator can be seen below, in Figure 36.

                                                                             To ADC
                                          8                       3   5.0V
                                               VIN+     VOUT1     2
                      7.2V                1
                                          5                       7
                                          6    SHDN         VTC
                                               VSET         GND

                                              ADM663A       0

                                  Figure 36. 5 V Regulator.

          All voltage produced from the battery charger will pass through a voltage
regulator. The Ni-MH batteries do not maintain a constant discharge rate and are
susceptible to overcharging. These voltage regulators will correct the problem and
provide the needed power to the circuits.

Voltage Divider

        The use of a voltage divider will be needed to achieve the high and low voltage
for the A/D Converter. The voltage divider will also supply the A/D Converter with its
main power supply of 5.0V. The voltage divider will be connected to the 5.0V fixed
output from the voltage regulator. The basic voltage divider circuit was designed and
simulated using p-Spice; and was found to produce the needed voltage outputs. The
voltages produced are the needed 1.3V and 3.6V. The schematic of the voltage divider
can be seen below in Figure 37.

                                               To Vcc

                        R6          R8
                        321         100

                                                   To Vrt
                        1.3V            3.6V

                        R7          R9
                        113         258

                        0           0          1.3V

                                               To Vrb

                              Figure 37. Voltage Divider Circuit.

Analog to Digital Converter

        The 8-bit Analog to Digital converter will be used to interpret and convert the
voltage from the rotary potentiometer. The A/D converter will be connected to a high
voltage supply of 3.6V and a low voltage supply 1.3V as discussed earlier. The encoder
itself will be powered by the main unit supply of 5.0V fixed voltage. The voltages
described above will be achieved by the use of a voltage divider after passing through the
voltage regulator. The A/D Converter Schematic can bee seen in Figure 38 below.

               From Voltage Divider             5.0V
                Varying Voltage                                       Digital Output
                                    8                            2
                                         VIN     Vcc        D0   1
                   1.3V             4                       D1   24
                                    9    VRB                D2   23
                   3.6V                  VRT                D3   15
                                    16                      D4   14
                                         CLK     ADC        D5   13
                                    22                      D6   12
                                         OE                 D7
                                    20                           11
                                         OGND           O/UF

                          CLK            HI5714


                                         Figure 38. ADC Schematic.

       The A/D converter will process the analog voltage input from the rotary
potentiometer and digitally encoded it. The voltage received from the potentiometer will
vary between 1.555V and 3.300V. Once received the bit representation of that specific
voltage will be sent to the transmitter. The voltage 1.555V will represent the 8-bit binary
code 00000000 while the voltage 3.300 will represent 11111111. The voltages received
between these values will relay the corresponding 8-bit representation.
       The transmitter will then relay that digital code to the receiver where it will be
processed by the PIC. The PIC will in turn adjust the amount of distortion needed for that
voltage level. The pin assignments can be seen in Table 7.

                                        Table 7. ADC Pins.
                       Pin       Description     Pin   Description
                        1    Digital Output (D0) 13 Digital Output (D3)
                        2    Digital Output (D1) 14 Digital Output (D4)
                        3    NC                  15 Digital Output (D5)
                        4    Vrb 1.3V            16 Clock
                        5    NC                  17 Digital Ground
                        6    Analog Ground       18 Digital +4.8V
                        7    Analog +4.8V        19 Digital +4.8V
                        8    Analog input        20 Digital Ground
                        9    Vrt 3.6V            21 Digital +4.8V
                       10    NC                  22 Output Enabled
                       11    Underflow/Overflow 23 Digital Output (D6)
                       12    Digital Output (D2) 24 Digital Output (D7)

       The A/D Converter will have various unused pins. These pins are accounted for
and will not affect the output of the device. The device will simply be used for voltage
referencing and digital outputting to the transmitter.

Transmitter and Antenna

       The transmitter/decoder chosen is the Linx technologies TXE-433-KH. The
transmitter combines a highly optimized RF transmitter with an on-board encoder. This
transmitter paired with RXD-433-KH module will produce a highly reliable wireless link.
The chips will be able to transfer 1 to 8 parallel input along with 3^10 address
information for distances in excess of 300 feet. The address lines will be used to enable
transmission. When the address lines are set to identical values the transmitter and
receiver will begin transmission. The layout of the chip can be seen below:
                                             J1   TXE-43-KH          S1
                                   2                          13
                                   3                          14                    11
                                   7                          15                    12
                                                              16                    13
                                   8                                      4         14
                                   9                          17          5         15
                                   10                         18           6        16
                                   11      Transmitter        19          7         17
                                   12                         20          8         18
                                   5                          21          9         19
                                   6                          22          10        20
                     3.3V          1                          23          SWDIP10
                                   4                          24                               0

                                                  GND                                    GND


                             Figure 39. Transmitter and Antenna.

        The transmitter will be powered by a positive 3.3V from voltage regulator. The
transmitter will receive the information for transmission from the A/D Converter. The
signal received from the A/D Converter will then be encoded and transmitted to the
receiver on the fuzz box. The pins 2-3 and 7-12 will be used for data in on the transmitter
chip. The information transmitted will be a digital representation of the voltage values
received by the A/D Converter from the potentiometer. Those values will in turn be
decoded and examined. That value will then be matched with its appropriate distortion.
The pin assignments can be seen below in Table 8.

                            Table 8. Linx TXE-433-KH Pin.
                         Pin Name               Function
                        1      GND       Ground
                        2      D0        Data in
                        3      D1        Data in
                        4      GND       Ground
                        5      VCC       Positive supply
                        6      TE        Transmit Enable
                        7      D2        Data in
                        8      D3        Data in
                        9      D4        Data in
                        10     D5        Data in
                        11     D6        Data in
                        12     D7        Data in
                        13-22 A0-A9 Address lines
                        23     GND       Ground
                        24     ANT       RF out to 50 Ω antenna

        The antenna that will be used is also made by Linx Technologies. It was selected
because it is optimized for the frequency at which the receiver operates (433MHz) and it
can be mounted on the printed circuit board. The antenna will play a key role in the pedal
control system. The antenna contains 6 input pins. The antenna will have 5 pins
connected to ground and 1 pin connected to the transmitter chip.

Foot Controlled Potentiometer

        In order to control the distortion relayed the fuzz box a device that controls the
voltage will be needed. The device most conventional for are application is a Rotary
Potentiometer of 10K Ohm with a power rating of 5W. The device will act as a voltage
divider. When the pedal is depressed the resistance value inside of the Potentiometer will
change producing a different voltage output. The Potentiometer will allow for up to 300
degrees of rotation. The input to the Pot will be a fixed 3.3V from the main power supply
unit after voltage regulation. The schematic of this circuit can be viewed below in Figure

                                                     Varying Voltage
                                           R1          C5

                                                      .1uF      0

                             Figure 40. Potentiometer Usage.

        The potentiometer will be set to pass 3.3V through when the pedal is not being
depressed. This voltage will correspond to the high voltage on the A/D Converter and
relay to the PIC that no distortion is needed. As the pedal is depressed and the
potentiometer is rotated the voltage will drop slowly. Once the pedal is depressed
completely and the Pot has rotated its maximum of 300 degrees the voltage reading will
be 3.3V. This voltage will represent the lowest voltage in on the A/D Converter and relay
to the PIC that full distortion is needed. A picture of the design of the rotary
potentiometer connected to the pedal is shown in Figure 41.

                             Figure 41. Rotary Potentiometer.

         The picture above shows how the potentiometer will be used in the pedal. A
sleeve will be used to cover the shaft of the potentiometer to allow for the rotation to be
as smooth as possible. The saw like shaft of the pedal will rotate the potentiometer as it is
         The potentiometer will be set so that it will only rotate between 40% and 100%
of its capability. This will be implemented in the length of the shaft on the pedal. The
Potentiometer will display the outputs shown in Table 9 below. These are for a 10 K Ω
potentiometer with an input of 3.3 VDC.

                       Table 9. Calculated Potentiometer Positions.
                  Position (%) Output VDC Power Dissipated (mW)
                      100            3.30                 0.3
                       90            2.97                 0.3
                       80            2.64                 0.3
                       70            2.31                 0.3
                       60            1.98                 0.3
                       50            1.65                 0.3
                       40            1.33                 0.3

         These output voltages are sufficient for operation in the A/D Converter. The
voltages lie between the high and low references on the converter. This will enable the
outputs to be digitally transmitted. The outputs of the potentiometer not corresponding to
the range of inputs; 1.555V and 3.300V on the A/D Converter will represent 0 and will
assume no action on the box.

Crystal Oscillator

        The Crystal Oscillator will be used to create the CLK. The Oscillator contains
only four pins. The power needed to operate the CLK is 3.3V. This voltage is the same as
the voltage required by the transmitter. Therefore, the oscillator will be connected to the
same voltage regulator. The pin assignments for the Oscillator are straight forward, and
are shown below in Figure 42 for clarity.

                              Figure 42. Crystal Oscillator.

Full Schematic of Pedal System

       The entire system assembled is shown on the next page in Figure 43.

                                                              From Voltage Divider                    5.0V
                                                                                              A1                                                                                      J1       TXE-43-KH                      S1
                                            To Vcc                                                                                                                          2                                      13
                                                                Varying Voltage                                                            Digital Output                                                                           1
                                                                                         8                                          2                                       3                                      14                       11
                                                                                              VIN                           D0                                                                                                     2
  5.0V                                                                                                    Vcc                       1                                       7                                      15                       12
                R6              R8                                 1.3V                                                     D1                                                                                                     3
                                                                                         4                                          24                                                                             16                       13
                321             100                                                           VRB                           D2                                          8                                                          4        14
                                                                                         9                                          23
                                                                   3.6V                       VRT                           D3      15                                  9                                          17              5        15
                                               To Vrt                                    16                                 D4      14                                  10                                         18                       16
                1.3V                3.6V
                                                                                              CLK         ADC               D5      13                                  11        Transmitter                      19              7        17
                                                                                         22                                 D6      12
                                                                                              OE                            D7                                          12                                         20              8        18
                                                                                                                                                                        5                                          21              9        19
                                                                                         20                                         11                                  6                                          22
                                                                                              OGND                         O/UF                                                                                                    10       20
                R7              R9                                                                                                                        3.3V          1                                          23              HT640
                113             258                                         CLK               HI5714                                                                        4                                      24                                   0

                                                                                                                                                                        0                  GND                                                    GND
                0              0            1.3V To Vrb                                                                                                                                                                     Antenna

         Rotary Potentiometer                                                                                                          0

                                                                                 3                             1
                                                                                     OUT            EOH
                                            Varying Voltage
                                                                                                               Oscillator                                                                                                      0

                               R1             C5                                               3.3V

                                              .1uF        0

                                                                                                                       Q1                                                                                                                  5.0V
                       Battery Charger                                                                                 2N6109
                                                                                                    R5                                                                          Voltage regulators
                      9V                                                             C4
                                                                                                                                                                                                                                              To ADC
                                                                            P1                                                                                   7.2V                      8                            3          5.0V
                                                                                                                                                                                                 VIN+      VOUT1        2
                                                                        6                                 14                      D1                                                       1               VOUT2
                                                                        5    TLO               DRV                                                                                               SENSE
                                                                                                                                  1N4001                                                   5                            7
                                                        .01uF                THI                                                                                                                 SHDN          VTC
                                                                       11                FASTCHG                   GND                     7.2V                                            6
                                                                                                                                                                                                 VSET          GND
         +                                                             16
    Wall                                                                                                                                                                                        ADM663A
                                                        C2              3                                           B1        B4                                                                               0
Transformer                                                                  PGM0                                   1.2V
                                      R3                                4
         _                                                              9    PGM1                                                 1.2V
                                                                                                                                                                                      V3                                           To Transmitter
                           10uF       68K                                    PGM2
                                                                             PGM3                                   B2        B5
                                                                                                                                                                 7.2V             8                            3
                                                                                                                    1.2V                                                               VIN+          VOUT1     2
                                                                        7                                                                                                                            VOUT2
                                      R4                                     TEMP                                                 1.2V                                            1                                         3.3V
                                                                        1                                                                                                              SENSE
                                                                             VLIMIT                                                                                               5                            7
                                                                                                                    B3        B6                                                  6    SHDN             VTC
                                      22K                               2
                                                                       12    BATT+                                  1.2V                                                               VSET             GND 4                      To Potentiometer
                                                                       15    BATT-
                                                                             V+                                                                                                       ADM663A                                 To Crystall Oscillator

                           0                                                                                                                0

                                                                                                    Figure 43. Pedal Schematic.
Distortion Control

         The receiver will receive a digital data message from the transmitter in the pedal
whenever it is pressed. The type of data sent to the receiver will depend upon how much
the pedal is depressed. This will control how much distortion is added to the signal,
ranging from nothing at all, this being a clean audio signal played straight through, to a
fully distorted signal. When the pedal is not depressed, no signal will be sent therefore
the receiver will not receive any information and the output signal will be exactly the
same as the input signal, that is, undistorted. However, if the pedal is depressed, there
must be a means of determining how much distortion should be mixed with the original
signal. The design that was chosen was to have the transmitter send one of four possible
signals depending on how far the pedal is depressed (how this is accomplished can be
found in the section of this report pertaining to the pedal design). Once the receiver
obtains the digital signal that was sent by the transmitter, it will send this data to the PIC
which will in turn adjust two gain controls. One of these controls will be for the straight
through, undistorted signal, while the other one will control the signal that has been
modified by the DSP. As can be seen in Figure 30 below, the input signal to the main unit
is split, using a Y-adapter, sending one signal through the DSP and the other signal
straight through with no modifications. These signals, distorted and undistorted, are then
combined by the mixer circuit shown in Figure 31 and this signal becomes the output
signal. This circuit provides a good even mix of the two signals to the output and causes
almost no distortion.
         The two log trimmer potentiometers that can be seen in the main schematic are
used to control the amount of undistorted and distorted signals that will be present in the
final output signal. These are labeled as gain control 1 and gain control 2 in the main unit
block diagram in Figure 44. These allowed the gain to be adjusted as needed which is
explained shortly. These potentiometers function by accepting a digital control signal and
then adjusting the wiper position as needed. The device wiper position is set to one of
eight positions by a 3 terminal parallel port with a resolution of 5dB per step and
therefore giving a total attenuation range of 0dB to 35dB. Data will be supplied to this
port directly from the receiver via pins D0, D1, and D2, depending on the position of the
pedal. As can be seen from the main schematic there are two potentiometers, one for the
undistorted signal and one for the distorted signal, and the data going to one of them will
pass through an inverter because as mentioned earlier, as the gain is increasing on one of
them it must be decreasing on the other one. For the data string 111 the potentiometer
provides 0dB of attenuation, therefore the log trimmer potentiometer on the undistorted
signal will allow the full signal to pass, while the potentiometer on the distorted signal
will have the data string 000 (because of the inverters) and will attenuate that signal by
35dB, effectively preventing it from becoming a part of the output signal. This means that
when the pedal is not depressed, the transmitter will send 111 to the receiver and the
output signal will be undistorted. The opposite of this is true when the pedal is fully
depressed the data 000 will be sent and the attenuation on the undistorted signal will be
35dB and 0dB for the distorted signal, producing a distorted output signal when they are
mixed back together. There will also be six other levels in between these two values to
allow for a variable amount of distortion (a pressure sensitive pedal).

                                    Figure 44. Main Unit.

                                  Figure 45. Mixer Circuit.

        As can be seen in Figure 45 above, there are audio jacks at the signal input to the
main unit and at the signal output. These are basic audio jacks, part number SC1123-ND,
that will accept a guitar lead at the signal input and also a lead to go to the amplifier at the
signal output.

                                                                                                                                                                 Signal Input from Guitar                               1.2V                                                           Signal going to DSP

                                                                                                                                                                                                                                                                                                                      U4                                       U5
                                                                                                                                                                                                                                                                                                                 1                                        1
                                                                                                                                                                                                                                                                                                                 2   P0                                   2   P0
                                                                                                                                                                                                                                                                                                                 7   P1                                   7   P1                                                R6 10k
                                                                                                                                                                                                                                                                                                                     P2                                       P2
                                                                                                                                                                                                                                                                                                                 3                                        3                                                                  Signal Output to External Amplifier
                                                                                                                                                                     U2 ADM663A                                                                                                                                  6   H                                    6   H
                                                                                                                                                                                                                                                                                                                 5   L                                    5   L
                                                                                                                                              7.2V input         8                                      3                                                                                                            W                                        W                                                 R7 10k
                                                                                                                                                                         VIN+        VOUT1              2                                                                                                        8                                        8
                                                                                                                                                                 1                   VOUT2                              5V output To Log Trimmer Pots                                                                VCC                                      VCC
                                                                                                                                                                 5       SENSE                          7                                                                                                            DS1866                                   DS1866
                                                                                                                                                                 6       SHDN            VTC

                                                                                                                                                                                     0                                                                                                                                Inverters

                                                                                                                                                                     U1 ADM663A
                                                                                                                                              7.2V input         8                                      3               3.3V output To DSP
                                                                                                                                                                         VIN+        VOUT1              2                                                                                                                  J1

                                                                                                                                                                 1                   VOUT2                              3.3V output To Rx
                                                                                                                                                                 5       SENSE                          7                                                                                                             1    NC     ANT   28
                                                                                                                                                                 6       SHDN            VTC                                                                                                                          2    D0     GND   27
                                                                                                                                                                         VSET                                                                                                                                         3    D1     NC    26
                                                                                                                                                                                                                                                                                                                      4    GND    NC    25
                                                                                                                                                                                                                                                                                                                      5    VCC    A9    24               S1              0
                                                                                                                                                                                                                                                                                                                      6    PDN    A8    23
                                                                                                                                                                                                                                                                                                             0        7    D2     A7    22
                                                                                                                                                                                     0                                                                                                                                8    D3     A6    21
                                                                                                                                                                                                                                                                                                                      9    D4     A5    20
                                                                                                                                                                                                                                                                                                                      10   DATA   A4    19
                                                                                                               2N6109                                                                                                                                                                                                 11   VT     A3    18
                                                                                              R13                                                                                                                                                                                U6B      U6A                         12   D5     A2    17
                                                                                              150                                                                                                                                                                                                                     13   D6     A1    16
                     9V                                                           C6                                                                                                                                                                                                                                  14   D7     A0    15
                                                                                                                                                                                                                                                                       4     2   6       3
                                                                R12                                                                                                                                                                                                                                                        RXD433XDKH
                                                                          P1                                                                                                                                                                                                                                                                             SWDIP10
                                                                1K                                                                                                                                                                                                                                                                                                       0
                                                                      6                               14              D2                                                                                                                                                              54HSC14
                                                                      5   TLO             DRV
                                                                                                                      1N4001                                                                                                                                                                                                                                                                                                                   15                       12
                                                      .01uF1              THI                                                                                                                                                                                                                                                                                                                                                                       DIN          DOUT
                                                                                                      8     GND
                                                                   11              FASTCHG
                                                                          CC                                                                                                                                                                                                                                                                                                                        Net Name                                   6                        19       Net Name
      +                                                            16
                                                                          REF  Battery                                                                                                                                                                                                                                                                                                                                                         3    VINL     VOUTL      20
                                                      C2                                                    B8
                                                                                                                               7.2V                                                                                                                                                                                                                                                                   Analog Input
                                                                                                                                                                                                                                                                                                                                                                                                                                                    VINR     VOUTR
                                                                          PGM0 Charger
Transformer                                                         3                                                 B6                                                     U7 ADM663A                                                                                                                                                                                                                                                        21                            Analog Output
                                 R10                                4                                       1.2V                                                                                                                                                                                                                                                                                                                                    VCOM
      _                                                             9     PGM1                                        1.2V
                                                                                                                                                    7.2V input
                          10uF1 68K                                       PGM2                                                                                           8                                      3                                                                                                                                                                                                                               5
                                                                   10                                       B9                     C5                                         VIN+        VOUT1                 2                                                                                                                                                                                                                                   VREFR
                          C3                                              PGM3                                        B7           10uF                                                   VOUT2                                                                                                                                                                                                                          0
                                                                                                            1.2V                                                         1                                                                                                                                                                                                                                                                     11
                                                                      7                                                                                                  5    SENSE                             7              R8                                                                                                                                                                                                              10   BCKIN
                                        R11                               TEMP                                        1.2V                                                    SHDN              VTC                                                                                                                                                                                                                                                 LRCIN
                                                                      1                                                                                                  6                                                     385k                                                                                                                                                                                                             9
                                                                          VLIMIT                                                                                              VSET                                                                                                                                                                                                                                                                  SYSCLK
                                                                                                             B10      B11                                                                                                                                                                                                                    Net Name
                                      22K                           2
                                                                          BATT+                              1.2V                                                                                                                                                                                                                                                                                                                              16
                                                                   12                                                 1.2V                                                                                                                                                                                                                                                                                                                     18   20BIT
                                                                   15     BATT-                                                                                                                                                                                                                                                                                                                                                                     DEM0
                                                                          V+                                                                                                                                                   R9                       1.8V output to DSP                                                                     ADC Power Down (activ e low)                                                                    17
                                                                                                                                                                                                                               1M                                                                                                                                                                                                               7   DEM1
                                 C2                                                                                                                                                                                                                                                                                                                                                                                                             8   PDAD
                                                                                                                      R                                                                                                                                                                                                                      Net Name                                                                                               PDDA
                                                                                                                                                                                                                                                                                                                                               DAC Power Down (activ e low)                                                                     1   VDD
                                 1uF                                                                                                                                                                                                                                                                                                                                                                                                            2   VCC1
                                                                                                                                                                                          0                                                                                                                                                                                                                                                    24   VCC1
                          0                                                                                                    0                                                                                                                                                                                                                                                                                                                    VCC2



              SW4                SW3             SW2                  SW1
                                                                                                      270 R1

              SW8                SW7             SW6                  SW5                                                                                                                                                             ICD
                                                                                                      270 R2

              SW9               SW10             SW11              SW12                                                                                                                                                                                                                                                                                                       1                       3

                                                                                                                                                                                                                                                                                                                                                                                        GN D
                                                                                                                                                                                                                                                                                                                                                                                        VC C
                                                                                                      270 R3                                                                                                                                                                                                                                                                      EOH           OUT                                       U9
                                                                                                                                                                         U8                                                                                                                                                                                                                                                                                                                                                                                                    Net Name
                                                                                                                                                                  2                                                             15                                                                                                                                                                                                   93                                                      71

              SW16              SW15             SW14              SW13                                                                                           3          RA0/AN0      T1OSO/T1CKI/RC0                       16                                                                                                                                                              20MHZ                                92   D0                                       D16       70
                                                                                                      270 R4                                                      4          RA1/AN1       T1OSI/CCP2/RC1                       17                                                                                                                                                                                                   91   D1                                       D17       68                                                                           A0
                                                                                                                                                                  5          RA2/AN2/VREF-       CCP1/RC2                       18                                                                                                                                                                                                   90   D2                                       D18       67
                                                                                                                                                                  6          RA3/AN3/VREF+    SCK/SCL/RC3                       23                                                                                                                                                          0                                        88   D3                                       D19       65
                                                                                                                                                                  7          RA4/T0CKI        SDI/SDA/RC4                       24                                                                                                                                                                                                   87   D4                                       D20       64
                                                                                                                                                                             RA5/AN4/SS/LVDIN     SDO/RC5                                                                                                                                                                                                                                 D5                                       D21                                                                                         Net Name
                                                                                                  100K R5                                                        14                                                             25                                                                                                                                                                                                   85                                                      62
                                                                                                                                                                             RA6/OSC2/CLKO       TX/CK/RC6                      26                                                                                                                                                                                                   84   D6                                       D22       61
                                                                                                                                                                 33                             RX/DT/RC7                                                                                                                                                                                                                            82   D7                                       D23       59                                                                           A1
                                                                                                                                                                 34          RB0/INT0                                           19                                                                                                                                                                                                   81   D8                                       D24       58
                                                                                                                                                                 35          RB1/INT1             PSP0/RD0                      20                                                                                                                                                                                                   79   D9                                       D25       57
                                                                                              0                                                                  36          RB2/INT2             PSP1/RD1                      21                                                                                                                                                                                                   78   D10                                      D26       55
                                                                                                                                                                 37          RB3/CCP2             PSP2/RD2                      22                                                                                                                                                                                                   76   D11                                      D27       54
                                                                                                                                                                 38          RB4                  PSP3/RD3                      27                                                                                                                                                                                                   75   D12                                      D28       52
                                                                                                                                                                 39          RB5                  PSP4/RD4                      28                                                                                                                                                                                                   74   D13                                      D29       51
                                                                                                                                                                 40          RB6                  PSP5/RD5                      29                                                                                                                                                                                                   73   D14                                      D30       50             U13
                                                                                                                                                                             RB7                  PSP6/RD6                      30                                                                                                                                                                                                        D15                                      D31
                                                                                                                                                                 13                               PSP7/RD7                                                                                                                                                                                                                          100                                                      99        12                 13
                                                                                                                                                                             OSC1/CLKI                                          8                                                                                                                                                                                                         TDI                                      TDO                 11   A0     I/O0   14
                                                                                                                                                                     1                         RD/AN5/RE0                       9                                                                                                                                                                                                   139                                                      30        10   A1     I/O1   15
                                                                                                                                                                             MCLR/VPP          WR/AN6/RE1                       10                                                                                                                                                                                                  138   RSV0                                       A0      29         9   A2     I/O2   17
                                                                                                                                                                 11                            CS/AN7/RE2                                                                                                                                                                                                                                 RSV1                                       A1      27         8   A3     I/O3   18
                                                                                                                                                                 32          VDD                                                                                                                                                                                                                                                    133                                              A2      26         7   A4     I/O4   19                                U11
                                                                                                                                                                             VDD                                                                                                                                                                                                                                                    132   XIN                                        A3      24         6   A5     I/O5   20
                                                                                                                                                                                                                                                                                                                                                                                                                                          XOUT                                       A4      22         5   A6     I/O6   21                   6                  1
                                                                                                                                                                                         PIC18F452                                                                                                                                                                                                                                  130                                              A5      21        27   A7     I/O7                                OUT IN0    3
                                                                           R17                                                                                                                                                                                                                                                                                                                                                       98   EXTCLK                                     A6      20        26   A8                                             IN1
                                                                                                                                                                                                                                                                                                                                                                                                                                          TCK                                        A7      19        23   A9                                                    7
                                                                           1K                                                                                                                                                                                                                                                                                                                                                                                                        A8                     A10                                             EN
                                                                                                                                                                                                                                                                                                                                                                                                                                    122                                                      17        25                                                         8
                                                                                                                                                                                                                                                                                                                                                                                                                                    121   INT0                                       A9      16         4   A11                                            SEL
                                              SW17            R16 100                                                                                                                                                                                                                                                                                                                                                               120   INT1                                      A10      14        28   A12                                                   4
                                                                                                                                                                                                                                                                                                                                                                                                                                    119   INT2                                      A11      13        29   A13                                            +VS    5
                                                                                                                                                                                                                                                                                                                                                                                                                                          INT3                                      A12      11         3   A14                                            -VS
                                                                                                                                                                                                                                                                                                                                                                                                                                    136                                             A13      10         2   A15
                                                                                                                                                                                                                                                                                                                                                                                                                                    135   CLKMD0                                    A14      8              A16                                    AD8180
                                    0                                                                                                                                                                                                                                                                                                                                                                                               124   CLKMD1                                    A15      7         24
                                                                                                                                                                                                                                                                                                                                                                                                                                          EDGEMODE                                  A16                     OE
                                                                                                                                                                                               LC D M od u le

                                                                                                                                                                 Vss            1                                   2      Vdd                                                                                                                                                                                                       47                                                      5         31                                                   U12
                                                                                                                                              R14 270                                                                                                                                                                                                                                                                               125   HOLD                                      A17      4         22   WE
                                                                                                                                                                                                                                                                                                                                                                                                                                     45   MCBL/MP                                   A18      3              CE                                 6                  1
                                                                                                                                                                 Vo             3                                   4      RS
                                                                                                                                                                                                                                                                                                                                                                                  0                                                 127   RDY                                       A19      1         32                                              OUT IN0    3
                                                                                                                                                                                                                                                                                                                                                                                                                                    128   RST                                       A20      144            VCC                                            IN1
                                                                                                                                                                 R/W            5                                   6      E
                              7.2VDC IN                            U3                                                                                                                                                                                                                                                                                                                                                               102   SHZ                                       A21      142                                                                  7
                                                                           LM7805                                                             R15 1K                                                                                                                                                                                                                                                                                103   TMS                                       A22      141            AT28LV010                                       EN    8
                                                                                                                                                                 DB0            7                                   8      DB1                                                                                                               Net Name
       7.2V input     J1                1                      8                                  1                                                                                                                                                                                                                                                                                                                                       TRST                                      A23                                                                    SEL
                                                                   VIN                 VOUT                                                                                                                                                                                                                                                                                                                                          12                                                      104                                                                  4
                                                                                                                                                                 DB2            9                                   10     DB3
                                                                                                                                                                                                                                                                                                                                               HOLD                                                                                  28   CVDD                                     DR0       111   0                                                       +VS    5

                                                                                                                                                                                                                                                                                                                                                                                                                                     46   CVDD                                     DX0       106                                                           -VS
                                                                                                                                                                 DB4            11                                  12     DB5
                                                                                                                                                                                                                                                                                                                                                                                                                                          CVDD                                    FSR0
                                                     + C1                                                  + C3                                                                                                                                                                                                                                                                                                                      66                                                      110
                                                       10uF                                                  1uF                                                                                                                                                                                                                                                                                                                     83   CVDD                                    FSX0                                                             AD8180
                                                                                                                                                                 DB6            13                                  14     DB7                                                                                                               Net Name
                                                                                                                                          0                                                                                                                                                                                                                                                                                         101   CVDD                                               96                                                                       0
                                                                                                                                                                                                                                                                                                                                                                                                                                    123   CVDD                                    EMU0       95
                                                                                                                                                                                                                                                                                                                                               MCBL/MP                                                                              137   CVDD                                    EMU1
                                                                                                                                                                                                                                                                                                                                                                                                                                      6   CVDD                                               38
                                                                                                                                                                                                                                                                                                                                                                                                                                     15   DVDD                                      H1       39                                            U14
                                                                                                                                                                                                                                                                                                                                                                                                                                     23   DVDD                                      H3       107
                                                                                                                                                                                                                                                                                                                                             Net Name                                                                                     DVDD                                   CLKR0
                                                                                                                                                                                                                                                                                                                                                                                                                                     31                                                      109                                3                  1
                                                                                                                                                                                                                                                                                                                                                                                                                                     37   DVDD                                   CLKX0       114                                4   Q0     A       2
                                                                                                                                                                                                                                                                                                                                               RESET                                                                                 43   DVDD                                   TCLK0       113                                5   Q1     B                                              J2
                                                                                   0                                                                                                                                                                                                                                                                                                                                                 53   DVDD                                   TCLK1                                          6   Q2             8
                                                                                                                                                                                                                                                                                                                                                                                                                                     60   DVDD                                               48                                10   Q3   CLK
                                                                                                                                                                                                                                                                                                                                                                                                                                     69   DVDD                                  HOLDA        44                                11   Q4             9                              1
                                                                                                                                                                                                                                                                                                                                                                                                                                     77   DVDD                                   IACK        36                                12   Q5   CLR                                                   14
                                                                                                                                                                                                                                                                                                                                                                                                                                     86   DVDD                                  PAGE0        35                                13   Q6                                            2
                                                                                                                                                                                                                                                                                                                                                                                                                                     94   DVDD                                  PAGE1        33                                     Q7                                                         15
                                                                                                                                                                                                                                                                                                                                                                                                                                    108   DVDD                                  PAGE2        32                                                                                   3
                                                                                                                                                                                                                                                                                                                                                                                                                                    115   DVDD                                  PAGE3        42                                     CD74HC164                                                  16
                                                                                                                                                                                                                                                                                                                                                                                                                                    129   DVDD                                    R/W        41                                            U16                                    4
                                                                                                                                                                                                                                                                                                                                                                                                                                    143   DVDD                                   STRB                                                                                                          17
                                                                                                                                                                                                                                                                                                                                                                                                                                    131   DVDD                                               117                                3                  1                              5
                                                                                                                                                                                                                                                                                                                                                                                                                                    134   PLLVDD                                    XF0      116                                4   Q0     A       2                                           18
                                                                                                                                                                                                                                                                                                                                                                                                                                          PLLVSS                                    XF1                                         5   Q1     B                                      6
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                6   Q2             8                                           19
                                                                                                                                                                                                                                                                                                                                                                                                                                          TMS320VC33                                                                           10   Q3   CLK                                      7
                                                                                                                                                                                                                                                                                                                                                                                                                             0                                                                                                 11   Q4             9                                           20
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               12   Q5   CLR                                      8
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               13   Q6                                                         21
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    Q7                                            9
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    CD74HC164                                    10
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           U17                                                 23
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                3                  1                                           24
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                4   Q0     A       2                             12
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                5   Q1     B                                                   25
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                6   Q2             8                             13
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               10   Q3   CLK
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               11   Q4             9
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               12   Q5   CLR
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               13   Q6                                    CONN DSUB 25-P


                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                3                  1
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                4   Q0     A       2
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                5   Q1     B
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                6   Q2             8
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               10   Q3   CLK
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               11   Q4             9
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               12   Q5   CLR
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               13   Q6


                                                                                                                                                                                                                                                                                        Figure 46. Full System Schematic.

Graphical User Interface on PC

        The user interface will be written in C++ using the latest edition of Microsoft
Visual Studio for Microsoft Windows XP. The interface will be written using an object-
oriented approach. Separate modules or classes will be used for each task, with emphasis
on reusability and portability. This approach will make the completion of the interface
easier, and allow future updates and changes to be quick and efficient. This section will
contain flow charts, diagrams, and pseudo code to illustrate the end product. The manner
in which each design problem is tackled is unimportant, as long as the guidelines and
specifications are set properly.
        That said, the graphical user interface (GUI) is the human interfacing software
that will allow the user to select effects files, modify them, and update the main unit
using a standard Microsoft Windows XP PC. These effect files will be provided, and the
user will select them by navigating the contents of their hard drive and picking them.
Modifications can then be done to the effects files, if there are any attributes for that file
that are allowed to be edited (such as severity of an echo effect, or the length of a delay).
The updates will be done via a serial connection to the main unit that is only present for
this purpose. The PC only needs to be connected during the updating of the main unit.
Figure 47 shows the software flowchart of this application.

                          Figure 47. GUI Application Flowchart.

        As is illustrated, the functionality of this application can be broken down in to 4
distinctly separate parts, or modules: The main menu, the file browser, the modification
routine, and the update function.
        The main menu will display all of the status information and options available to
the user. This means displaying the status of each “slot” where effects will be placed. On
this menu, there will also be displayed the three options of browse, modify, or update. A
rough drawing of this menu is show in Figure 48 to help illustrate how this is organized.

       File    Effects       Help Exit

                Slot 1
                                           Slot 2                       Slot 3
                                        (NO EFFECT                   (NO EFFECT
                                          LOADED)                      LOADED)
                                            LOAD                         LOAD

                                       UPDATE MAIN

                             Figure 48. Sketch of GUI Menu.

The file browser is used to select various effects files from the hard drive of the PC. This
will be a standard file browser window. After a file is navigated to and selected by the
user, they will be presented with a dialog box asking them to select which slot they want
to put the effect in to. After this, they will be returned to the updated main menu that
shows the changes they just made. A file browser window similar to what will be used is
shown in Figure 49.

                            Figure 49. Example File Browser.

        The next option available is to modify effects files that have already been selected
via the browser. This will be done through numerical values entered in to dialog boxes on
or under the slot. The allowed modifications of the effects files will be user entered
integer values that correspond to attributes of the selected effect. For example, if a delay
effect was being modified, the user could have the option of entering the length of the
delay in milliseconds.
        Finally, the main unit must be updated with the newly selected and modified
effects. This will be done via the PC serial connection to the main unit. A proprietary
driver package will be used that programs the EEPROM in-circuit over this connection.
A small table of error messages will be used when failures are detected during this step.
These messages will be displayed to the user, along with any details of the failure, and
then the user will be returned to the main menu screen that will still reflect their choices
of effects and modifications. The pseudo code outline of the discussed interface is shown
here in Figure 50.

//Psuedocode Skeleton for the GUI menu
//the GUI will use an "Effect" datatype to store all currently
//used file locations and attributes
//it is overloaded to allow easy display
//an array of "Effects" will be used for keeping track of all
//information for the GUI
//all manipulation in the GUI will manipulate this array
int main(){
      Effect CurrentEffects[]; //array of effects and attributes
      displayStatus()   //shows all current slots on the box,
      displayMenu(){    //what is in them, and the attributes
                  case 'modify'
                              cout << CurrentEffects[]
                              cin >> CurrentEffects[x].attribname
                  case 'browse'
                        //starting directory for search
                        //get directory and display pertinent files
                        //load file location and attributes
                        //update slot status to show new file
                        // -> CurrentEffects[x]
                        //show user modifiable attributes
                        //save new attribute values for effect
                  case 'update box'
                        //program PIC via serial connection
                        //display error codes and common causes for
                        //errors (“Please check that device is on”)

class Effect{ //effect datatype for easy updating and display
            name //get from effects file
            attribs     //get from effects file
            overloaded cout

                         Figure 50. GUI Pseudocode.

Microcontroller Application

       The program that will be running on the microcontroller is one of the most
important aspects of this project. It controls nearly everything. It must initialize all other
subsystems of the device, and afterwards, it must control most of them. A general
flowchart for the application is shown below in Figure 51, and will be broken down and
explained further.

                        User Generated

                         Switch to New
                                                           DSP Bootload


                     Figure 51. Microcontroller Application Flowchart.

         The first thing that must be done is to initialize the PIC18F452 itself. This means
setting all the required options, including setting up interrupts, timers, or other options.
Afterwards, the rest of the devices can be initialized. The LCD is next, and it has
initialization procedures as well. These are discussed in the LCD section of the report.
Finally, the DSP boot loader must be executed as specified in the DSP section of the
report. The pseudo code for this application is shown below in Figure 52.

//Pseudocode Skeleton for PIC program
int main(){
            -setup ports that will be used
            -set PIC options
            -initialize interrupts
            -wireless chipset
                  //wait for chip to power on
            -LCD Screen
                  //wait for LCD to power on
                  //send LCD initialization
                  //configure LCD
                  //initialize DSP
      RUN() //the heart of the project - the actual control of the
                  //Bootload the DSP
            displayLCD()       //show status of pedal including current

onInterrupt(){    //this function waits for an interrupt generated by
                  //user input
      switchDistortion()//this switches the distortions and exits back
                        //to RUN() after loading the DSP again

                 Figure 52. Pseudocode for Microcontroller Application

Testing Procedures: Verification and Validation

         The proposed setup of the circuitry involves many steps where errors can occur.
The group must have a plan to diagnose and resolve any issues that will arise due to
human error, software malfunction, and hardware failure. The following will explain in
detail the procedures that have been devised to test every aspect of the project, and to
verify the functionality of each part, and then the unit as a whole.

Hardware Testing

       The transmitter and receiver pair will be tested together prior to system assembly
by powering on each unit separately. A logic value will then be applied to the transmitter,
and the receiver will be checked for the corresponding value. This will be repeated on
every pin applicable.

Digital Signal Processor
        This will be tested by connecting everything as specified and verifying that it is
receiving power. Several example programs will be run on the DSP from a PC via the
serial connector included with the DSK to verify its functionality.

        This will be tested by powering it on and checking that it is functioning. Further
functionality testing is done once the software for the microcontroller application is
being tested. An oscilloscope will be used at that point to determine that the correct
outputs are generated.

        The LCD will be tested by a small application programmed to the microcontroller
that will initialize the display after it is powered on. After initialization, a small test
message will be sent to the display. This will be visually inspected to verify functionality.

Software Testing

Digital Signal Processor
        Each effect algorithm will be programmed and tested from a PC via the included
serial port. Once programmed, the sound out from the PC will be hooked up to the audio
codec input and its output will be connected to a speaker. An mp3 file will be played and
the given effect verified. The interface between the PIC and DSP will be verified by
having the PIC program the DSP with a sample effect and testing the effect as specified.

        The microcontroller software can first be verified using the Microchip MPLAB
IDE and In-Circuit Debugger (ICD) to determine that the software produces the desired
outputs from simulated inputs. These simulations, while not reflecting that the system has
the desired functionality, will serve to show that the software produces results that are
desirable. Once the project is built, a similar test will be done with the programmed
microcontroller and an oscilloscope.

Graphical User Interface
        The application will be built using Microsoft Visual Studio, which has an internal
debugging system that will be used extensively to verify correct coding was done. The
compiled application will then be ran on a Microsoft Windows XP PC, and thoroughly
used to ensure that all functions work as described. This step will ensure compatibility
with most desktop PC systems, as the setup used will be as generic as possible.

System Testing

         Once the unit is completed, and all individual subsystems inspected, the entire
unit will be inspected as a whole. First, a physical inspection is to be performed to ensure
that all connections are properly soldered, all parts are securely in place, and that no
wires are accidentally shorted or grounded. Only after this step will power be applied to
the unit. Then, it will be gone over with a digital multimeter to ensure that each part has
the proper voltages applied to it, and that they are on. At this point, an oscilloscope can
be used to verify functionality of the all of the subsets, and that they are all
communicating. The final test of the unit will be to actually program it, connect it to a
guitar, and play while listening to the distortion. This test is known as “rocking out,” and
is performed using the listener’s ear.

Financial Budget

       The department has dictated that the cost of labor is to be $10.00 per hour of
work. It is assumed that each member of the group will be working on the project for
about 10 hours a week for all 15 weeks of the semester. The cost of labor is broken down
in Table 10.

                            Table 10. Estimated Labor Cost.
 Design Team       Cost Per      Hours Per         Number of            Estimated
    Member          Hour           Week              Weeks                Cost
John DeBacco         $10.00                 10               15         $1,500.00
James Kunc           $10.00                 10               15         $1,500.00
Eric Marinucci       $10.00                 10               15         $1,500.00
Paul Smith           $10.00                 10               15         $1,500.00
                                                 Total Cost:            $6,000.00

       The estimated cost of building this project from scratch is shown here, in Table

                           Table 11. Estimated Material Cost.
        Part Number               Brief Description Qty Cost/Unit Total Cost
SC1034-ND                Stereo Jack                 2    $6.84    $13.68
CU-3284                  Plastic Box                 1   $10.60     $8.85
T210-P7P-ND              AC Adapter                  2    $3.63     $7.26
KODAK 2300               1.2V Ni-MH Batteries        6   $2.42     $14.52
TMS320VC33PGE120         DSP                         1   $19.77    $19.77
AT28LV010                EEPROM                      1   $49.24    $49.24
CD74HC164                Shift Register              4    $0.72     $2.88
RXD-433-KH-ND            Receiver                    1   $15.93    $15.93
ANT-433-SP               Antenna                     2    $2.08     $4.16
Lab X-1                  X-1 board                   1 $105.00 $105.00
HI5714/4CB-ND            ADC 8-bit 40MSPS 24-SOIC    2    $9.45     $9.45
TXE-433-KH-ND            Transmitter                 1    $9.98     $9.98
CTX306TR-ND              OSC Clock 20.0MHz 5.0V SMD 2     $0.96     $1.92
MAX712                   Battery Charger             2    $7.71    $15.42
ADM663A                  Voltage Regulator           5    $2.22    $11.10
PIC18F452                PIC Microcontroller         1    $6.66     $6.66
DS1866                   Log Trimmer Potentiometer   2   $1.26      $2.52
CFR-25JR-300R            RES 300 OHM 1/4W 5%         1   $0.06      $0.06
CFR-25JB-82R             RES 82 OHM 1/4W 5%          2   $0.06      $0.12
CFR-25JB-110R            RES 110 OHM 1/4W 5%         1   $0.06      $0.06
CFR-25JB-240R            RES 240 OHM 1/4W 5%         2   $0.06      $0.12
In stock                 Various Capacitor Values    2      0         0
In stock                 Various Resistor Values     2      0         0

Team Funding

        The material funding for the team has been set by the department at $100 per
team member. The group consists of four members, yielding a total of $400 for the
design of this project.
        There are no additional sources of funding. Any additional costs above the budget
will be paid out of pocket by the group members.

Project Schedule

        The following table and figure show the design strategy that will be used by the
team. Table 12 shows the design Gantt chart, and Figure 53 shows this information in a
timeline view. Table 13 shows the Gantt chart of the implementation phase of the project.
It includes detailed descriptions, and shows the hierarchy of the individual tasks that must
be completed. Figure 54 shows this information pictorially.

                                                         Table 12. Design Gantt Chart.
ID   Task Name                                       Duration       Start           Finish      Predecessors   Resource Names

1    Introduction                                        9 days   Mon 8/29/05      Thu 9/8/05
2    Block Diagrams                                    21 days    Mon 8/29/05     Tue 9/20/05
6    Design Specifications                               5 days    Tue 9/13/05    Sun 9/18/05 4                Eric Marinucci,James Kunc,John DeBacco,Paul Smith
7    Alternative Design Analysis                        7 days    Sun 9/18/05     Sun 9/25/05 6
29   Alternative Design Presentation                     7 days    Sun 9/18/05    Sun 9/25/05 6
30   Progress Reports                                  56 days    Sun 9/25/05    Sun 11/20/05
39   Accepted Project Design                           69 days    Sun 9/25/05     Sun 12/4/05 29
40       Design Gantt Chart                              7 days    Sun 10/2/05    Sun 10/9/05 31               James Kunc,Paul Smith
41       Software Design                               56 days    Sun 9/25/05    Sun 11/20/05
42            Pseudo Code for DSP                       56 days    Sun 9/25/05   Sun 11/20/05                  James Kunc
43            Pseudo Code for DSP / PIC Interface       56 days    Sun 9/25/05   Sun 11/20/05                  James Kunc,John DeBacco
44            Pseudo Code for PC and PIC / PC Inte      56 days    Sun 9/25/05   Sun 11/20/05                  James Kunc,John DeBacco
45            Pseudo Code for PIC Control               56 days    Sun 9/25/05   Sun 11/20/05                  John DeBacco
46       Hardware Design                               56 days    Sun 9/25/05    Sun 11/20/05
47            Rechargeable Battery System               56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,Paul Smith
48            Pressure Sensitive Pedal                  56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci
49            Transceiver in Pedal                      56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci
50            Antenna for Pedal and Box                 56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci
51            LCD Display                               56 days    Sun 9/25/05   Sun 11/20/05                  Paul Smith
52            Power System for Main Unit                56 days    Sun 9/25/05   Sun 11/20/05                  Paul Smith
53            Filter Design                             56 days    Sun 9/25/05   Sun 11/20/05                  Paul Smith
54            Transceiver in Main Unit                  56 days    Sun 9/25/05   Sun 11/20/05                  Paul Smith
55            Simulations (Compatability)               56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,James Kunc,John DeBacco,Paul Smith
56            Schematics                                56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,James Kunc,John DeBacco,Paul Smith
57            Parts Request Form                        56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,James Kunc,John DeBacco,Paul Smith
58       Budget (Estimated)                             56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,James Kunc,John DeBacco,Paul Smith
59       Testing Procedures                            56 days    Sun 9/25/05    Sun 11/20/05
60            Hardware Procedures                       56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,James Kunc,John DeBacco,Paul Smith
61            Software Procedures                       56 days    Sun 9/25/05   Sun 11/20/05                  Eric Marinucci,James Kunc,John DeBacco,Paul Smith
62       Project Poster                                 21 days    Sun 10/9/05   Sun 10/30/05 40               Eric Marinucci,James Kunc,John DeBacco,Paul Smith
63       Implementation Gantt Chart                     27 days   Sun 10/30/05   Sun 11/27/05 62               Eric Marinucci,James Kunc,John DeBacco,Paul Smith
64       Final Design Presentation                       7 days   Sun 11/27/05    Sun 12/4/05 63               Eric Marinucci,James Kunc,John DeBacco,Paul Smith
65       Final Design Report                            69 days    Sun 9/25/05    Sun 12/4/05 1                Eric Marinucci,James Kunc,John DeBacco,Paul Smith

     4, '05        Aug 28, '05        Sep 11, '05           Sep 25, '05        Oct 9, '05        Oct 23, '05         Nov 6, '05        Nov 20, '05           Dec 4, '05
       T      M   F    T      S   W    S     T        M    F    T      S   W    S       T   M   F     T      S   W    S      T    M   F    T      S      W    S       T   M
6                                                   Eric Marinucci,James Kunc,John DeBacco,Paul Smith
40                                                                             James Kunc,Paul Smith
42                                                                                                                                      James Kunc
43                                                                                                                                      James Kunc,John DeBacco
44                                                                                                                                      James Kunc,John DeBacco
45                                                                                                                                      John DeBacco
47                                                                                                                                      Eric Marinucci,Paul Smith
48                                                                                                                                      Eric Marinucci
49                                                                                                                                      Eric Marinucci
50                                                                                                                                      Eric Marinucci
51                                                                                                                                      Paul Smith
52                                                                                                                                      Paul Smith
53                                                                                                                                      Paul Smith
54                                                                                                                                      Paul Smith
55                                                                                                                                      Eric Marinucci,James Kunc,John De
56                                                                                                                                      Eric Marinucci,James Kunc,John De
57                                                                                                                                      Eric Marinucci,James Kunc,John De
58                                                                                                                                      Eric Marinucci,James Kunc,John De
60                                                                                                                                      Eric Marinucci,James Kunc,John De
61                                                                                                                                      Eric Marinucci,James Kunc,John De
62                                                                                                           Eric Marinucci,James Kunc,John DeBacco,Paul Smith

                                                       Figure 53. Design Gantt Chart Timeline View.

Table 13. Implementation Gantt Chart Tasks.

     , '06        Jan 15, '06     Jan 29, '06         Feb 12, '06        Feb 26, '06       Mar 12, '06        Mar 26, '06      Apr 9, '06         Apr 23, '06      May 7, '
        T    M   F    T     S   W  S    T     M      F    T     S    W    S    T     M    F    T     S   W     S    T     M   F    T      S   W    S     T    M   F   T
4                            0%
5                                  0%
6                                                     0%
7                                                      0%
8                          0%
9                                  0%
10                                         0%
11                                                    0%
12                                                                        0%
13                                                              0%
14                                                              0%
15                                                                       0%
16                                                                                        0%
17                                                                                        3/10
18                                                                       0%
19                                                                                  0%
20                                              0%
21                                   0%
22                                            0%
23                                              0%
24                                   0%
25                                            0%
26                                                       0%
27                                                                                  0%
28                                                                                  3/5
29                                                                                                                                                         0%
30                                                                                                0%
31                                                                                                           0%
32                                                                                                                     0%
33                                                                                                                            0%

                                          Figure 54. Implementation Gantt Chart Timeline View.

Design Team Information

James Kunc
Computer Engineer
Team Leader
DSP Design

John DeBacco
Computer Engineer
GUI Design, Microcontroller Design

Eric Marinucci
Electrical Engineer
Wireless System Design, Pedal Design

Paul Smith
Electrical Engineering
Power Systems

Conclusions and Recommendations

        The project presented above was conceived because of the recognition that, with
the technology available today, there is no reason for a guitar player to own more than
one distortion pedal. Most serious guitar players that like distortion pedals own multiple
pedals, if not dozens. The capabilities of this project make it a universal distortion pedal.
Since no new hardware will ever need to be added, the software potential is the only
limiting factor. As this report has expressed, though, that is hardly a limit.
        Many devices on the market today in the audio trade are designed with engineers
or technicians in mind. The appeal of this device is the simplicity. Each subsystem of the
device was designed with ease-of-use in mind. It is to be as consumer friendly as
possible, and as easy to use as possible. No degree in engineering will be required to
operate this device.
        The project was also designed to be easily modified. Any future updates or ideas
can be implemented with very little hassle. This is important, since the group had many
ideas that were constrained by time. A hand-held or guitar mounted remote control of the
device, for example, will not be realized in the final design, but would not, after the rest
of the project is completed, be hard to implement. In the future, many of these ideas
could still be added with minimal effort.


Microchip PIC18F452 Data Sheet

Linx technologies TXE-433-KH Data Sheet

TMS320VC33 Data Sheet

PCM3003 Data Sheet

Lab X-1 Summary Sheet

DM2023 Data Sheet

Acoustics / Audio / DSP Links - Academic and Non-Academic

Fast Fourier Transform Stuff

Sound Processing Kit Home Page

Clear, Efficient Audio Signal Processing in ANSI C

Music-DSP Source Code Archive

Digitized Sound - Understanding Samples, Rates and Digital Audio

All-Pass from Two Combs Article

Finite Impulse Response Properties


           Figure 55. DSP Starter Kit Schematic.