Digital Integrated Circuit Design I
http://ece.pdx.edu/˜ecex25/course/x25/pdf/syllabus.pdf 〈Syllabus in PDF〉
Portland State University ECE 425/525
Instructor: W. Robert Daasch, email@example.com, FAB 160-14
Ofﬁce Hours: MW 1:00-3:00PM or by appointment
Class Meeting: TR 6:40-8:30PM, URBN 204
TA: Muhammad Akhtar
TA Ofﬁce Hours: MF 9:00AM-11:00AM, VLSI Lab,
Text: Principles of CMOS VLSI Design, 3nd Edition, Weste and Harris
Others: CMOS Digital Integrated Circuits (Analysis and Design), 2nd Edition, Kang
Digital Integrated Circuits, A Design Perspective, J.M. Rabaey
VLSI Design Techniques for Analog and Digital Circuits, Gieger, Allen and Strader.
The Modern VLSI Design, W. Wolf
The Design and Analysis of VLSI Circuits, L. Glasser and D. Dobberpuhl
Course URL: http://ece.pdx.edu/˜daasch/course/x25
Streaming URL: http://www.media.pdx.edu is listed as ECE 525.
Textbook URL: http://www.cmosvlsi.com/ with errata occasionally updated
Deadline for forming and approval of laboratory team is October 9th.
This is the ﬁrst term of an approved two term graduate sequence and an approved undergraduate
sequence ECE 425 and ECE 426. ECE 525 and ECE 526 are prerequisites for third term ECE
527. The ﬁrst term’s goals are to learn three large signal device models for the MOSFET and use
them in simple design problems; to introduce the steps used in MOSFET fabrication and begin
the study of CMOS circuit and logic design. A laboratory is integrated into the lecture. Students
will gain skills in device and small scale integrated circuit simulation, CMOS IC layout, and ver-
iﬁcation and validation of design speciﬁcations.
Coverage: Chapters 1-4 (Light on Chap. 3, Fabrication); introduction to the NFET and PFET,
modeling, fabrication as well as the passive linear and nonlinear circuit elements
in a modern CMOS technology. Chapters 5-7; static CMOS logic circuits (power,
delay and other performance characteristics) and, pass transistor (Chapter 7.5).
Chapter 8-9; dynamic circuits and, ﬂip-ﬂops and latches. Chapter 10 (time per-
mitting); memories. Recommended homework will be assigned weekly.
Tools: Cadence IC 5.0. Either VLSI Laboratory ECE logins or a X-windows enabled PC
(eg. Cygwin) is required to access the CAE packages.
Technology: The lecture will focus on behavior of n(p) channel MOS enhancement devices
with depletion and zero threshold devices used in some circuits. Scalable
(lambda) CMOS design rules are used in the laboratory. Devices models are based
on 0.25 and 0.18 micron CMOS n-well technologies.
Background: Undergraduate: 1 high level programming language, logic design, MOS electron-
ics. Prerequisites 323.
Graduate: MOS ICs, logic and analog simulation CAD tools, basic layout geome-
try of MOS ICs.
Laboratory: With the high enrollment laboratory will be done in small teams of three. All
groups must be approved in advance. Email subject line and zip ﬁle basename are
assigned to the team before, October 5th.
Submissions are electronic and only a single zip ﬁle of the PDFs of required ﬁles
for each lab report are accepted. Filenames are a concatenation of groupnum-
ber_labnumber_ﬁlename.pdf Grade summaries (ASCII) are returned to the sender
of the team.
Laboratory work will be graded by the TA. Generally speaking, the laboratory
will require no access to hardcopy. Printing accounts are available for the
Four labs will be assigned this term. Each laboratory is roughly two weeks in
duration. Labs will have speciﬁc due dates. Late labs may be accepted however,
the late report will be graded on a decreasing, sliding scale. Late reports will not
be accepted after on-time reports are returned, roughly one week after its due
The FAB VLSI and Intel labs are open to EE/CpE students from 8AM-5PM Mon-
day through Friday. Accounts will be set up for each student. During open hours
all systems in the VLSI lab can be used. There are, however, other classes using
these facilities on a similar unscheduled basis. To be considerate of your class-
mates and other ECE students use your time wisely and personally restrict your
login sessions to 2 hours or less.
Grading: Students will be graded using a total of 400 pts.; midterm is 100 pts, the 5 labs
normalized at the end of the quarter to 100 pts, and a ﬁnal is 200 pts.
Exams are closed book and no notes. Partial credit for incomplete exam answers
is given. Make-up exams are discouraged and must be arranged at least one class
period before the exam.
The course is taped but not a substitute for regular attendance. Attendance is
encouraged by the following program. Begining October 10th a class roster sheet
will be distributed every class period and signed by students attending class.
Lower attendance changes the partial credit grading. Exam grading is on a three
step credit scale 100%, 50%, and 0% for attendance between 33% and 50% (i.e.
less than one class per week and better than one in three). Attendance of less than
33% grading is a two step scale 100% and 0%.
Separate grade scales will be set for ECE 425 and ECE 525.
A total score of 95% or more is assigned a grade of A. For an average number of
points, the grade will range between B− to B+ depending on class performance. A
total score of less than 50% will be assigned a grade no higher than C − . As deter-
mined by the instructor a failing percentage may be set and graded with an F.