Silicon wafer packaging for HB-LEDs

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Silicon wafer packaging
      for HB-LEDs



Technology White Paper



       Tom Murphy
     Jochen Kuhmann




     Issue 1.0 September 2007
                        Silicon wafer packaging for HB-LEDs

                                  Tom Murphy, Jochen Kuhmann

Introduction
The growth rate of the LED market is set to increase fuelled by current demand and new
applications. These new sectors bring fresh challenges for LEDs including improved thermal
management, extended lifetime, increased functionality and operation under harsh conditions. The
choice of packaging has a major influence on the cost and performance of LED modules. Some of
the packaging requirements for high-brightness LEDs are listed below:

           –   High thermal conductivity for power dissipation in excess of Watts
           –   Optimised optical efficiency and performance
           –   Small size
           –   Versatile design concept
           –   Hermetic sealing possible
           –   Low cost

We present here the HyLED™ solution, a new approach to packaging particularly suited to
applications with high demands on optical and thermal performance combined with increased
functionality and small size. Hymite has previously demonstrated silicon wafer level packaging for
RF applications requiring hermetic sealing [1], [2] and [3]. These applications utilised precision
silicon micro-machining and 3D lithography to obtain high-frequency performance with minimal
distortion and improved manufacturing repeatability.

The applications at hand exploit the thermal and mechanical properties of silicon to provide a robust
package with the associated advantages of silicon micro-machining. Metal coatings and 3D metal
lithography provide design flexibility to match customer LED designs and improved optical
performance.

In the following sections, schematic representations of the manufacturing processes associated
with HyLEDTM are outlined. Example customer designs and open tool samples are presented and
thermal and optical characteristics outlined.




                                                                                                   1
Overview of HyLEDTM
The 3D sectioned schematic in Fig. 1 shows the main features of HyLEDTM where the part is shown
without an assembled component. LEDs are placed into etched cavities which act as reflector,
thermal contact and reservoir for silicone/colour converter gel. Smaller cavities are etched from the
other side and are subsequently coated with conducting metal to form vertical electrical
feedthroughs. Structured plated and thin film on the cavity base forms landing pads for the LED.
The cavity walls are mirror coated. The package shown in Fig. 1 is for LEDs with wire bond
electrical contacts. Designs for flip-chip LEDs will be discussed in a later section.




Fig. 1 Schematic diagram of sectioned HyLEDTM package. (1) Micro-machined silicon (2) metal coated
vertical feedthroughs (3) mirrored cavity sidewalls (4) die attach pad for LED (5) anode and cathode pads (6)
electrically isolated thermal contact pad
The design of Fig. 1 has three SMD contacts, anode, cathode and an electrically isolated thermal
pad. This allows separation of signal and ground or thermal pad. This is further illustrated in Fig. 2.



                                                                                             Electrical path
                                                                                             Thermal path
Fig. 2 Sectioned schematic of HyLEDTM on metal
core PCB with isolated electrical and thermal paths

                                                                                                 PCB pads


                                                                                               Metal core PCB



Some advantages of silicon as a material for HB-LED packages are listed below:
            –   Excellent thermal and mechanical properties
            –   KOH etched vertical feedthrough vias mean smallest SMD package size
            –   Improved reliability compared to plastic/polymer packaging materials
            –   No UV degradation of lens/lid-attach epoxies with anodic or AuSn attached lens/lids
            –   Hermetic sealing, an option with either anodic bonding of glass to silicon wafers or a
                AuSn reflow of a lens/lid wafer
            –   Small silicon micro-machined structures and tight array packaging increase
                homogeneity for colour conversion and better colour mixing



                                                                                                               2
Manufacturing
The package processing steps and subsequent assembly is shown schematically in Fig. 3. The
steps outlined are for a flip-chip LED and an optional lid/lens attach process is included.

                                                                   Mirrored       AuSn
                                                                   walls          bumps




1) Wafer etching                                     2) Metal coating and 3D structuring

                   Colour       Lid/lens         Application PCB
   LED             converter/   wafer
                   silicone




3) Wafer level assembly                              4) Board assembly


Fig. 3 Schematic representation of package processing and assembly steps. Steps are shown for a flip-chip
LED and an optional wafer level lid/lens attach step.


1) Wafer etching: batch KOH wafer etch processes form deep cavities for the LEDs on one side of
the wafer and via feedthroughs from the other.
2) Metal coating and 3D structuring: the vias are coated with metal forming electrical
interconnects. Subsequent 3D structuring forms the die attach pads, SMD pads, the electrical
rerouting circuits and the mirror walls. AuSn may be deposited in the cavity matching the pad
structure of a flip-chip LED.
3) Wafer level assembly: using flip-chip LEDs as an example, the devices are placed in the
cavities and a reflow step simultaneously electrically contacts all LEDs. The cavities are filled with a
silicone for LED protection and if required colour conversion. Wafers scale lids or lenses may be
attached using either anodic bonding, AuSn reflow or epoxy attach. (Further details on lid attach
follow)
4) Board assembly: the wafer is diced and the individual LED packages are SMD mounted onto
PCB boards.

Lens or Lid attach
Three lens or lid attach methods exist for HyLEDTM; epoxy attach, anodic bonding and AuSn solder
attach. The choice of lens or lid attach is governed by the application requirements and process
compatibility. Sealing is then chip-to-chip (CtC) where a single lens/lid is placed on a singlulated
package, chip-to-wafer (CtW) where a single lens/lid is attached to a wafer or wafer-to-wafer (WtW)
where lens/lid and package wafer are attached in one step, sealing all packages simultaneously.




                                                                                                       3
All three lid attach methods are WtW compatible. Some further details of the three technologies
follow:

Epoxy Attach: This process is applicable to most lens/lid materials and has the advantage of low
temperature processing. Epoxy can be either dispensed, screen printed or applied as preforms. The
type of epoxy used depends on the lens/lid material and process limitations.
Anodic bonding: Pyrex glass lens/lids are used for anodic bonding. Process temperatures of
300°C and applied voltages of 200 to 1000V are necessary. This sealing method is hermetic.
Solder attach: This sealing technology combines anodic bonding and solder attach. “Windows”
are etched through a silicon wafer which is anodically bonded to a pyrex glass wafer. The
composite wafer structure is metallised providing a AuSn solder ring on the lens/lid. A
corresponding gold metal ring is required on the LED package. After assembly of devices into the
cavities, the wafers are aligned and a single reflow step hermetically seals both wafers. This
method is also applicabable to C2C or C2W.

A summary of this information is included in Table 1 and an example lens wafer [5] and a schematic
representation of CtC epoxy attach of a lens/lid is shown in Fig. 4.

Table 1 Summary of HyLEDTM lens/lid attach technologies

                                                                                              CtW / CtC
          Description            Lens/lid material     Process parameters        Hermeric
                                                                                              compatible
          Epoxy attach            Polymer or glass      Dependant on epoxy
                                                               300°C
          Anodic bonding         Pyrex glass
                                                           200     1000V
                                 Silicon / pyrex
          AuSn solder attach                                   320°C
                                 composite wafer




                                                                                                         Lid/lens


                                                                            Epoxy




Fig. 4 6” HyLEDTM wafer with wafer level micro-optic lenses (left) and schematic of CtC epoxy attach of lens/lid
attach (right)




                                                                                                                    4
Applications of silicon HB-LED packages
Application examples for silicon-based HB-LED packages are shown in Fig. 5.




Fig. 5 Application examples of HyLEDTM showing a section of a complete wafer (left), a diced package with
AuSn solder bumps for a flip-chip LED (center) and an assembled open tool HyLEDTM sample (right)
Hymite provides open-tool samples for customer evaluation and also customer specific solutions.
Details of the open tool samples are included in Table 2 together with a technical drawing in Fig. 6.

Table 2. List of parameters for the HyLEDTM open tool sample


             Parameter                                 Comment
             Package material                          Silicon
             Cavity wall coating                       Aluminium
             LED die attach pad in cavity              Au
             SMD metallisation                         UBM for solder attach
             LED attach in package                     Soldering or epoxy
             LED electrical connection                 Flip-chip soldering and/or wire-bonding
                                                       (Requires AuSn on LED for reflow)
             Package dimensions                        2.8 × 2.8 × 0.65 mm
             LED die attach pad dimensions             1.0 × 1.0 mm
             Maximum current rating                    3A (9W)
             Thermal resistance (junction-to-board)    <5 K/W




Fig. 6 Technical drawing of HyLEDTM open tool design


                                                                                                       5
Performance data
Thermal performance
Theoretical modeling: The Ansys Finite Element Model (FEM) tool was used to examine the
thermal performance of the open tool HyLEDTM package and test board. The bottom surface of the
metal core PCB was set to 25°C and the heat generated by the active area of the LED was 1W.
This implied that the effective thermal resistance can be read directly from the model results in K/W.
The LED has a single pad of side length 760 µm. We modeled an active-side-down LED with an
AuSn reflow die attach process. The thermal parameters used are included in Table 3.

                                                                              Table 3. List of parameters used in thermal
                                                                                               model of HyLEDTM package
Solder dam on MCPCB
(Not in the thermal path)                                                                Material                      Thermal Conductivity
                                                                                                                       (W/mK)
                                                                                         AuSn                          57
                                                                                         Silicon                       150
                                                                                         Solder                        57
                                                                                         (SnAgCu)
                                                                                         Copper                        390
                                                                                         FR4                           0.5
                                                                                         Aluminium                     200
Fig. 7 Sectioned schematic showing the materials in
the thermal path of the assembled package


Results from the thermal modeling are included in Fig. 8
                                                                                                                              Aluminium
                                                                                                             Copper




                                                                  45
                                                                                                   Solder
                                                                               Silicon
                                                                       AuSn




                                                                                                                        FR4




                                                                  40
                                               Temperature / °C




                                                                  35



                                                                  30



                                                                  25



                                                                  20
                                                                    0.0           0.1                  0.2            0.3      0.4
                                                                                               Distance / mm




Fig. 8 Results from the Ansys thermal analysis of the LED package showing temperature distribution across
the LED active area (left) and a vertical temperature profile through the assembly (right)




                                                                                                                                          6
The results of Fig. 8 estimate a thermal resistance of 15 K/W from junction to the bottom of the
metal-core PCB. It is important to note that the major contributors to the latter value are the solder
attach of the package to PCB (thickness 50 µm) and the FR4 insulating layer on the board
(thickness 50 µm).

Experimental results: An active-side-down EZ1000 blue LED from Cree with pad side length of
980 µm was reflow soldered to an open tool HyLEDTM package and mounted onto a metal core PCB
test board. The test board was placed on a thermo-electric cooler (TEC). The temperature gradient
end point was determined by placing a probe on the TEC and PCB’s upper side, as shown in Fig. 9.
The measurement consists of two steps. In the first, the V-I characteristics of the LED are measured
using a pulsed current source at a controlled temperature in an oven. No electrical heating of the
junction takes place and the relationship between the junction temperate and V-I is established. The
V-I characteristics are then measured under CW conditions where the electrical heating of the LED
increases the junction temperature. The cross-over points of the pulsed and CW curves allow
estimation of the junction temperature. More details on the measurement are given by Y. Xi and E.
F. Schubert [4].

                      Thermoelectric
                                                         3.3
                      cooler
                                                         3.2

                                                         3.1
                                           Voltage / V




                                                         3.0
                                                                                                                     25°C
                                                         2.9                                                         30°C
                                                                                                                     35°C
                                                         2.8                                                         40°C
                                                                                                                     45°C
                                                         2.7                                                         50°C
                                                                                                                     55°C
                                                         2.6                                                         CW

                                                         2.5
                  Temperature
                  probe                                        0   50   100   150     200    250   300   350   400
                                                                                    Current / mA



Fig. 9 Determination of thermal resistance, set-up (left) and results from pulsed and CW measurements
(right)


The thermal resistance was measured to be <5 K/W junction-to-board and 15 K/W junction to the
underside of the metal-core PCB. This is in very good agreement with the theoretical values of the
previous section. As stated in the previous section, the main contributor to the thermal resistance in
the FR4 layer and experiments are underway with PCBs having dielectric materials with increased
thermal conductivities to improve overall system performance.

The results are best-in-class considering the very small size of this package type.




                                                                                                                            7
Radiation patterns
The angular spectra were measured by positioning a large area detector 0.75 m from the LED and
rotating the part 180° about its own axis. We investigated the open-tool sample described
previously together with the EZ1000 blue LED from Cree. This emitter has an active area of 1 mm².
Measurements were performed with and without micro-optic lenses from Heptagon [5]. No silicone
or matching gel was used in the cavity. It is worthwhile to note that inclusion of the (wafer scale)
lenses do not increase the footprint requirements of the LED.



                                                                                                                      with lens
                                                                                                                      no lens




                                                  Intensity / ard unit




                                                                         -80   -60   -40   -20   0     20   40   60     80
                                                                                             Angle / deg



Fig. 10 Measurement of radiation patterns. Assembled package with Heptagon micro-optic lens (left) and
angular spectra with and without lens (right)



The results shown in Fig. 10 indicate a FWHM radiation pattern of 100° without lens and 70° with
lens. It should be noted that the lens in question was not designed for HyLEDTM. The tests were
designed to show that wafer level optics can be used for beam forming of the LED radiation. For
optimized results a dedicated lens design is required.




                                                                                                                                  8
Market positioning of HyLEDTM

Thermal performance and size
HyLEDTM is the obvious solution where high demands on performance are combined with small size
requirements. There follows a list of possible applications:
          – Automotive interior or daytime running lights
          – Accent/mood lighting
          – Back light units
          – Harsh environments requiring hermetic sealing
          – Deep UV operation such as medical/dental sources
          – Colour mixing applications with tight size and rendering requirements


Using data sheet values for required footprint area on the application board and junction-to-board
thermal resistance, we compared HyLEDTM to a range of other commercially available package
styles (with 1 mm² LED, drive current between 350 and 1000 mA). The result of the comparison is
graphically represented in Fig. 10: HyLEDTM offers the same power and thermal resistance
performance with a much reduced board real estate.




                                                      0.9
                Thermal resistance / Footprint Area




                                                      0.8

                                                      0.7

                                                      0.6

                                                      0.5

                                                      0.4

                                                      0.3

                                                      0.2

                                                      0.1

                                                            K2   Xlamp              Rebel   HyLED
                                                                         LED type
Fig. 11 Comparison of thermal resistance / footprint area for range of LEDs




                                                                                                    9
Conclusions
We have presented HyLEDTM, a silicon wafer packaging solution for HB-LEDs. The manufacturing
steps are semiconductor-industry established batch processes ensuring high volume capability and
maximized yields. This ensures a cost effective solution in this competitive market. The high
performance for smallest size provides application design flexibility and reduces real-estate
requirements on metal core PCBs, further lowering system costs.
Customer designs and open tool samples were discussed and data for the later presented.
A summary of features of the presented solution follow:

           –   LEDs mounted in etched cavities in silicon which act as reflector, thermal contact
               and reservoir for silicone/converter gel
           –   Vertical feedthroughs form electrical contacts to SMD side
           –   AuSn on cavity base for a solder reflow attach of a flip-chip LED is possible
           –   Wafer level assembly, testing and lens/lid attach process steps
           –   Presented an open tool package for 1 mm² LEDs with size 2.8 × 2.8 × 0.65 mm³
           –   Thermal resistance junction-to-board of <5 K/W giving a better size/thermal
               performance ratio compared to state-of-the-art packaged LEDs
           –   Radiation pattern FWHM values of 70° and 100° with and without wafer scale micro-
               optic lens, respectively. Including the lens does not increase the footprint size of the
               package




                                           REFERENCES


1
    R. Hauffe et al, “Optimized Micro-Via Technology for High Density and High Frequency (>40GHz)
Hermetic Through-Wafer Connections in Silicon,” Proc 55th Electronic Components and Technology Conf.,
Orlando, FL, 2005, pp. 324-330.
2
    M. Winter et al, “Application and RF Performance of Integrated Resistor Structures on Non-Planar
Topologies in Micro Machined Silicon Packages for Transmitter Optical Subassemblies”, ECTC 2006
3
    M.Winter et al, “Simplified Optical Coupling and Alignment Scheme for Cost Effective 10 Gbit/s TOSA
Modules Based on Edge Emitters Hermetically Packaged in Micro-Machined Silicon Structures”, OFC 2005
4
    Y. Xi and E. F. Schubert, “Junction–temperature measurement in GaN ultraviolet light-emitting diodes
using diode forward voltage method”, Applied Physics Letters, Volume 85, Number 12, 2163-2165 (2004)
5
    http://www.heptagon.fi/downloads/Heptagon%201031%20flash%20module%20for%20Luxeon%20LXCL-
PWF1%20v2%204%20A4.pdf




                                                                                                     10