Lecture 6 Edge-triggered Flip-Flop, State Table, State Diagram - PowerPoint

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					        Lecture 6:
 Edge-triggered Flip-Flop,
State Table, State Diagram
       Soon Tee Teoh
          CS 147
          Edge-triggered Flip-Flop
• Contrast to Pulse-triggered SR Flip-Flop
    – Pulse-triggered: Read input while clock is 1, change output when the
      clock goes to 0. What happens during the entire HIGH part of clock can
      affect eventual output.
• Edge-triggered: Read input only on edge of clock cycle (positive or
  negative)
    – Example below: Positive Edge-Triggered D Flip-Flop (Fig 6-13, pg. 253)
         • On the positive edge (while the clock is going from 0 to 1), the input D is
           read, and almost immediately propagated to the output Q. Only the value of
           D at the positive edge matters.

  D                                                                               Q
                         D                                   S

                                                             C
                         C                                                        Q
 Clock                                                       R
                          Symbol
• Symbol of edge-triggered D flip-flop



             D                       D


             C                       C


     Positive-edge triggered   Negative-edge triggered
               Flip-Flop Timing
• Set-up time: ts
   – Input needs to be stable before trigger
• Hold time: th
   – Input needs to be stable after trigger
• Propagation delay: tp
   – Some delay from trigger to output change
• Example: Negative edge triggered flip-flip

 Clock


                            ts th

                                tp
    Sequential Circuit Description
•   Input Equations
•   State Table
•   State Diagram
•   We’ll use the following example
    Sequential Circuit Description
X                                            A
                                   D


                                   C         A




                                   D         B


                                   C         B

                         Clock
                                             Y

                From Figure 6-17, page 259
        Sequential Circuit Description
                              Next state    Present state


  X                                                            A
                                        D


input                                   C                     A




                                        D                     B


                                        C                     B

                          Clock

                                                              Y
                      At the clock trigger, the next state
                      will be read and transferred to the
                                                             output
                      present state
              Input Equations


Anext = ApresentX + BpresentX
                                Next state in terms of
                                input and present state
Bnext = A’presentX
                                Output in terms of input
Y = (Apresent + Bpresent)X’     and present state
                State Table

Present State    Input   Next State   Output

A     B          X       A     B      Y

0      0         0       0      0     0
0      0         1       0      1     0
0      1         0       0      0     1
0      1         1       1      1     0
1      0         0       0      0     1
1      0         1       1      0     0
1      1         0       0      0     1
1      1         1       1      0     0
State Diagram
             1/0
0/0



        00         01

             0/1
  0/1               1/0
             0/1


        10         11
             1/0


1/0
     Mealy and Moore Models

• Preceding Example: Output depends on
  present state and input. This is called the
  Mealy Model
• Another kind of circuit: Output only
  depends on present state. This is called
  the Moore Model
            Example of Moore Model
X
                                            A
Y                                  D                   Z


                                   C                       Anext = Apresent + XY

                                                           Z = Apresent
                         Clock


    X   Y   Apresent Anext

    0   0   0        0                            11
                                 00,01,10
    0   0   1        1
    0   1   0        0
    0   1   1        1
    1   0   0        0
                                            0/0                  1/1
    1   0   1        1
    1   1   0        1
    1   1   1        1                                                    00,01,10,11
                         Moore Model



                                       Some
Inputs   Some                          Combinational
         Combinational                 Circuit
         Circuit                                       Outputs




                          Flip-flops
                         Mealy Model



                                       Some
Inputs   Some                          Combinational
         Combinational                 Circuit
         Circuit                                       Outputs




                          Flip-flops
                Mealy and Moore Model
                   State Diagrams
                                                                   1/0
                                          0/0



                                                      00                     01
    Moore                             input
                                                                   0/1
                                                0/1                              1/0
      input                                                    0/1
                                       output
                          11                          10                     11
00,01,10                                                           1/0


                                              1/0
               0/0             1/1                         state
                                                                         Mealy
           state output              00,01,10,11
How to Design a Sequential Circuit
•   1. Specification
•   2. Formulation: Draw a state diagram
•   3. Assign state number for each state
•   4. Draw state table
•   5. Derive input equations
•   5. One D flip-flop for each state bit
                         Example
• Design a sequential circuit to recognize
  the input sequence 1101.
• That is, output 1 if the sequence 1101 has
  been read, output 0 otherwise.
   0/0                              1/0


             1/0             1/0          0/0
         A               B          C           D

                   0/0        1/1



                             0/0
               Assign States
• 4 states, so we need 2 bits

    0/0                                1/0


               1/0              1/0          0/0
          00               01          10          11

                     0/0         1/1



                                0/0
      Draw State Table

Present State   Input   Next State   Output

A     B         X       A     B      Y

0      0        0       0      0     0
0      0        1       0      1     0
0      1        0       0      0     0
0      1        1       1      0     0
1      0        0       1      1     0
1      0        1       1      0     0
1      1        0       0      0     0
1      1        1       0      1     1
Derive Input Equations


    Anext = A’BX + AB’

    Bnext = A’B’X + AB’X’ + ABX

    Y = ABX
           Draw Circuit
X                                      A
                                   D


                                   C   A




    Exercise:                      D   B
    Fill in the input to
    Flip-Flop B
                                   C   B
                           Clock

                                       Y