RISC FPGA by accinent

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									                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


       5       XSA-50 Board with Spartan-II FPGA
       Components of the XSA-50 board:
       Ø XC2S50 –5 tq144 Spartan2 FPGA                       50k logic gates, 768 slices, 144-Pins, 32kbit Block-RAM
       Ø XC9572XL CPLD                                       serves for I/O interfacing for downloading via parallel port
       Ø Programmable oscillator                             divider 1 – 2052, generates frequencies between 100MHz and
                                                             48.7kHz
       Ø    8M x 16 Synchronous DRAM                         requires interface design emulating SRAM, fosc> 25MHz!
       Ø    256 kByte Flash-RAM                              might be used as a boot-ROM for the volatile FPGA-memory
       Ø    One 7-Segment LED                                is recommended to be used for check of proper download
       Ø    4 DIP switches, push button                      a high level is provided by the push button if not pressed
       Ø    PS2- and VGA-ports
       Ø    Parallel port interface                          the interface connects to the XC9572XL CPLD only

       The CPLD can be directly configured using GXSLOAD with the parallel port. The JTAG configuration
       clock is generated in the PC-host. With a first step the CPLD must be loaded with a special CPLD configura-
       tion file: dwnldpar.svf . File is provided by the C:/XSTOOLs/XSA directory.




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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


                                                        XSA-50 Programmers Model




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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


              Properties of Standard CPLD
              Configuration (dwnldpar.svf)
       After configuring the FPGA, the CPLD is
       transparent for the parallel port data pins
       (marked in green input to FPGA).
       Therefore the FPGA should never drive
       those pins as long as dwnldpar.svf is loaded
       in the CPLD!
       During FPGA-download the CPLD acti-
       vates the decimal-point of the LED (FPGA-
       pin 44). This pin should also be never driven
       from the FPGA!
       After configuring the FPGA, the CPLD is
       also transparent for the status lines (marked
       in red).
       After configuring the FPGA the CPLD is
       transparent for the oscillator clock (FPGA-
       Pin 88).


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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


       5.1     Block-RAM in Spartan-II FPGA Devices
              · Spartan-II FPGAs incorporate several large block RAM memories. These complement the distrib-
                uted RAM Look-Up Tables (LUTs) that provide memory structures implemented in CLBs.




              · Block RAM memory blocks are organized in columns. All Spartan-II devices contain two such col-
                umns, one along each vertical edge. These columns extend the full height of the chip. Each memory
                block is four CLBs high, and consequently, a Spartan XC2S50 device 16 CLBs high will contain four
                memory blocks per column, and a total of eight blocks.



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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                            Hamburg University of Applied Sciences

       · There are four Delay-Locked Loops
         (DLLs), one at each corner of the die.
          These circuits provide zero propagation de-
          lay, low clock skew between output clock
          signals distributed throughout the device,
          and advanced clock domain control.

       · The DLL can provide multiple phases of
         the source clock. The DLL can also act as a
         clock doubler or it can divide the user
         source clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16.




                                                                      Basisc Spartan-II family block diagram (XC2S15).


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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


       Block RAM Features of Spartan-II Devices

       · The Spartan-II FPGAs provide blocks of on-chip,
         true dual-read/write port synchronous RAM, with
         4096 memory cells. Each port of the block RAM
         memory can be independently configured as a
         read/write port, a read port, a write port, and can
         be configured to a specific
          data width.

       · Block RAM memory supports two operating
         modes.
          Ø Read Through:                                                                  Single-port block RAM
          The read address is registered on the read port
          clock edge and data appears on the output after the RAM access time.
          Ø Write Back: The write address is registered on the write port clock edge and the data input is written
            to the memory and mirrored on the write port input.



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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences

       Block RAM Characteristics:
       1. All inputs are registered with the port clock and have a setup to clock timing specification.

       2. All outputs have a read through or write back function depending on the state of the port WE pin.
          The outputs relative to the port clock are available after the clock-to-out timing specification.

       3. The block RAM are true SRAM memories and do not have a combinatorial path from the address to the
          output. The LUT cells in the CLBs are still available with this function.

       4. The ports are completely independent from each other (i.e., clocking, control, address, read/write
          function, and data width) without arbitration.

       5. Write and read operations require only one clock edge.

          · Single-port Block RAM timing:
       Ø At the first rising edge of the CLK pin, the ADDR, DI, EN, WE, and RST pins are sampled. The EN pin is
        High and the WE pin is Low indicating a read operation. The DO bus contains the contents of the memory
        location 00Hex, as indicated by the ADDR bus.



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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences




                       Timing diagram for single-port block RAM memory

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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


          Ø At the second rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again.
           The EN and WE pins are High indicating a write operation. The DO bus mirrors the DI bus. The DI
           bus value CCCCHex is written to the memory location 0FHex.
          Ø At the third rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The
           EN pin is High and the WE pin is Low indicating a read operation. The DO bus contains the contents of
           the memory location 7EHex as indicated by the ADDR bus.
          Ø At the fourth rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again.
           The EN pin is Low indicating that the block RAM memory is now disabled. The DO bus retains the last
           value.




                                                                     RISC Project                                                 5-9

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                                                                                              Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                                           Hamburg University of Applied Sciences



       5.2  Block Memory Generation
       The CoreGen program generates memory structures using the block RAM features. This program outputs
       VHDL simulation code templates and an EDIF file for inclusion in a design.

                                                     <M-N>.EDN                                                                      <T-E-N>.bit
                                                       Netlist                                                                       progr. file
                                                                                                                      Implemen-
                                                                                                    XST                 tation
                                                                                                   VHDL                Place &             MTI
                                                   Top Entity                                     Synthesis             Route             Timing
                             Xilinx     <M-N>.VHO             <T-E-N>.VHD
          <M-N>.COE                                  with                                                                               Simulation
                             CORE        Template              Top Entity
         Coefficient file                         Components
                            Generator                                                  MTI           <T-E-N>.NGC
                                                   <M-N>.VHD                        Behavioural   Native generic circuit                <T-E-Ntimesim>.VHD
                                                   Wrapper file                     Simulation                                          HW behavioural model
                                                                                                             <T-E-Ntimesim>.SDF
                                                   <M-N>.MIF                                               Standard delay format file
                                                  Memory init. file



          · ModuleXilinxCoreLib with MTI Generator processing steps:
                   generation        Core     Library
                              *.VHD            Compilation        xilinx_lib_comp
       1. Start ® Programs ® Xilinx ISE 4.2 ® Accessories ® Core Generator flow with CoreGen modules.
                      has to be processed once               FPGA design System


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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences

          Xilinx CORE Generator and Getting Started window opened
       1. Getting Started window
           ® Create a New Project ® New Project window opened, browse and select
           Directory: C:\ISE_Work\<project_name>                   Has to be the same location for all ISE project input files and
                                                                   implementation output files.
           Options:
           Output Options:       Flow Vendor
           Design Entry:         VHDL         ISE
           Target Architecture:  Spartan2
           Overwrite Files:      False
            ® OK ® Xilinx CORE Generator window will be filled with current selections
                 Current Project: C:\ISE_Work\<project_name>
                 View Catalog:    by Function
                 Target Family: Spartan2

       2. Xilinx CORE Generator window, select in catalog with functions
           ® Memories & Storage Elements ® RAMs & ROMs
            In “Contents of:” all available memory modules for Spartan2 will be listed in black.
           ® Single Port Block Memory® Main parameterisation window will be opened

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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences

       3. Single Port Block Memory assign component name and select parameters
           Component Name:        DAT_MEM_16_256 i.e. for data memory: samples, constants and coefficients
           Port Configuration:    Read and Write
           Memory Size            Width: 16            Depth: 256
           Write Mode:            Read After Write     is fixed for Spartan2 devices
           Initial Contents
           Global Init Value:     0Hex
           Load Init File         select
           <Init_file>.coe        type name of prepared memory initialisation file in small letters
           ® Load file ® Select coe file browse for file which has to be edited in advance
           ® Design Options ® Pipelining and additional control signals can be chosen
           Design Options
           Optional Pins:         no enable pin selected, because data bus will be driven by tristate drivers
           Register Inputs:       no additional register, input data are taken from Codec interface register
           Output Register Options
           Additional Output Pipe Stages: 0 and no SINIT synchronous reset pin for output register
           Implementation Options        no Limit Data Width
            ® OK        Information panel gives address width, number of used blocks and read pipeline latency
            ® Generate five files *.vho, *.vhd, * .mif, *.edn and *.xco are created for implementation and
                              behavioural simulation
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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences


          · Specifying Memory Contents
              The initial contents of the memory can be assigned by specifying the desired information in a separate
              text file called a *.coe-file. An example of a *.coe-file for a 3 by 16 RAM is shown

              MEMORY_INITIALIZATION_RADIX=16;
              MEMORY_INITIALIZATION_VECTOR= fec0, d456, aaaa;


              The MEMORY_INITIALIZATION_VECTOR takes the form of a sequence of comma-separated val-
              ues, one value per memory location, terminated by a semicolon. Any amount of white space, including
              new lines, can be included in the vector. The format of an individual value in the vector will depend on
              the MEMORY_INITIALIZATION_RADIX value.

          · Explanation of generated output files
                  Ø A VHDL template for component declaration and instantiation is given by the *.vho file.
                  Ø The wrapper file *.vhd will be used for behavioural simulation and therefore has to be compiled
                   together with the top entity and all other components in a correct order. This file calls and pa-
                   rameterises the behavioural models which are located in a xilinx_lib_comp library which con-
                   tains compiled VHDL modules from XilinxCoreLib library.

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                                                                                    Hochschule für Angewandte Wissenschaften Hamburg
       Prof. Dr. B. Schwarz
                                                                                                         Hamburg University of Applied Sciences

                  Ø The *.mif file supports behavioural simulation with memory initialisation values.
                  Ø Implementation uses the *.edn netlist file which contains the synthesis result.
                  Ø All parameters of the CoreGen module generation process are listed in the *.xco file.




                                                                     RISC Project                                                 5-14

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