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µPILRâ„¢Stacked Packaging Thermal Analysis by alq49994

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									µPILR™ Stacked Packaging
Thermal Analysis
    Outline


     Objective:
     Evaluate thermal characteristics of µPILR™ in a stacked package, using
     DDR2 memory chips on a VLP (Very Low Profile) DIMM substrate


    Outline:
     DIMM substrate
     Flotherm model of stacked package using MicroContact
     Thermal resistance from junction to ambient
     Air cooling of 4 memory modules
     Summary
     Conclusions



2
    µPILR™ Package Stack




                                      Pins


           µPILR™ 4-Stack DDR2 DRAM




3
    VLP (Very Low Profile) DIMM Board



                                                      133 x 18.3 x 1.27 mm


                                                  trace layer




                                                                Dielectric
                                                                (FR4)


    layer         1      2     3      4      5          6
    Thickness
                 17.5   35    17.5   17.5   35        17.5
    (micron)
    Cu content   20%    90%   50%    50%    90%       20%

4
    DRAM Package




            Package Dimensions              µPILR™ Dimensions

    Component      x y (mm)      z (mm)
    Die            9.7 x 8.35    0.15     Post top      80 micron
                                          diameter
    Die attach     9.7 x 8.35    0.02
                                          Post base     180 micron
    polyimide      12.8 x 9.8    0.013    diameter
    trace          12.8 x 9.8    0.012    Post height   125 micron


5
    DRAM 4 Stack


                                                                                K
                                                   Component     Material
                                                                             (W/m.K)

                                                   Die           Silicon       117.5

                                                   Tape          Polyimide      0.2


                                               3   Elastomer     Silicone    192.6(x,y)
                                                   /Trace        /Cu           0.4(z)
                                               2
                                               1
                                                   Pin           Cu             390
                                               0
                                                                 Eutectic
                                                   Solder ball                  50
                                                                 Sn/Pb
                                                   Board
                                                                 FR4            0.3
                                                   dielectric
     Die no. Power (W)
                                                   Traces        copper         390
       0        0.1
                         Worst case: active
       1        0.1      device on top stack
       2        0.1      Total power per stack =
       3        0.7      1.0 W

6
    µPILR™ 4 Stack on DIMM




     • Natural convection, Tamb = 20 oC
     • Rth(j-a) = 32.6oC/W,
     • Temperature is nearly uniform within the package stack, ΔT < 5 oC from die to die
     • R(j-b) < 7 oC/W, R(pcb-a) is the main component
     • Heat is conducted horizontally from the die to the µPILR™ pins, then from the pins
     down to the PCB.
7
    Thermal Resistance

                        4 stack**   4 stack*   2 stack*   1 layer*

           Rth (oC/W)      32.6       27.5       29.5        30.8



     * power evenly distributed between dies
     ** top die being active

        Rth defined with maximum die temperature
        Natural Convection
               µPILR™ thermal advantage:

               • High conductivity
               • Shorter length
               • Higher density

8
    Full R-DIMM Simulation Server Environment




      4 Stack x 18 sites = 72 DRAMs, with Cu heat spreader


       • 4 DIMMs in parallel, 0.5 inch apart (worst case server environment)
       • 1 DIMM active, 3 stand by
       • Active P = 20W (with register and PLL), standby P = 5W
       • Average P = 8.75W


9
     Forced Convection with 500 LFM
        DIMM with MicroContact                          Regular DIMM
        (height < 4 mm)                                 (height~6mm)
     Air flow speed                            Air flow speed




     Temperature
                                             Temperature




     Boundary layer growth between the DIMMs reduces air flow on the surface
      µPILR™ makes each DIMM thinner, which increases space for air flow, and
      improve air cooling efficiency 17 oC cooler than regular DIMM
10
     Thermal Analysis Summary


   Thermal performance of stacked memory, using µPILR™ package, on VLP DIMM
 substrate is analyzed with Flotherm v6.1
   With worst case thermal regime (active die on top), thermal resistance for 4 stack µPILR™
 is approximately 32 oC/W.
  With even power distribution between layers, thermal resistance for single layer, 2 stack
 and 4 stack are 31 oC/W, 30 oC/W, and 28 oC/W, respectively.
     Compared to other interconnect, µPILR™ stacked package has benefits of:
        –   Higher thermal conductivity
        –   Shorter heat transfer path
        –   Higher pin count, (benefits heat transfer)
     These benefits are partially offset by the reduced cross section area




11
     Conclusions



      At package level the overall thermal performance of the µPILR™
      is about the same as Solder Ball
      When DIMMs are placed in parallel, as in a server application,
      Stacked µPILR™ package performs better because the memory
      module is thinner, and enables more efficient air cooling




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