CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING PROCESS

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					CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS                                             438 - 1



                                                                           30   ..Liquid crystal component
438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



1                                      HAVING BIOMATERIAL COMPONENT OR
                                          INTEGRATED WITH LIVING           31   ..Optical waveguide structure
                                          ORGANISM                         32   ..Optical grating structure
2                                      HAVING SUPERCONDUCTIVE COMPONENT    33   .Substrate dicing
3                                      HAVING MAGNETIC OR FERROELECTRIC    34   .Making emissive array
                                          COMPONENT                        35   ..Multiple wavelength emissive
4                                      REPAIR OR RESTORATION               36   .Ordered or disordered
5                                      INCLUDING CONTROL RESPONSIVE TO     37   .Graded composition
                                          SENSED CONDITION                 38   .Passivating of surface
6                                      .Interconnecting plural devices     39   .Mesa formation
                                          on semiconductor substrate       40   ..Tapered etching
7                                      .Optical characteristic sensed      41   ..With epitaxial deposition of
8                                      ..Chemical etching                          semiconductor adjacent mesa
9                                      ...Plasma etching                   42   .Groove formation
10                                     .Electrical characteristic sensed   43   ..Tapered etching
11                                     ..Utilizing integral test element   44   ..With epitaxial deposition of
12                                     ..And removal of defect                     semiconductor in groove
13                                     ..Altering electrical property by   45   .Dopant introduction into
                                          material removal                         semiconductor region
14                                     WITH MEASURING OR TESTING           46   .Compound semiconductor
15                                     .Packaging (e.g., with mounting,    47   ..Heterojunction
                                          encapsulating, etc.) or          48   MAKING DEVICE OR CIRCUIT
                                          treatment of packaged                    RESPONSIVE TO NONELECTRICAL
                                          semiconductor                            SIGNAL
16                                     .Optical characteristic sensed      49   .Chemically responsive
17                                     .Electrical characteristic sensed   50   .Physical stress responsive
18                                     ..Utilizing integral test element   51   ..Packaging (e.g., with mounting,
19                                     HAVING INTEGRAL POWER SOURCE                encapsulating, etc.) or
                                          (E.G., BATTERY, ETC.)                    treatment of packaged
20                                     ELECTRON EMITTER MANUFACTURE                semiconductor
21                                     MANUFACTURE OF ELECTRICAL DEVICE    52   ..Having cantilever element
                                          CONTROLLED PRINTHEAD             53   ..Having diaphragm element
22                                     MAKING DEVICE OR CIRCUIT EMISSIVE   54   .Thermally responsive
                                          OF NONELECTRICAL SIGNAL          55   ..Packaging (e.g., with mounting,
23                                     .Having diverse electrical device           encapsulating, etc.) or
24                                     ..Including device responsive to            treatment of packaged
                                          nonelectrical signal                     semiconductor
25                                     ...Packaging (e.g., with            56   .Responsive to corpuscular
                                          mounting, encapsulating, etc.)           radiation (e.g., nuclear
                                          or treatment of packaged                 particle detector, etc.)
                                          semiconductor                    57   .Responsive to electromagnetic
26                                     .Packaging (e.g., with mounting,            radiation
                                          encapsulating, etc.) or          58   ..Gettering of substrate
                                          treatment of packaged            59   ..Having diverse electrical
                                          semiconductor                            device
27                                     ..Having additional optical         60   ...Charge transfer device (e.g.,
                                          element (e.g., optical fiber,            CCD, etc.)
                                          etc.)                            61   ..Continuous processing
28                                     ..Plural emissive devices           62   ...Using running length substrate
29                                     .Including integrally formed        63   ..Particulate semiconductor
                                          optical element (e.g.,                   component
                                          reflective layer, luminescent
                                          material, contoured surface,
                                          etc.)



                                                                                                     January 2009
438 - 2           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



64        ..Packaging (e.g., with mounting,   88    ..Direct application of electric
             encapsulating, etc.) or                   current
             treatment of packaged            89    ..Fusion or solidification of
             semiconductor                             semiconductor region
65        ...Having additional optical        90    ..Including storage of electrical
             element (e.g., optical fiber,             charge in substrate
             etc.)                            91    ..Avalanche diode
66        ...Plural responsive devices        92    ..Schottky barrier junction
             (e.g., array, etc.)              93    ..Compound semiconductor
67        ....Assembly of plural              94    ...Heterojunction
             semiconductor substrates         95    ...Chalcogen (i.e., oxygen (O),
68        ..Substrate dicing                           sulfur (S), selenium (Se),
69        ..Including integrally formed                tellurium (Te)) containing
             optical element (e.g.,           96    ..Amorphous semiconductor
             reflective layer, luminescent    97    ..Polycrystalline semiconductor
             layer, etc.)                     98    ..Contact formation (i.e.,
70        ...Color filter                              metallization)
71        ...Specific surface topography      99    HAVING ORGANIC SEMICONDUCTIVE
             (e.g., textured surface, etc.)            COMPONENT
72        ...Having reflective or             100   MAKING POINT CONTACT DEVICE
             antireflective component         101   .Direct application of electrical
73        ..Making electromagnetic                     current
             responsive array                 102   HAVING SELENIUM OR TELLURIUM
74        ...Vertically arranged (e.g.,                ELEMENTAL SEMICONDUCTOR
             tandem, stacked, etc.)                    COMPONENT
75        ...Charge transfer device (e.g.,    103   .Direct application of electrical
             CCD, etc.)                                current
76        ....Majority signal carrier         104   HAVING METAL OXIDE OR COPPER
             (e.g., buried or bulk channel,            SULFIDE COMPOUND SEMICONDUCTOR
             peristaltic, etc.)                        COMPONENT
77        ....Compound semiconductor          105   HAVING DIAMOND SEMICONDUCTOR
78        ....Having structure to improve              COMPONENT
             output signal (e.g., exposure    106   PACKAGING (E.G., WITH MOUNTING,
             control structure, etc.)                  ENCAPSULATING, ETC.) OR
79        .....Having blooming suppression             TREATMENT OF PACKAGED
             structure (e.g., antiblooming             SEMICONDUCTOR
             drain, etc.)                     107   .Assembly of plural
80        ...Lateral series connected array            semiconductive substrates each
81        ....Specified shape junction                 possessing electrical device
             barrier (e.g., V-grooved         108   ..Flip-chip-type assembly
             junction, etc.)                  109   ..Stacked array (e.g., rectifier,
82        ..Having organic semiconductor               etc.)
             component                        110   .Making plural separate devices
83        ..Forming point contact             111   ..Using strip lead frame
84        ..Having selenium or tellurium      112   ...And encapsulating
             elemental semiconductor          113   ..Substrate dicing
             component                        114   ...Utilizing a coating to perfect
85        ..Having metal oxide or copper               the dicing
             sulfide compound                 115   .Including contaminant removal or
             semiconductive component                  mitigation
86        ...And cadmium sulfide compound     116   .Having light transmissive window
             semiconductive component         117   .Incorporating resilient
87        ..Graded composition                         component (e.g., spring, etc.)
                                              118   .Including adhesive bonding step



January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS               438 - 3



119    ..Electrically conductive           146   ..Majority signal carrier (e.g.,
          adhesive                                  buried or bulk channel,
120    .With vibration step                         peristaltic, etc.)
121    .Metallic housing or support        147   ..Changing width or direction of
122    ..Possessing thermal dissipation             channel (e.g., meandering
          structure (i.e., heat sink)               channel, etc.)
123    ..Lead frame                        148   ..Substantially incomplete signal
124    ..And encapsulating                          charge transfer (e.g., bucket
125    .Insulative housing or support               brigade, etc.)
126    ..And encapsulating                 149   .On insulating substrate or layer
127    .Encapsulating                               (e.g., TFT, etc.)
128    MAKING DEVICE ARRAY AND             150   ..Specified crystallographic
          SELECTIVELY INTERCONNECTING               orientation
129    .With electrical circuit layout     151   ..Having insulated gate
130    .Rendering selected devices         152   ...Combined with electrical
          operable or inoperable                    device not on insulating
131    .Using structure alterable to                substrate or layer
          conductive state (i.e.,          153   ....Complementary field effect
          antifuse)                                 transistors
132    .Using structure alterable to       154   ...Complementary field effect
          nonconductive state (i.e.,                transistors
          fuse)                            155   ...And additional electrical
133    MAKING REGENERATIVE-TYPE                     device on insulating substrate
          SWITCHING DEVICE (E.G., SCR,              or layer
          IGBT, THYRISTOR, ETC.)           156   ...Vertical channel
134    .Bidirectional rectifier with       157   ...Plural gate electrodes (e.g.,
          control electrode (e.g.,                  dual gate, etc.)
          triac, diac, etc.)               158   ...Inverted transistor structure
135    .Having field effect structure      159   ....Source-to-gate or drain-to-
136    ..Junction gate                              gate overlap
137    ...Vertical channel                 160   ....Utilizing backside
138    ..Vertical channel                           irradiation
139    .Altering electrical                161   ...Including source or drain
          characteristic                            electrode formation prior to
140    .Having structure increasing                 semiconductor layer formation
          breakdown voltage (e.g., guard            (i.e., staggered electrodes)
          ring, field plate, etc.)         162   ...Introduction of nondopant into
141    MAKING CONDUCTIVITY MODULATION               semiconductor layer
          DEVICE (E.G., UNIJUNCTION        163   ...Adjusting channel dimension
          TRANSISTOR, DOUBLE BASE DIODE,            (e.g., providing lightly doped
          CONDUCTIVITY-MODULATED                    source or drain region, etc.)
          TRANSISTOR, ETC.)                164   ...Semiconductor islands formed
142    MAKING FIELD EFFECT DEVICE HAVING            upon insulating substrate or
          PAIR OF ACTIVE REGIONS                    layer (e.g., mesa formation,
          SEPARATED BY GATE STRUCTURE BY            etc.)
          FORMATION OR ALTERATION OF       165   ....Including differential
          SEMICONDUCTIVE ACTIVE REGIONS             oxidation
143    .Gettering of semiconductor         166   ...Including recrystallization
          substrate                                 step
144    .Charge transfer device (e.g.,      167   .Having Schottky gate (e.g.,
          CCD, etc.)                                MESFET, HEMT, etc.)
145    ..Having additional electrical      168   ..Specified crystallographic
          device                                    orientation
                                           169   ..Complementary Schottky gate
                                                    field effect transistors


                                                                       January 2009
438 - 4           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



170       ..And bipolar device               201   ....Including insulated gate
171       ..And passive electrical device             field effect transistor having
             (e.g., resistor, capacitor,              gate surrounded by dielectric
             etc.)                                    (i.e., floating gate)
172       ..Having heterojunction (e.g.,     202   ....Including bipolar transistor
             HEMT, MODFET, etc.)                      (i.e., BiCMOS)
173       ..Vertical channel                 203   .....Complementary bipolar
174       ..Doping of semiconductive                  transistors
             channel region beneath gate     204   .....Lateral bipolar transistor
             (e.g., threshold voltage        205   .....Plural bipolar transistors
             adjustment, etc.)                        of differing electrical
175       ..Buried channel                            characteristics
176       ..Plural gate electrodes (e.g.,    206   .....Vertical channel insulated
             dual gate, etc.)                         gate field effect transistor
177       ..Closed or loop gate              207   .....Including isolation
178       ..Elemental semiconductor                   structure
179       ..Asymmetric                       208   ......Isolation by PN junction
180       ..Self-aligned                              only
181       ...Doping of semiconductive        209   ....Including additional vertical
             region                                   channel insulated gate field
182       ....T-gate                                  effect transistor
183       ....Dummy gate                     210   ....Including passive device
184       ....Utilizing gate sidewall                 (e.g., resistor, capacitor,
             structure                                etc.)
185       .....Multiple doping steps         211   ...Having gate surrounded by
186       .Having junction gate (e.g.,                dielectric (i.e., floating
             JFET, SIT, etc.)                         gate)
187       ..Specified crystallographic       212   ...Vertical channel
             orientation                     213   ...Common active region
188       ..Complementary junction gate      214   ...Having underpass or crossunder
             field effect transistors        215   ...Having fuse or integral short
189       ..And bipolar transistor           216   ...Gate insulator structure
190       ..And passive device (e.g.,                 constructed of diverse
             resistor, capacitor, etc.)               dielectrics (e.g., MNOS, etc.)
191       ..Having heterojunction                     or of nonsilicon compound
192       ..Vertical channel                 217   ...Doping of semiconductor
193       ...Multiple parallel current                channel region beneath gate
             paths (e.g., grid gate, etc.)            insulator (e.g., threshold
                                                      voltage adjustment, etc.)
194       ..Doping of semiconductive
             channel region beneath gate
                                             218   ...Including isolation structure
             (e.g., threshold voltage        219   ....Total dielectric isolation
             adjustment, etc.)               220   ....Isolation by PN junction only
195       ..Plural gate electrodes           221   ....Dielectric isolation formed
196       ..Including isolation structure             by grooving and refilling with
197       .Having insulated gate (e.g.,               dielectric material
             IGFET, MISFET, MOSFET, etc.)    222   .....With epitaxial semiconductor
198       ..Specified crystallographic                layer formation
             orientation                     223   .....Having well structure of
199       ..Complementary insulated gate              opposite conductivity type
             field effect transistors        224   ......Plural wells
             (i.e., CMOS)                    225   ....Recessed oxide formed by
200       ...And additional electrical                localized oxidation (i.e.,
             device                                   LOCOS)
                                             226   .....With epitaxial semiconductor
                                                      layer formation


January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS               438 - 5



227    .....Having well structure of       257   ..Having additional gate
          opposite conductivity type                electrode surrounded by
228    ......Plural wells                           dielectric (i.e., floating
229    ...Self-aligned                              gate)
230    ....Utilizing gate sidewall         258   ...Including additional field
          structure                                 effect transistor (e.g., sense
231    .....Plural doping steps                     or access transistor, etc.)
232    ....Plural doping steps             259   ...Including forming gate
233    ...And contact formation                     electrode in trench or recess
234    ..Including bipolar transistor               in substrate
          (i.e., BiMOS)                    260   ...Textured surface of gate
235    ...Heterojunction bipolar                    insulator or gate electrode
          transistor                       261   ...Multiple interelectrode
236    ...Lateral bipolar transistor                dielectrics or nonsilicon
237    ..Including diode                            compound gate insulator
238    ..Including passive device (e.g.,   262   ...Including elongated source or
          resistor, capacitor, etc.)                drain region disposed under
239    ...Capacitor                                 thick oxide regions (e.g.,
                                                    buried or diffused bitline,
240    ....Having high dielectric
                                                    etc.)
          constant insulator (e.g.,
          Ta2O5, etc.)
                                           263   ....Tunneling insulator
241    ....And additional field effect
                                           264   ...Tunneling insulator
          transistor (e.g., sense or       265   ...Oxidizing sidewall of gate
          access transistor, etc.)                  electrode
242    .....Including transistor formed    266   ...Having additional, nonmemory
          on trench sidewalls                       control electrode or channel
                                                    portion (e.g., for accessing
243    ....Trench capacitor
                                                    field effect transistor
244    .....Utilizing stacked capacitor
                                                    structure, etc.)
          structure (e.g., stacked
                                           267   ....Including forming gate
          trench, buried stacked
                                                    electrode as conductive
          capacitor, etc.)
                                                    sidewall spacer to another
245    .....With epitaxial layer formed
                                                    electrode
          over the trench
                                           268   ..Vertical channel
246    .....Including doping of trench
                                           269   ...Utilizing epitaxial
          surfaces
                                                    semiconductor layer grown
247    ......Multiple doping steps
                                                    through an opening in an
248    ......Including isolation means
                                                    insulating layer
          formed in trench
                                           270   ...Gate electrode in trench or
249    ......Doping by outdiffusion from
                                                    recess in semiconductor
          a dopant source layer (e.g.,              substrate
          doped oxide, etc.)
                                           271   ....V-gate
250    ....Planar capacitor
                                           272   ....Totally embedded in
251    .....Including doping of
                                                    semiconductive layers
          semiconductive region
                                           273   ...Having integral short of
252    ......Multiple doping steps
                                                    source and base regions
253    ....Stacked capacitor
                                           274   ....Short formed in recess in
254    .....Including selectively                   substrate
          removing material to undercut
                                           275   ..Making plural insulated gate
          and expose storage node layer
                                                    field effect transistors of
255    .....Including texturizing                   differing electrical
          storage node layer                        characteristics
256    .....Contacts formed by selective   276   ...Introducing a dopant into the
          growth or deposition                      channel region of selected
                                                    transistors



                                                                       January 2009
438 - 6           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



277       ....Including forming overlapping   302   ....Oblique implantation
             gate electrodes                  303   ....Utilizing gate sidewall
278       ....After formation of source or             structure
             drain regions and gate           304   .....Conductive sidewall
             electrode (e.g., late                     component
             programming, encoding, etc.)     305   .....Plural doping steps
279       ..Making plural insulated gate      306   ....Plural doping steps
             field effect transistors         307   .....Using same conductivity-type
             having common active region               dopant
280       ..Having underpass or crossunder    308   ..Radiation or energy treatment
281       ..Having fuse or integral short              modifying properties of
282       ..Buried channel                             semiconductor regions of
283       ..Plural gate electrodes (e.g.,              substrate (e.g., thermal,
             dual gate, etc.)                          corpuscular, electromagnetic,
284       ..Closed or loop gate                        etc.)
285       ..Utilizing compound                309   FORMING BIPOLAR TRANSISTOR BY
             semiconductor                             FORMATION OR ALTERATION OF
286       ..Asymmetric                                 SEMICONDUCTIVE ACTIVE REGIONS
287       ..Gate insulator structure          310   .Gettering of semiconductor
             constructed of diverse                    substrate
             dielectrics (e.g., MNOS, etc.)   311   .On insulating substrate or layer
             or of nonsilicon compound                 (i.e., SOI type)
288       ..Having step of storing            312   .Having heterojunction
             electrical charge in gate        313   ..Complementary bipolar
             dielectric                                transistors
289       ..Doping of semiconductive          314   ..And additional electrical
             channel region beneath gate               device
             insulator (e.g., adjusting       315   ..Forming inverted transistor
             threshold voltage, etc.)                  structure
290       ...After formation of source or     316   ..Forming lateral transistor
             drain regions and gate                    structure
             electrode                        317   ..Wide bandgap emitter
291       ...Using channel conductivity       318   ..Including isolation structure
             dopant of opposite type as       319   ...Air isolation (e.g., mesa,
             that of source and drain                  etc.)
292       ..Direct application of             320   ..Self-aligned
             electrical current               321   ...Utilizing dummy emitter
293       ..Fusion or solidification of       322   .Complementary bipolar
             semiconductor region                      transistors
294       ..Including isolation structure     323   ..Having common active region
295       ...Total dielectric isolation                (i.e., integrated injection
296       ...Dielectric isolation formed by            logic (I2L), etc.)
             grooving and refilling with      324   ...Including additional
             dielectric material                       electrical device
297       ...Recessed oxide formed by         325   ...Having lateral bipolar
             localized oxidation (i.e.,                transistor
             LOCOS)                           326   ..Including additional electrical
298       ....Doping region beneath                    device
             recessed oxide (e.g., to form    327   ..Having lateral bipolar
             chanstop, etc.)                           transistor
299       ..Self-aligned                      328   .Including diode
300       ...Having elevated source or        329   .Including passive device (e.g.,
             drain (e.g., epitaxially                  resistor, capacitor, etc.)
             formed source or drain, etc.)    330   ..Resistor
301       ...Source or drain doping



January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS               438 - 7



331    ...Having same doping as emitter    361   ...Including deposition of
          or collector                              polysilicon or noninsulative
332    ...Lightly doped junction                    material into groove
          isolated resistor                362   ..Recessed oxide by localized
333    .Having fuse or integral short               oxidation (i.e., LOCOS)
334    .Forming inverted transistor        363   ...With epitaxial semiconductor
          structure                                 layer formation
335    .Forming lateral transistor         364   .Self-aligned
          structure                        365   ..Forming active region from
336    ..Combined with vertical bipolar             adjacent doped polycrystalline
          transistor                                or amorphous semiconductor
337    ..Active region formed along        366   ...Having sidewall
          groove or exposed edge in        367   ....Including conductive
          semiconductor                             component
338    ..Having multiple emitter or        368   ...Simultaneously outdiffusing
          collector structure                       plural dopants from
339    ..Self-aligned                               polysilicon or amorphous
340    .Making plural bipolar                       semiconductor
          transistors of differing         369   ..Dopant implantation or
          electrical characteristics                diffusion
341    .Using epitaxial lateral            370   ...Forming buried region (e.g.,
          overgrowth                                implanting through insulating
342    .Having multiple emitter or                  layer, etc.)
          collector structure              371   ...Simultaneous introduction of
343    .Mesa or stacked emitter                     plural dopants
344    .Washed emitter                     372   ....Plural doping steps
345    .Walled emitter                     373   .....Multiple ion implantation
346    .Emitter dip prevention or                   steps
          utilization                      374   ......Using same conductivity-
347    .Permeable or metal base                     type dopant
348    .Sidewall base contact              375   .....Forming partially
349    .Pedestal base                               overlapping regions
350    .Forming base region of specified   376   .....Single dopant forming
          dopant concentration profile              regions of different depth or
          (e.g., inactive base region               concentrations
          more heavily doped than active   377   .....Through same mask opening
          base region, etc.)               378   .Radiation or energy treatment
351    .Direct application of electrical            modifying properties of
          current                                   semiconductor regions of
352    .Fusion or solidification of                 substrate (e.g., thermal,
          semiconductor region                      corpuscular, electromagnetic,
353    .Including isolation structure               etc.)
354    ..Having semi-insulative region     379   VOLTAGE VARIABLE CAPACITANCE
355    ..Total dielectrical isolation               DEVICE MANUFACTURE (E.G.,
356    ..Isolation by PN junction only              VARACTOR, ETC.)
357    ...Including epitaxial              380   AVALANCHE DIODE MANUFACTURE
          semiconductor layer formation             (E.G., IMPATT, TRAPPAT, ETC.)
358    ....Up diffusion of dopant from     381   MAKING PASSIVE DEVICE (E.G.,
          substrate into epitaxial layer            RESISTOR, CAPACITOR, ETC.)
359    ..Dielectric isolation formed by    382   .Resistor
          grooving and refilling with      383   ..Lightly doped junction isolated
          dielectrical material                     resistor
360    ...With epitaxial semiconductor     384   ..Deposited thin film resistor
          formation in groove              385   ...Altering resistivity of
                                                    conductor


                                                                       January 2009
438 - 8           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



386       .Trench capacitor                   415   ..Thermomigration
387       ..Having stacked capacitor          416   ..With epitaxial semiconductor
             structure (e.g., stacked                  formation
             trench, buried stacked           417   ...And simultaneous
             capacitor, etc.)                          polycrystalline growth
388       ..With epitaxial layer formed       418   ...Dopant addition
             over the trench                  419   ....Plural doping steps
389       ..Including doping of trench        420   ..Plural doping steps
             surfaces                         421   .Having air-gap dielectric (e.g.,
390       ...Multiple doping steps                     groove, etc.)
391       ...Including isolation means        422   ..Enclosed cavity
             formed in trench                 423   .Implanting to form insulator
392       ...Doping by outdiffusion from a    424   .Grooved and refilled with
             dopant source layer (e.g.,                deposited dielectric material
             doped oxide)                     425   ..Combined with formation of
393       .Planar capacitor                            recessed oxide by localized
394       ..Including doping of                        oxidation
             semiconductive region            426   ...Recessed oxide laterally
395       ...Multiple doping steps                     extending from groove
396       .Stacked capacitor                  427   ..Refilling multiple grooves of
397       ..Including selectively removing             different widths or depths
             material to undercut and         428   ...Reflow of insulator
             expose storage node layer        429   ..And epitaxial semiconductor
398       ..Including texturizing storage              formation in groove
             node layer                       430   ..And deposition of polysilicon
399       ..Having contacts formed by                  or noninsulative material into
             selective growth or deposition            groove
400       FORMATION OF ELECTRICALLY           431   ...Oxidation of deposited
             ISOLATED LATERAL                          material
             SEMICONDUCTIVE STRUCTURE         432   ....Nonoxidized portions
401       .Having substrate registration               remaining in groove after
             feature (e.g., alignment mark)            oxidation
402       .And gettering of substrate         433   ..Dopant addition
403       .Having semi-insulating component   434   ...From doped insulator in groove
404       .Total dielectric isolation         435   ..Multiple insulative layers in
405       ..And separate partially isolated            groove
             semiconductor regions            436   ...Reflow of insulator
406       ..Bonding of plural                 437   ...Conformal insulator formation
             semiconductive substrates        438   ..Reflow of insulator
407       ..Nondopant implantation            439   .Recessed oxide by localized
408       ..With electrolytic treatment                oxidation (i.e., LOCOS)
             step                             440   ..Including nondopant
409       ...Porous semiconductor formation            implantation
410       ..Encroachment of separate          441   ..With electrolytic treatment
             locally oxidized regions                  step
411       ..Air isolation (e.g., beam lead    442   ..With epitaxial semiconductor
             supported semiconductor                   layer formation
             islands, etc.)                   443   ..Etchback of recessed oxide
412       ...Semiconductor islands formed     444   ..Preliminary etching of groove
             upon insulating substrate or     445   ...Masking of groove sidewall
             layer (e.g., mesa isolation,     446   ....Polysilicon containing
             etc.)                                     sidewall
413       ..With epitaxial semiconductor      447   ....Dopant addition
             formation                        448   ..Utilizing oxidation mask having
414       .Isolation by PN junction only               polysilicon component


January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS               438 - 9



449    ..Dopant addition                   480   ..Including implantation of ion
450    ...Implanting through recessed               which reacts with
          oxide                                     semiconductor substrate to
451    ...Plural doping steps                       form insulating layer
452    ..Plural oxidation steps to form    481   ..Utilizing epitaxial lateral
          recessed oxide                            overgrowth
453    ..And electrical conductor          482   .Amorphous semiconductor
          formation (i.e.,                 483   ..Compound semiconductor
          metallization)                   484   ..Running length (e.g., sheet,
454    .Field plate electrode                       strip, etc.)
455    BONDING OF PLURAL SEMICONDUCTOR     485   ..Deposition utilizing plasma
          SUBSTRATES                                (e.g., glow discharge, etc.)
456    .Having enclosed cavity             486   ..And subsequent crystallization
457    .Warping of semiconductor           487   ...Utilizing wave energy (e.g.,
          substrate                                 laser, electron beam, etc.)
458    .Subsequent separation into         488   .Polycrystalline semiconductor
          plural bodies (e.g.,             489   ..Simultaneous single crystal
          delaminating, dicing, etc.)               formation
459    .Thinning of semiconductor          490   ..Running length (e.g., sheet,
          substrate                                 strip, etc.)
460    SEMICONDUCTOR SUBSTRATE DICING      491   ..And subsequent doping of
461    .Beam lead formation                         polycrystalline semiconductor
462    .Having specified scribe region     492   .Fluid growth step with preceding
          structure (e.g., alignment                and subsequent diverse
          mark, plural grooves, etc.)               operation
463    .By electromagnetic irradiation     493   .Plural fluid growth steps with
          (e.g., electron, laser, etc.)             intervening diverse operation
464    .With attachment to temporary       494   ..Differential etching
          support or carrier               495   ..Doping of semiconductor
465    .Having a perfecting coating        496   ..Coating of semiconductive
466    DIRECT APPLICATION OF ELECTRICAL             substrate with
          CURRENT                                   nonsemiconductive material
467    .To alter conductivity of fuse or   497   .Fluid growth from liquid
          antifuse element                          combined with preceding
468    .Electromigration                            diverse operation
469    .Utilizing pulsed current           498   ..Differential etching
470    .Fusion of semiconductor region     499   ..Doping of semiconductor
471    GETTERING OF SUBSTRATE              500   .Fluid growth from liquid
472    .By vibrating or impacting                   combined with subsequent
473    .By implanting or irradiating                diverse operation
474    ..Ionized radiation (e.g.,          501   ..Doping of semiconductor
          corpuscular or plasma            502   ..Heat treatment
          treatment, etc.)                 503   .Fluid growth from gaseous state
475    ...Hydrogen plasma (i.e.,                    combined with preceding
          hydrogenization)                          diverse operation
476    .By layers which are coated,        504   ..Differential etching
          contacted, or diffused           505   ..Doping of semiconductor
477    .By vapor phase surface reaction    506   ...Ion implantation
478    FORMATION OF SEMICONDUCTIVE         507   .Fluid growth from gaseous state
          ACTIVE REGION ON ANY SUBSTRATE            combined with subsequent
          (E.G., FLUID GROWTH,                      diverse operation
          DEPOSITION)                      508   ..Doping of semiconductor
479    .On insulating substrate or layer   509   ..Heat treatment




                                                                       January 2009
438 - 10           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



510        INTRODUCTION OF CONDUCTIVITY        540   ..Including plural controlled
              MODIFYING DOPANT INTO                     heating or cooling steps or
              SEMICONDUCTIVE MATERIAL                   nonuniform heating
511        .Ordering or disordering            541   ...Including diffusion after
512        .Involving nuclear transmutation             fusing step
              doping                           542   .Diffusing a dopant
513        .Plasma (e.g., glow discharge,      543   ..To control carrier lifetime
              etc.)                                     (i.e., deep level dopant)
514        .Ion implantation of dopant into    544   ..To solid-state solubility
              semiconductor region                      concentration
515        ..Ionized molecules                 545   ..Forming partially overlapping
516        ..Including charge neutralization            regions
517        ..Of semiconductor layer on         546   ..Plural dopants in same region
              insulating substrate or layer             (e.g., through same mask
518        ..Of compound semiconductor                  opening, etc.)
519        ...Including multiple               547   ...Simultaneously
              implantation steps               548   ..Plural dopants simultaneously
520        ....Providing nondopant ion                  in plural regions
              (e.g., proton, etc.)             549   ..Single dopant forming plural
521        ....Using same conductivity-type             diverse regions (e.g., forming
              dopant                                    regions of different
522        ...Including heat treatment                  concentrations or of different
523        ...And contact formation (i.e.,              depths, etc.)
              metallization)                   550   ..Nonuniform heating
524        ..Into grooved semiconductor        551   ..Using multiple layered mask
              substrate region                 552   ...Having plural predetermined
525        ..Using oblique beam                         openings in master mask
526        ..Forming buried region             553   ..Using metal mask
527        ..Including multiple implantation   554   ..Outwardly
              steps                            555   ..Laterally under mask opening
528        ...Providing nondopant ion (e.g.,   556   ..Edge diffusion by using edge
              proton, etc.)                             portion of structure other
529        ...Using same conductivity-type              than masking layer to mask
              dopant                           557   ..From melt
530        ..Including heat treatment          558   ..From solid dopant source in
531        ..Using shadow mask                          contact with semiconductor
532        ..Into polycrystalline region                region
533        ..And contact formation (i.e.,      559   ...Using capping layer over
              metallization)                            dopant source to prevent out-
534        ...Rectifying contact (i.e.,                 diffusion of dopant
              Schottky contact)                560   ...Plural diffusion stages
535        .By application of corpuscular or   561   ...Dopant source within trench or
              electromagnetic radiation                 groove
              (e.g., electron, laser, etc.)    562   ...Organic source
536        ..Recoil implantation               563   ...Glassy source or doped oxide
537        .Fusing dopant with substrate       564   ...Polycrystalline semiconductor
              (i.e., alloy junction)                    source
538        ..Using additional material to      565   ..From vapor phase
              improve wettability or flow      566   ...Plural diffusion stages
              characteristics (e.g., flux,     567   ...Solid source in operative
              etc.)                                     relation with semiconductor
539        ..Application of pressure to                 region
              material during fusion           568   ....In capsule-type enclosure
                                               569   ...Into compound semiconductor
                                                        region


January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS              438 - 11



570    FORMING SCHOTTKY JUNCTION (I.E.,    595   ..Having sidewall structure
          SEMICONDUCTOR-CONDUCTOR          596   ...Portion of sidewall structure
          RECTIFYING JUNCTION CONTACT)              is conductive
571    .Combined with formation of ohmic   597   .To form ohmic contact to
          contact to semiconductor                  semiconductive material
          region                           598   ..Selectively interconnecting
572    .Compound semiconductor                      (e.g., customization, wafer
573    ..Multilayer electrode                       scale integration, etc.)
574    ...T-shaped electrode               599   ...With electrical circuit layout
575    ...Using platinum group metal       600   ...Using structure alterable to
          (i.e., platinum (Pt),                     conductive state (i.e.,
          palladium (Pd), rodium (Rh),              antifuse)
          ruthenium (Ru), iridium (Ir),    601   ...Using structure alterable to
          osmium (Os), or alloy thereof)            nonconductive state (i.e.,
576    ..Into grooved or recessed                   fuse)
          semiconductor region             602   ..To compound semiconductor
577    ...Utilizing lift-off               603   ...II-VI compound semiconductor
578    ...Forming electrode of specified   604   ...III-V compound semiconductor
          shape (e.g., slanted, etc.)      605   ....Multilayer electrode
579    ....T-shaped electrode              606   ....Ga and As containing
580    .Using platinum group metal                  semiconductor
          (i.e., platinum (Pt),            607   ..With epitaxial conductor
          palladium (Pd), rhodium (Rh),             formation
          ruthenium (Ru), iridium (Ir),    608   ..Oxidic conductor (e.g., indium
          osmium (Os), or alloy thereof)            tin oxide, etc.)
581    ..Silicide                          609   ...Transparent conductor
582    .Using refractory group metal       610   ..Conductive macromolecular
          (i.e., titanium (Ti),                     conductor (including metal
          zirconium (Zr), hafnium (Hf),             powder filled composition)
          vanadium (V), niobium (Nb),      611   ..Beam lead formation
          tantalum (Ta), chromium (Cr),    612   ..Forming solder contact or
          molybdenum (Mo), tungsten (W),            bonding pad
          or alloy thereof)
                                           613   ...Bump electrode
583    ..Silicide
                                           614   ....Plural conductive layers
584    COATING WITH ELECTRICALLY OR
                                           615   ....Including fusion of conductor
          THERMALLY CONDUCTIVE MATERIAL
                                           616   .....By transcription from
585    .Insulated gate formation
                                                    auxiliary substrate
586    ..Combined with formation of
                                           617   .....By wire bonding
          ohmic contact to semiconductor
                                           618   ..Contacting multiple
          region
                                                    semiconductive regions (i.e.,
587    ..Forming array of gate
                                                    interconnects)
          electrodes
                                           619   ...Air bridge structure
588    ...Plural gate levels
                                           620   ...Forming contacts of differing
589    ..Recessed into semiconductor
                                                    depths into semiconductor
          substrate
                                                    substrate
590    ..Compound semiconductor
                                           621   ...Contacting diversely doped
591    ..Gate insulator structure                   semiconductive regions (e.g.,
          constructed of plural layers              p-type and n-type regions,
          or nonsilicon containing                  etc.)
          compound
                                           622   ...Multiple metal levels,
592    ..Possessing plural conductive               separated by insulating layer
          layers (e.g., polycide)                   (i.e., multiple level
593    ...Separated by insulator (i.e.,             metallization)
          floating gate)                   623   ....Including organic insulating
594    ....Tunnelling dielectric layer              material between metal levels


                                                                      January 2009
438 - 12           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



624        ....Separating insulating layer     650   ....Having noble group metal
              is laminate or composite of               (i.e., silver (Ag), gold (Au),
              plural insulating materials               platinum (Pt), palladium (Pd),
625        ....At least one metallization               rhodium (Rh), ruthenium (Ru),
              level formed of diverse                   iridium (Ir), osmium (Os), or
              conductive layers                         alloy thereof)
626        .....Planarization                  651   .....Silicide
627        .....At least one layer forms a     652   ..Plural layered electrode or
              diffusion barrier                         conductor
628        .....Having adhesion promoting      653   ...At least one layer forms a
              layer                                     diffusion barrier
629        .....Diverse conductive layers      654   ...Having adhesion promoting
              limited to viahole/plug                   layer
630        ......Silicide formation            655   ...Silicide
631        ....Having planarization step       656   ...Having refractory group metal
632        .....Utilizing reflow                        (i.e., titanium (Ti),
633        .....Simultaneously by chemical              zirconium (Zr), hafnium (Hf),
              and mechanical means                      vanadium (V), niobium (Nb),
634        .....Utilizing etch-stop layer               tantalum (Ta), chromium (Cr),
635        ....Insulator formed by reaction             molybdenum (Mo), tungsten (W),
              with conductor (e.g.,                     or alloy thereof)
              oxidation, etc.)                 657   ...Having electrically conductive
636        ....Including use of                         polysilicon component
              antireflective layer             658   ..Altering composition of
637        ....With formation of opening                conductor
              (i.e., viahole) in insulative    659   ...Implantation of ion into
              layer                                     conductor
638        .....Having viaholes of diverse     660   ..Including heat treatment of
              width                                     conductive layer
639        .....Having viahole with sidewall   661   ...Subsequent fusing conductive
              component                                 layer
640        .....Having viahole of tapered      662   ....Utilizing laser
              shape                            663   ...Rapid thermal anneal
641        ....Selective deposition            664   ....Forming silicide
642        ...Diverse conductors               665   ..Utilizing textured surface
643        ....At least one layer forms a      666   ..Specified configuration of
              diffusion barrier                         electrode or contact
644        ....Having adhesion promoting       667   ...Conductive feedthrough or
              layer                                     through-hole in substrate
645        ....Having planarization step       668   ...Specified aspect ratio of
646        .....Utilizing reflow                        conductor or viahole
647        ....Having electrically             669   ..And patterning of conductive
              conductive polysilicon                    layer
              component                        670   ...Utilizing lift-off
648        ....Having refractory group metal   671   ...Utilizing multilayered mask
              (i.e., titanium (Ti),            672   ...Plug formation (i.e., in
              zirconium (Zr), hafnium (Hf),             viahole)
              vanadium (V), niobium (Nb),      673   ...Tapered etching
              tantalum (Ta), chromium (Cr),    674   ..Selective deposition of
              molybdenum (Mo), tungsten (W),            conductive layer
              or alloy thereof)                675   ...Plug formation (i.e., in
649        .....Silicide                                viahole)
                                               676   ...Utilizing electromagnetic or
                                                        wave energy




January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS               438 - 13



677    ...Pretreatment of surface to       699   ...Plural coating steps
          enhance or retard deposition     700   ..Formation of groove or trench
678    ..Electroless deposition of         701   ...Tapered configuration
          conductive layer                 702   ...Plural coating steps
679    ..Evaporative coating of            703   ..Plural coating steps
          conductive layer                 704   .Having liquid and vapor etching
680    ..Utilizing chemical vapor                   steps
          deposition (i.e., CVD)           705   .Altering etchability of
681    ...Of organo-metallic precursor              substrate region by
          (i.e., MOCVD)                             compositional or crystalline
682    ..Silicide                                   modification
683    ...Of refractory group metal        706   .Vapor phase etching (i.e., dry
          (i.e., titanium (Ti),                     etching)
          zirconium (Zr), hafnium (Hf),    707   ..Utilizing electromagnetic or
          vanadium (V), niobium (Nb),               wave energy
          tantalum (Ta), chromium (Cr),    708   ...Photo-induced etching
          molybdenum (Mo), tungsten (W),   709   ....Photo-induced plasma etching
          or alloy thereof)                710   ...By creating electric field
684    ..Electrically conductive                    (e.g., plasma, glow discharge,
          polysilicon                               etc.)
685    ..Refractory group metal (i.e.,     711   ....Utilizing multiple gas
          titanium (Ti), zirconium (Zr),            energizing means
          hafnium (Hf), vanadium (V),      712   ....Reactive ion beam etching
          niobium (Nb), tantalum (Ta),              (i.e., RIBE)
          chromium (Cr), molybdenum        713   ....Forming tapered profile
          (Mo), tungsten (W), or alloy              (e.g., tapered etching, etc.)
          thereof)
                                           714   ....Including change in etch
686    ..Noble group metal (i.e., silver            influencing parameter (e.g.,
          (Ag), gold (Au), platinum                 energizing power, etchant
          (Pt), palladium (Pd), rhodium             composition, temperature,
          (Rh), ruthenium (Ru), iridium             etc.)
          (Ir), osmium (Os), or alloy
                                           715   ....With substrate heating or
          thereof)
                                                    cooling
687    ..Copper of copper alloy
                                           716   ....With substrate handling
          conductor
                                                    (e.g., conveying, etc.)
688    ..Aluminum or aluminum alloy
                                           717   ....Utilizing multilayered mask
          conductor
                                           718   ....Compound semiconductor
689    CHEMICAL ETCHING
                                           719   ....Silicon
690    .Combined with the removal of
                                           720   ....Electrically conductive
          material by nonchemical means
                                                    material (e.g., metal,
          (e.g., ablating, abrading,
                                                    conductive oxide, etc.)
          etc.)
                                           721   .....Silicide
691    ..Combined mechanical and
                                           722   ....Metal oxide
          chemical material removal
                                           723   ....Silicon oxide or glass
692    ...Simultaneous (e.g., chemical-
                                           724   ....Silicon nitride
          mechanical polishing, etc.)
693    ....Utilizing particulate
                                           725   ....Organic material (e.g.,
                                                    resist, etc.)
          abradant
                                           726   ....Having microwave gas
694    .Combined with coating step
                                                    energizing
695    ..Simultaneous etching and
                                           727   .....Producing energized gas
          coating
                                                    remotely located from
696    ..Coating of sidewall
                                                    substrate
697    ..Planarization by etching and
                                           728   ......Using magnet (e.g.,
          coating
                                                    electron cyclotron resonance,
698    ...Utilizing reflow
                                                    etc.)


                                                                       January 2009
438 - 14           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



729        ....Using specified electrode/      754   ..Electrically conductive
              susceptor configuration (e.g.,            material (e.g., metal,
              of multiple substrates using              conductive oxide, etc.)
              barrel-type susceptor, planar    755   ...Silicide
              reactor configuration, etc.)     756   ..Silicon oxide
              to generate plasma               757   ..Silicon nitride
730        .....Producing energized gas        758   COATING OF SUBSTRATE CONTAINING
              remotely located from                     SEMICONDUCTOR REGION OR OF
              substrate                                 SEMICONDUCTOR SUBSTRATE
731        ......Using intervening shield      759   .Combined with the removal of
              structure                                 material by nonchemical means
732        ....Using magnet (e.g., electron    760   .Utilizing reflow (e.g.,
              cyclotron resonance, etc.)                planarization, etc.)
733        ...Using or orientation dependent   761   .Multiple layers
              etchant (i.e., anisotropic       762   ..At least one layer formed by
              etchant)                                  reaction with substrate
734        ..Sequential etching steps on a     763   ..Layers formed of diverse
              single layer                              composition or by diverse
735        ..Differential etching of                    coating processes
              semiconductor substrate          764   .Formation of semi-insulative
736        ...Utilizing multilayered mask               polycrystalline silicon
737        ...Substrate possessing multiple    765   .By reaction with substrate
              layers                           766   ..Implantation of ion (e.g., to
738        ....Selectively etching substrate            form ion amorphousized region
              possessing multiple layers of             prior to selective oxidation,
              differing etch characteristics            reacting with substrate to
739        .....Lateral etching of                      form insulative region, etc.)
              intermediate layer (i.e.,        767   ..Compound semiconductor
              undercutting)                             substrate
740        .....Utilizing etch stop layer      768   ..Reaction with conductive region
741        ......PN junction functions as      769   ..Reaction with silicon
              etch stop                                 semiconductive region (e.g.,
742        ....Electrically conductive                  oxynitride formation, etc.)
              material (e.g., metal,           770   ...Oxidation
              conductive oxide, etc.)          771   ....Using electromagnetic or wave
743        ....Silicon oxide or glass                   energy
744        ....Silicon nitride                 772   .....Microwave gas energizing
745        .Liquid phase etching               773   ....In atmosphere containing
746        ..Utilizing electromagnetic or               water vapor (i.e., wet
              wave energy                               oxidation)
747        ..With relative movement between    774   ....In atmosphere containing
              substrate and confined pool of            halogen
              etchant                          775   ...Nitridation
748        ..Projection of etchant against a   776   ....Using electromagnetic or wave
              moving substrate or                       energy
              controlling the angle or         777   .....Microwave gas energizing
              pattern of projected etchant     778   .Insulative material deposited
749        ..Sequential application of                  upon semiconductive substrate
              etchant                          779   ..Compound semiconductor
750        ...To same side of substrate                 substrate
751        ....Each etch step exposes          780   ..Depositing organic material
              surface of an adjacent layer              (e.g., polymer, etc.)
752        ..Germanium                         781   ...Subsequent heating modifying
753        ..Silicon                                    organic coating composition



January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS              438 - 15



782    ..With substrate handling during    904   CHARGE CARRIER LIFETIME CONTROL
          coating (e.g., immersion,        905   CLEANING OF REACTION CHAMBER
          spinning, etc.)                  906   CLEANING OF WAFER AS INTERIM STEP
783    ..Insulative material having        907   CONTINUOUS PROCESSING
          impurity (e.g., for altering     908   .Utilizing cluster apparatus
          physical characteristics,        909   CONTROLLED ATMOSPHERE
          etc.)                            910   CONTROLLING CHARGING STATE AT
784    ...Introduction simultaneous with            SEMICONDUCTOR-INSULATOR
          deposition                                INTERFACE
785    ..Insulative material is compound   911   DIFFERENTIAL OXIDATION AND
          of refractory group metal                 ETCHING
          (i.e., titanium (Ti),            912   DISPLACING PN JUNCTION
          zirconium (Zr), hafnium (Hf),    913   DIVERSE TREATMENTS PERFORMED IN
          vanadium (V), niobium (Nb),               UNITARY CHAMBER
          tantalum (Ta), chromium (Cr),    914   DOPING
          molybdenum (Mo), tungsten (W),
                                           915   .Amphoteric doping
          or alloy thereof)
                                           916   .Autodoping control or
786    ..Tertiary silicon containing
                                                    utilization
          compound formation (e.g.,
                                           917   .Deep level dopants (e.g., gold
          oxynitride formation, etc.)
                                                    (Au), chromium (Cr), iron
787    ..Silicon oxide formation
                                                    (Fe), nickel (Ni), etc.)
788    ...Using electromagnetic or wave
                                           918   .Special or nonstandard dopant
          energy (e.g., photo-induced
                                           919   .Compensation doping
          deposition, plasma, etc.)
                                           920   .Controlling diffusion profile by
789    ....Organic reactant
                                                    oxidation
790    ...Organic reactant
                                           921   .Nonselective diffusion
791    ..Silicon nitride formation
                                           922   .Diffusion along grain boundaries
792    ...Utilizing electromagnetic or
                                           923   .Diffusion through a layer
          wave energy (e.g., photo-
          induced deposition, plasma,
                                           924   .To facilitate selective etching
          etc.)                            925   .Fluid growth doping control
793    ....Organic reactant                         (e.g., delta doping, etc.)
794    ...Organic reactant                 926   DUMMY METALLIZATION
795    RADIATION OR ENERGY TREATMENT       927   ELECTROMIGRATION RESISTANT
          MODIFYING PROPERTIES OF                   METALLIZATION
          SEMICONDUCTOR REGION OF          928   FRONT AND REAR SURFACE PROCESSING
          SUBSTRATE (E.G., THERMAL,        929   EUTECTIC SEMICONDUCTOR
          CORPUSCULAR, ELECTROMAGNETIC,    930   TERNARY OR QUATERNARY
          ETC.)                                     SEMICONDUCTOR COMPRISED OF
796    .Compound semiconductor                      ELEMENTS FROM THREE DIFFERENT
797    ..Ordering or disordering                    GROUPS (E.G., I-III-V, ETC.)
798    .Ionized irradiation (e.g.,         931   SILICON CARBIDE SEMICONDUCTOR
          corpuscular or plasma            932   BORON NITRIDE SEMICONDUCTOR
          treatment, etc.)                 933   GERMANIUM OR SILICON OR GE-SI ON
799    .By differential heating                     III-V
800    MISCELLANEOUS                       934   SHEET RESISTANCE (I.E., DOPANT
                                                    PARAMETERS)
                                           935   GAS FLOW CONTROL
                                           936   GRADED ENERGY GAP
CROSS-REFERENCE ART COLLECTIONS            937   HILLOCK PREVENTION
                                           938   LATTICE STRAIN CONTROL OR
                                                    UTILIZATION
900    BULK EFFECT DEVICE MAKING
                                           939   LANGMUIR-BLODGETT FILM
901    CAPACITIVE JUNCTION
                                                    UTILIZATION
902    CAPPING LAYER
                                           940   LASER ABLATIVE MATERIAL REMOVAL
903    CATALYST AIDED DEPOSITION
                                           941   LOADING EFFECT MITIGATION


                                                                      January 2009
438 - 16           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



942        MASKING                             982                      VARYING ORIENTATION OF DEVICES IN
943        .Movable                                                        ARRAY
944        .Shadow                             983                      ZENER DIODES
945        .Special (e.g., metal, etc.)
946        .Step and repeat
947        .Subphotolithographic processing
948        .Radiation resist                   FOREIGN ART COLLECTIONS
949        ..Energy beam treating radiation
              resist on semiconductor          FOR 000 CLASS-RELATED FOREIGN DOCUMENTS
950        ..Multilayer mask including         MOC NOTES
                                               Any foreign patents...



              nonradiation sensitive layer     Any foreign patents or non-patent litera-
951        ..Lift-off                          ture from subclasses that have been
952        ..Utilizing antireflective layer    reclassified have been transferred
953        MAKING RADIATION RESISTANT DEVICE   directly to FOR Collections listed below.
954        MAKING OXIDE-NITRIDE-OXIDE DEVICE   These Collections contain ONLY foreign
                                               patents or non-patent literature. The par-
955        MELT-BACK
                                               enthetical references in the Collection
956        MAKING MULTIPLE WAVELENGTH
                                               titles refer to the abolished subclasses
              EMISSIVE DEVICE
                                               from which these Collections were derived.
957        MAKING METAL-INSULATOR-METAL        Any foreign patents...




              DEVICE
958        PASSIVATION LAYER
959        MECHANICAL POLISHING OF WAFER
960        POROUS SEMICONDUCTOR                                         METHODS (156/1)
961        ION BEAM SOURCE AND GENERATION      FOR 100 .Etching of semiconductor
962        QUANTUM DOTS AND LINES                                          precursor, substrates, and
963        REMOVING PROCESS RESIDUES FROM                                  devices used in an electrical
              VERTICAL SUBSTRATE SURFACES                                  function (156/625.1)
964        ROUGHENED SURFACE                   FOR 101                  ..Measuring, testing, or
                                                                           inspecting (156/626.1)
965        SHAPED JUNCTION FORMATION
966        SELECTIVE OXIDATION OF ION-
                                               FOR 102                  ...By electrical means or of
                                                                           electrical property (156/
              AMORPHOUSIZED LAYER
                                                                           627.1)
967        SEMICONDUCTOR ON SPECIFIED
              INSULATOR
                                               FOR 103                  ..Altering the etchability of a
                                                                           substrate by alloying,
968        SEMICONDUCTOR-METAL-SEMICONDUCTOR
                                                                           diffusing, or chemical
969        SIMULTANEOUS FORMATION OF
                                                                           reacting (156/628.1)
              MONOCRYSTALLINE AND
                                               FOR 104                  ..With uniting of preforms (e.g.,
              POLYCRYSTALLINE REGIONS
                                                                           laminating, etc.) (156/629.1)
970        SPECIFIED ETCH STOP MATERIAL
                                               FOR 105                  ...Prior to etching (156/630.1)
971        STOICHIOMETRIC CONTROL OF HOST
                                               FOR 106                  ....Delamination subsequent to
              SUBSTRATE COMPOSITION
                                                                           etching (156/631.1)
972        STORED CHARGE ERASURE
                                               FOR 107                  ....With coating (156/632.1)
973        SUBSTRATE ORIENTATION
                                               FOR 108                  ...Differential etching (156/
974        SUBSTRATE SURFACE PREPARATION
                                                                           633.1)
975        SUBSTRATE OR MASK ALIGNING
                                               FOR 109                  ....Metal layer etched (156/
              FEATURE
                                                                           634.1)
976        TEMPORARY PROTECTIVE LAYER
                                               FOR 110                  ..With in situ activation or
977        THINNING OR REMOVAL OF SUBSTRATE
                                                                           combining of etching
978        FORMING TAPERED EDGES ON                                        components on surface (156/
              SUBSTRATE OR ADJACENT LAYERS                                 635.1)
979        TUNNEL DIODES                       FOR 111                  ..With thin film of etchant
980        UTILIZING PROCESS EQUIVALENTS OR                                between relatively moving
              OPTIONS                                                      substrate and conforming
981        UTILIZING VARYING DIELECTRIC                                    surface (e.g., chemical
              THICKNESS                                                    lapping, etc.) (156/636.1)


January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS                       438 - 17



FOR 112 ..With relative movement between      FOR 133 ....Plural resist coating (156/
             the substrate and a confined                   661.11)
             pool of etchant (156/637.1)      FOR 134 ..Silicon, germanium, or gallium
FOR 113   ...With removal of adhered                         containing substrate (156/
             reaction product from                           662.1)
             substrate (156/638.1)            FOR 135     MAKING DEVICE HAVING ORGANIC
FOR 114   ...With substrate rotation,                        SEMICONDUCTOR COMPONENT (437/
             repeated dipping, or advanced                   1)
             movement (156/639.1)             FOR 136     MAKING DEVICE RESPONSIVE TO
FOR 115   ..Projection of etchant against a                  RADIATION (437/2)
             moving substrate or              FOR 137     .Radiation detectors, e.g.,
             controlling the angle or                        infrared, etc. (437/3)
             pattern of projected etchant     FOR 138     .Composed of polycrystalline
             (156/640.1)                                     material (437/4)
FOR 116   ..Recycling or regenerating         FOR 139     .Having semiconductor compound
             etchant (156/642.1)                             (437/5)
FOR 117   ..With treatment by high energy     FOR 140     MAKING THYRISTOR, E.G., DIAC,
             radiation or plasma (e.g., ion                  TRIAC, ETC. (437/6)
             beam, etc.) (156/643.1)          FOR 141     INCLUDING CONTROL RESPONSIVE TO
FOR 118   ..Forming or increasing the size                   SENSED CONDITION (437/7)
             of an aperture (156/644.1)       FOR 142     INCLUDING TESTING OR MEASURING
FOR 119   ..With mechanical deformation,                     (437/8)
             severing, or abrading of a       FOR 143     INCLUDING APPLICATION OF
             substrate (156/ 645.1)                          VIBRATORY FORCE (437/9)
FOR 120   ..Etchant is a gas (156/646.1)      FOR 144     INCLUDING GETTERING (437/10)
FOR 121   ..Etching according to              FOR 145     .By ion implanting or irradiating
             crystalline planes (156/647.1)                  (437/11)
FOR 122   ..Etching isolates or modifies a    FOR 146     .By layers which are coated,
             junction in a barrier layer                     contacted, or diffused (437/
             (156/648.1)                                     12)
FOR 123   ...Discrete junction isolated       FOR 147     .By vapor phase surface reaction
             (e.g., mesa formation, etc.)                    (437/13)
             (156/649.1)                      FOR 148     THERMOMIGRATION (437/14)
FOR 124   ..Sequential application of         FOR 149     INCLUDING FORMING A SEMICONDUCTOR
             etchant material (156/650.1)                    JUNCTION (437/15)
FOR 125   ...Sequentially etching the same    FOR 150     .Using energy beam to introduce
             surface of a substrate (156/                    dopant or modify dopant
             651.1)                                          distribution (437/ 16)
FOR 126   ....Each etching exposes surface    FOR 151     ..Neutron, gamma ray or electron
             of an adjacent layer (156/                      beam (437/17)
             652.1)                           FOR   152   ..Ionized molecules (437/18)
FOR 127   .....Etched layer contains          FOR   153   ..Coherent light beam (437/19)
             silicon (e.g., oxide, nitride,
                                              FOR   154   ..Ion beam implantation (437/20)
             etc.) (156/653.1)
                                              FOR   155   ..Of semiconductor on insulating
FOR 128   ..Differential etching of a
                                                             substrate (437/21)
             substrate (156/654.1)
                                              FOR 156     ...Of semiconductor compound
FOR 129   ...Composite substrate (156/
                                                             (437/22)
             655.1)
                                              FOR 157     ....Light emitting diode (LED)
FOR 130   ....Substrate contains metallic
                                                             (437/23)
             element or compound (156/
                                              FOR 158     ...Providing nondopant ion
             656.1)
                                                             including proton (437/24)
FOR 131   ....Substrate contains silicon or
                                              FOR 159     ...Providing auxiliary heating
             silicon compound (156/657.1)
                                                             (437/25)
FOR 132   ...Resist coating (156/659.11)
                                              FOR 160     ...Forming buried region (437/26)



                                                                               January 2009
438 - 18            CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



FOR 161 ...Including multiple                   FOR 196 .....Specifics of metallization/
               implantations of same region                 contact (437/41 SM)
               (437/27)                         FOR 197 .....Recessed gate (Schottky
FOR 162     ....Through insulating layer                    falls below in SH) (437/41 RG)
               (437/28)                         FOR 198 .....Schottky gate/MESFET (437/41
FOR 163     .....Forming field effect                       SH)
               transistor (FET) type device     FOR 199 .....Sidewall (437/41 SW)
               (437/29)                         FOR 200 .....Thin film transistor,
FOR 164     ....Using same conductivity type                inverted (437/41 TFI)
               dopant (437/30)                  FOR 201 .....Thin film transistor (437/41
FOR 165     ....Forming bipolar transistor                  TFT)
               (NPN/PNP) (437/31)               FOR 174 ....Forming pair of device
FOR 166     .....Lateral bipolar transistor                  regions separated by gate
               (437/32)                                      structure, i.e., FET (437/40
FOR 167     .....Having dielectric isolation                 R)
               (437/33)                         FOR 175   ....Asymmetrical FET (any
FOR 168     ....Forming complementary MOS                    asymmetry in S/D profile, gate
               (metal oxide semiconductor)                   spacing, etc.) (437/40 AS)
               (437/34)                         FOR 176   ....DMOS/vertical FET (437/40 DM)
FOR 169     ...Using oblique beam (437/35)      FOR 177   ....Gate specific (specifics of
FOR 170     ...Using shadow mask (437/36)                    gate insulator/structure/
FOR 171     ...Having projected range less                   material/ contact) (437/40 GS)
               than thickness of dielectrics    FOR 178   ....Junction FET/static induction
               on substrate (437/37)                         transistor (437/40 JF)
FOR 172     ...Into shaped or grooved           FOR 179   ....Layered channel (e.g., HEMT,
               semiconductor substrate (437/                 MODFET, 2DEG, heterostructure
               38)                                           FETS) (437/40 LC)
FOR 173     ...Involving Schottky contact       FOR 180   ....Recessed gate (437/40 RG)
               formation (437/39)               FOR 181   ....Schottky gate/MESFET
FOR 202     ....Gate structure constructed of                (controls over RG) (437/40 SH)
               diverse dielectrics (437/42)     FOR 182   ....Sidewall (not LDD`s) (437/40
FOR 203     .....Gate surrounded by                          SW)
               dielectric layer, e.g.,          FOR 183   ....Thin film transistor
               floating gate, etc. (437/43)                  inverted/staggered (437/40
FOR 204     .....Adjusting channel dimension                 TFI)
               (437/44)                         FOR 184   ....Thin film transistor (437/40
FOR 205     .....Active step for controlling                 TFT)
               threshold voltage (437/45)       FOR 206   ...Into polycrystalline or
FOR   185   .....Self-aligned (437/41 R)                     polyamorphous regions (437/46)
FOR   186   .....With bipolar (437/41 RBP)      FOR 207   ...Integrating active with
FOR   187   .....CMOS (437/41 RCM)                           passive devices (437/47)
FOR   188   .....Lightly doped drain (437/41    FOR 208   ...Forming plural active devices
               RLD)                                          in grid/array, e.g., RAMS/
FOR 189     .....Memory devices (437/41 RMM)                 ROMS, etc. (437/48)
FOR 190     .....Asymmetrical FET (437/41 AS)   FOR 209   ....Having multiple-level
FOR 191     .....Channel specifics (437/41                   electrodes (437/49)
               CS)                              FOR 210   ...Forming electrodes in
FOR 192     .....DMOS/vertical FET (437/41                   laterally spaced relationships
               DM)                                           (437/50)
FOR 193     .....Gate specifics (437/41 GS)     FOR 211   .Making assemblies of plural
FOR 194     .....Junction FET/static                         individual devices having
               induction transistor (437/41                  community feature, e.g.,
               JF)                                           integrated circuit, electrical
FOR 195     .....Layered channel (437/41 LC)                 connection, etc. (437/51)
                                                FOR 212   ..Memory devices (437/52)


January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS                     438 - 19



FOR 213 ..Charge coupled devices (CCD)        FOR 238 ...By etching and refilling with
             (437/53)                                      semiconductor material having
FOR 214   ..Diverse types (437/54)                         diverse conductivity (437/78)
FOR 215   ...Integrated injection logic       FOR 239   ...Using polycrystalline region
             (I2L) circuits (437/55)                       (437/79)
FOR 216   ...Plural field effect              FOR 240   .Shadow masking (437/80)
             transistors (CMOS) (437/56)      FOR 241   .Doping during fluid growth of
FOR 217   ....Complementary metal oxide                    semiconductor material on
             having diverse conductivity                   substrate (437/81)
             source and drain regions (437/   FOR 242   ..Including heat to anneal (437/
             57)                                           82)
FOR 218   ....Having like conductivity        FOR 243   ..Growing single crystal on
             source and drain regions (437/                amorphous substrate (437/83)
             58)                              FOR 244   ..Growing single crystal on
FOR 219   ...Including field effect                        single crystal insulator (SOS)
             transistor (437/59)                           (437/84)
FOR 220   ...Including passive device (437/   FOR 245   ..Including purifying stage
             60)                                           during growth (437/85)
FOR 221   .Including isolation step (437/     FOR 246   ..Using transitory substrate
             61)                                           (437/86)
FOR 222   ..By forming total dielectric       FOR 247   ..Using inert atmosphere (437/87)
             isolation (437/62)               FOR 248   ..Using catalyst to alter growth
FOR 223   ..By forming vertical isolation                  process (437/88)
             combining dielectric and PN      FOR 249   ..Growth through opening (437/89)
             junction (437/63)                FOR 250   ...Forming recess in substrate
FOR 224   ..Using vertical dielectric (air-                and refilling (437/90)
             gap/insulator) and horizontal    FOR 251   ....By liquid phase epitaxy (437/
             PN junction (437/64)                          91)
FOR 225   ...Grooved air-gap only (437/65)    FOR 252   ...By liquid phase epitaxy (437/
FOR 226   ....V-groove (437/66)                            92)
FOR 227   ...Grooved and refilled with        FOR 253   ..Specified crystal orientation
             insulator (437/67)                            other than (100) or (111)
FOR 228   ....V-groove (437/68)                            planes (437/93)
FOR 229   ...Recessed oxide by localized      FOR 254   ..Introducing minority carrier
             oxidation (437/69)                            life time reducing dopant
FOR 230   ....Preliminary formation of                     during growth, i.e., deep
             guard ring (437/70)                           level dopant Au (Gold), Cr
FOR 231   ....Preliminary anodizing (437/                  (Cromium), Fe (Iron), Ni
             71)                                           (Nickel), etc. (437/94)
FOR 232   ....Preliminary etching of groove   FOR 255   ..Autodoping control (437/95)
             (437/72)                         FOR 256   ...Compound formed from Group III
FOR 233   .....Using overhanging oxidation                 and Group V elements (437/96)
             mask and pretreatment of         FOR 257   ..Forming buried regions with
             recessed walls (437/ 73)                      outdiffusion control (437/97)
FOR 234   ..Isolation by PN junction only     FOR 258   ...Plural dopants simultaneously
             (437/74)                                      outdiffusioned (437/98)
FOR 235   ...By diffusion from upper          FOR 259   ..Growing mono and
             surface only (437/75)                         polycrystalline regions
FOR 236   ...By up-diffusion from substrate                simultaneously (437/99)
             region and down diffusion into   FOR 260   ..Growing silicon carbide (SiC)
             upper surface layer (437/76)                  (437/100)
FOR 237   ....Substrate and epitaxial         FOR 261   ..Growing amorphous semiconductor
             regions of same conductivity                  material (437/101)
             type, i.e., P or N (437/77)      FOR 262   ..Source and substrate in close-
                                                           space relationship (437/102)


                                                                             January 2009
438 - 20           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



FOR 263 ...Group IV elements (437/103)         FOR 291 ...Si (Silicon on Ge (Germanium)
FOR 264 ...Compound formed from Group III                   or Ge (Germanium) on Si
              and Group V elements (437/104)                (Silicon) (437/131)
FOR 265    ..Vacuum growing using molecular    FOR 292   ...Either Si (Silicon) or Ge
              beam, i.e., vacuum deposition                 (Germanium) layered with or on
              (437/105)                                     compound formed from Group III
FOR 266    ...Group IV elements (437/106)                   and Group V elements (437/132)
FOR 267    ...Compound formed from Group III   FOR 293   ...Compound formed from Group III
              and Group V elements (437/107)                and Group V elements on
FOR 268    ..Growing single layer in multi-                 diverse Group III and Group V
              steps (437/108)                               including substituted Group
FOR 269    ...Polycrystalline layers (437/                  III and Group V compounds
              109)                                          (437/133)
FOR 270    ...Using modulated dopants or       FOR 294   .By fusing dopant with substrate,
              materials, e.g., superlattice,                e.g., alloying, etc. (437/134)
              etc. (437/110)                   FOR 295   ..Using flux (437/135)
FOR 271    ...Using preliminary or             FOR 296   ..Passing electric current
              intermediate metal layer (437/                through material (437/136)
              111)                             FOR 297   ..With application of pressure to
FOR 272    ...Growing by varying rates (437/                material during fusing (437/
              112)                                          137)
FOR 273    ..Using electric current, e.g.,     FOR 298   ..Including plural controlled
              Peltier effect, glow                          heating or cooling steps (437/
              discharge, etc. (437/ 113)                    138)
FOR 274    ..Using seed in liquid phase        FOR 299   ..Including diffusion after
              (437/114)                                     fusion step (437/139)
FOR 275    ...Pulling from melt (437/115)      FOR 300   ..Including additional material
FOR 276    ....And diffusing (437/116)                      to improve wettability or flow
FOR 277    ..Liquid and vapor phase epitaxy                 characteristics (437/140)
              in sequence (437/117)            FOR 301   .Diffusing a dopant (437/141)
FOR 278    ..Involving capillary action        FOR 302   ..To control carrier lifetime,
              (437/118)                                     i.e., deep level dopant Au
FOR 279    ..Sliding liquid phase epitaxy                   (Gold), Cr (Chromium), Fe
              (437/119)                                     (Iron), Ni (Nickel), etc.
                                                            (437/142)
FOR 280    ...Modifying melt composition
              (437/120)
                                               FOR 303   ..Al (Aluminum) dopant (437/143)
FOR 281    ...Controlling volume or
                                               FOR 304   ..Li (Lithium) dopant (437/144)
              thickness of growth (437/121)    FOR 305   ..Including nonuniform heating
                                                            (437/145)
FOR 282    ...Preliminary dissolving
              substrate surface (437/122)      FOR 306   ..To solid state solubility
                                                            concentration (437/146)
FOR 283    ...With nonlinear slide movement
              (437/123)                        FOR 307   ..Using multiple layered mask
                                                            (437/147)
FOR 284    ...One melt simultaneously
              contacting plural substrates     FOR 308   ...Having plural predetermined
              (437/124)                                     openings in master mask (437/
                                                            148)
FOR 285    ..Tipping liquid phase epitaxy
              (437/125)                        FOR 309   ..Forming partially overlapping
                                                            regions (437/149)
FOR 286    ..Heteroepitaxy (437/126)
FOR 287    ...Multi-color light emitting
                                               FOR 310   ..Plural dopants in same region,
                                                            e.g., through same mask
              diode (LED) (437/127)
                                                            opening, etc. (437/150)
FOR 288    ...Graded composition (437/128)
                                               FOR 311   ...Simultaneously (437/151)
FOR 289    ...Forming laser (437/129)
                                               FOR 312   ..Plural dopants simultaneously
FOR 290    ...By liquid phase epitaxy (437/
                                                            in plural region (437/152)
              130)



January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS                       438 - 21



FOR 313 ..Single dopant forming plural          FOR 339 .Using metal, i.e., Pt
               diverse regions (437/153)                     (Platinum), Pd (Palladium), Rh
FOR 314     ...Forming regions of different                  (Rhodium), Ru (Ruthenium), Ir
               concentrations or different                   (Iridium), Os (Osmium), Au
               depths (437/154)                              (Gold), Ag (Silver) (437/179)
FOR   315   ..Using metal mask (437/155)        FOR 340   MAKING OR ATTACHING ELECTRODE ON
FOR   316   ..Outwardly (437/156)                            OR TO SEMICONDUCTOR, OR
FOR   317   ..Laterally under mask (437/157)                 SECURING COMPLETED
FOR   318   ..Edge diffusion by using edge                   SEMICONDUCTOR TO MOUNTING OR
               portion of structure other                    HOUSING (437/180)
               than masking layer to mask       FOR 341   .Forming transparent electrode
               (437/158)                                     (437/181)
FOR 319     ..From melt (437/159)               FOR 342   .Forming beam electrode (437/182)
FOR 320     ..From solid dopant source in       FOR 343   .Forming bump electrode (437/183)
               contact with substrate (437/     FOR 344   .Electrode formed on substrate
               160)                                          composed of elements of Group
FOR 321     ...Using capping layer over                      III and Group V semiconductor
               dopant source to prevent                      compound (437/184)
               outdiffusion of dopant (437/     FOR 345   .Electrode formed on substrate
               161)                                          composed of elements of Group
FOR 322     ...Polycrystalline semiconductor                 II and Group VI semiconductor
               source (437/162)                              compound (437/185)
FOR 323     ...Organic source (437/163)         FOR 346   .Single polycrystalline electrode
FOR 324     ...Glassy source or doped oxide                  layer on substrate (437/186)
               (437/164)                        FOR 347   .Single metal layer electrode on
FOR   325   ..From vapor phase (437/165)                     substrate (437/187)
FOR   326   ...In plural stages (437/166)       FOR 348   ..Subsequently fusing, e.g.,
FOR   327   ...Zn (Zinc) dopant (437/167)                    alloying, sintering, etc.
FOR   328   ...Solid source is operative                     (437/188)
               relation with semiconductor      FOR 349   .Forming plural layered electrode
               material (437/168)                            (437/189)
FOR 329     ....In capsule type enclosure       FOR 350   ..Including central layer acting
               (437/169)                                     as barrier between outer
FOR 330     DIRECTLY APPLYING ELECTRICAL                     layers (437/190)
               CURRENT (437/170)                FOR 351   ..Of polysilicon only (437/191)
FOR 331     .And regulating temperature (437/   FOR 352   ..Including refractory metal
               171)                                          layer of Ti (Titanium), Zr
FOR 332     .Alternating or pulsed current                   (Zirconium), Hf (Hafnium), V
               (437/172)                                     (Vanadium), Nb (Niobium), Ta
                                                             (Tantalum), Cr (Chromium), Mo
FOR 333     APPLYING CORPUSCULAR OR
                                                             (Molybdenum), W (Tungsten)
               ELECTROMAGNETIC ENERGY (437/
                                                             (437/192)
               173)
                                                FOR 353   ..Including polycrystalline
FOR 334     .To anneal (437/174)
                                                             silicon layer (437/193)
FOR 335     FORMING SCHOTTKY CONTACT (437/
                                                FOR 354   ..Including Al (Aluminum) layer
               175)
                                                             (437/194)
FOR 336     .On semiconductor compound (437/
                                                FOR 355   ..Including layer separated by
               176)
                                                             insulator (437/195)
FOR 337     ..Multi-layer electrode (437/177)
                                                FOR 356   .Forming electrode of alloy or
FOR 338     .Using platinum group silicide,
                                                             electrode of a compound of Si
               i.e., silicide of Pt
                                                             (Silicon) (437/196)
               (Platinum), Pd (Palladium), Rh
                                                FOR 357   ..Al (Aluminum) alloy (437/197)
               (Rhodium), Ru (Ruthenium), Ir
               (Iridium), Os (Osmium) (437/     FOR 358   ...Including Cu (Copper) (437/
               178)                                          198)




                                                                               January 2009
438 - 22           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



FOR 359 ...Including Si (Silicon) (437/        FOR 384 ...Including encapsulating (437/
              199)                                           224)
FOR 360    ..Silicide of Ti (Titanium), Zr     FOR 385 INCLUDING COATING OR MATERIAL
              (Zirconium), Hf (Hafnium), V                    REMOVAL, E.G., ETCHING,
              (Vanadium), Nb (Niobium), Ta                    GRINDING, ETC. (437/ 225)
              (Tantalum), Cr (Chromium), Mo    FOR 386     .Substrate dicing (437/226)
              (Molybdenum), W (Tungsten),      FOR 387     ..With a perfecting coating (437/
              (437/200)                                       227)
FOR 361    ..Of plantinum metal group Ru       FOR 388     .Coating and etching (437/228)
              (Ruthenium), Rh (Rhodium), Pd    FOR 389     .Of radiation resist layer (437/
              (Palladium), Os (Osmium), Ir                    229)
              (Iridium), Pt (Platinum) (437/   FOR 390     .By immersion metal plating from
              201)                                            solution, i.e., electroless
FOR 362    ..By fusing metal with                             plating (437/230)
              semiconductor (alloying) (437/   FOR 391     .By spinning (437/231)
              202)                             FOR 392     .Elemental Se (Selenium)
FOR 363    .Depositing electrode in                           substrate or coating (437/232)
              preformed recess in substrate    FOR 393     .Of polycrystalline semiconductor
              (437/203)                                       material on substrate (437/
FOR 364    .Including positioning of point                    233)
              contact (437/204)                FOR 394     ..Semiconductor compound or mixed
FOR 365    .Making plural devices (437/205)                   semiconductor material (437/
FOR 366    ..Using strip lead frame (437/                     234)
              206)                             FOR 395     .Of a dielectric or insulative
FOR 367    ...And encapsulating (437/207)                     material (437/235)
FOR 368    ..Stacked array, e.g., rectifier,   FOR 396     ..Containing Group III atom (437/
              etc. (437/208)                                  236)
FOR 369    .Securing completed semiconductor   FOR 397     ...By reacting with substrate
              to mounting, housing or                         (437/237)
              external lead (437/209)          FOR 398     ..Monoxide or dioxide or Ge
FOR 370    ..Including contaminant removal                    (Germanium) or Si (Silicon)
              (437/210)                                       (437/238)
FOR 371    ..Utilizing potting or              FOR 399     ...By reacting with substrate
              encapsulating material only to                  (437/239)
              surround leads and device to     FOR 400     ...Doped with impurities (437/
              maintain position, i.e.                         240)
              without housing (437/211)        FOR 401     ..Si (Silicon) and N (Nitrogen)
FOR 372    ...Including application of                        (437/241)
              pressure (437/212)               FOR 402     ...By chemical reaction with
FOR 373    ...Glass material (437/213)                        substrate (437/242)
FOR 374    ..Utilizing header (molding         FOR 403     ..Directly on semiconductor
              surface means) (437/214)                        substrate (437/243)
FOR 375    ..Insulating housing (437/215)      FOR 404     ...By chemical conversion of
FOR 376    ...Including application of                        substrate (437/244)
              pressure (437/216)               FOR 405     .Comprising metal layer (437/245)
FOR 377    ...And lead frame (437/217)         FOR 406     ..On metal (437/246)
FOR 378    ...Ceramic housing (437/218)        FOR 407     TEMPERATURE TREATMENT MODIFYING
FOR 379    ...Including encapsulating (437/                   PROPERTIES OF SEMICONDUCTOR,
              219)                                            E.G., ANNEALING, SINTERING,
FOR 380    ..Lead frame (437/220)                             ETC. (437/247)
FOR 381    ..Metallic housing (437/221)        FOR   408   .Heating and cooling (437/248)
FOR 382    ...Including application of         FOR   409   INCLUDING SHAPING (437/249)
              pressure (437/222)               FOR   410   MISCELLANEOUS (437/250)
FOR 383    ...Including glass support base     FOR   411   UTILIZING PROCESS EQUIVALENTS OR
              (437/223)                                       OPTIONS (437/900)


January 2009
CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS                         438 - 23



FOR 412 MAKING PRESSURE SENSITIVE DEVICE        FOR 440 RADIATION ENHANCED DIFFUSION
               (437/901)                                      (R.E.D.) (437/929)
FOR 413     MAKING DEVICE HAVING HEAT SINK      FOR 441 ION BEAM SOURCE AND GENERATION
               (437/902)                                      (437/930)
FOR   414   MAKING THERMOPILE (437/903)         FOR 442 IMPLANTATION THROUGH MASK (437/
FOR   415   MAKING DIODE (437/904)                            931)
FOR   416   .Light emmitting diode (437/905)    FOR 443 RECOIL IMPLANTATION (437/932)
FOR   417   ..Mounting and contact (437/906)    FOR 444 DUAL SPECIES IMPLANTATION OF
FOR   418   LASER PROCESSING OF FIELD EFFECT                  SEMICONDUCTOR (437/933)
               TRANSISTOR (FET) (437/907)       FOR 445 DOPANT ACTIVATION PROCESS (437/
FOR 419     LASER PROCESSING OF TRANSISTOR                    934)
               (437/908)                        FOR 446 BEAM WRITING OF PATTERNS (437/
FOR 420     MAKING TRANSISTOR ONLY (437/909)                  935)
FOR 421     MAKING JOSEPHSON JUNCTION DEVICE    FOR 447 BEAM PROCESSING OF COMPOUND
               (437/910)                                      SEMICONDUCTOR DEVICE (437/936)
FOR 422     MAKING JUNCTION-FIELD EFFECT        FOR 448 HYDROGEN PLASMA TREATMENT OF
               TRANSISTOR (J-FET) OR STATIC                   SEMICONDUCTOR DEVICE (437/937)
               INDUCTION THYRSISTOR (SIT)       FOR 449 MAKING RADIATION RESISTANT DEVICE
               DEVICE (437/911)                               (437/938)
FOR 423     MAKING METAL SEMICONDUCTOR FIELD    FOR 450 DEFECT CONTROL OF SEMICONDUCTOR
               EFFECT TRANSISTOR (MESFET)                     WAFER (PRETREATMENT) (437/939)
               DEVICE ONLY (437/912)            FOR 451 SELECTIVE OXIDATION OF ION
FOR 424     MAKING METAL OXIDE SEMICONDUCTOR                  AMORPHOUSIZED LAYERS (437/940)
               FIELD EFFECT TRANSISTOR          FOR 452 CONTROLLING CHARGING STATE AT
               (MOSFET) DEVICE (437/913)                       SEMICONDUCTOR-INSULATOR
FOR 425     MAKING NON-EPITAXIAL DEVICE (437/                  INTERFACE (437/941)
               914)                             FOR 453     INCOHERENT LIGHT PROCESSING (437/
FOR 426     MAKING VERTICALLY STACKED DEVICES                  942)
               (3-DIMENSIONAL STRUCTURE)        FOR 454     THERMALLY ASSISTED BEAM
               (437/915)                                       PROCESSING (437/943)
FOR 427     MAKING PHOTOCATHODE OR VIDICON      FOR 455     UTILIZING LIFT OFF (437/944)
               (437/916)                        FOR 456     STOICHIOMETRIC CONTROL OF HOST
FOR 428     MAKING LATERAL TRANSISTOR (437/                    SUBSTRATE COMPOSITION (437/
               917)                                            945)
FOR 429     MAKING RESISTOR (437/918)           FOR 457     SUBSTRATE SURFACE PREPARATION
FOR 430     MAKING CAPACITOR (437/919)                         (437/946)
FOR 431     MAKING SILICON-OXIDE-NITRIDE-       FOR 458     FORMING TAPERED EDGES ON
               OXIDE ON SILICON (SONOS)                        SUBSTRATE OR ADJACENT LAYERS
               DEVICE (437/920)                                (437/947)
FOR 432     MAKING STRAIN GAGE (437/921)        FOR   459   MOVABLE MASK (437/948)
FOR 433     MAKING FUSE OR FUSABLE DEVICE       FOR   460   CONTROLLED ATMOSPHERE (437/949)
               (437/922)                        FOR   461   SHALLOW DIFFUSION (437/950)
FOR 434     WITH REPAIR OR RECOVERY OF DEVICE   FOR   462   AMPHOTERIC DOPING (437/951)
               (437/923)                        FOR   463   CONTROLLING DIFFUSION PROFILE BY
FOR 435     HAVING SUBSTRATE OR MASK ALIGNING                  OXIDATION (437/952)
               FEATURE (437/924)                FOR 464     DIFFUSION OF OVERLAPPING REGIONS
FOR 436     SUBSTRATE SUPPORT OR CAPSULE                       (COMPENSATION) (437/953)
               CONSTRUCTION (437/925)           FOR 465     VERTICAL DIFFUSION THROUGH A
FOR 437     CONTINUOUS PROCESSING (437/926)                    LAYER (437/954)
FOR 438     FORMING HOLLOW BODIES AND           FOR   466   NONSELECTIVE DIFFUSION (437/955)
               ENCLOSED CAVITIES (437/927)      FOR   467   DISPLACING P-N JUNCTION (437/956)
FOR 439     ENERGY BEAM TREATING RADIATION      FOR   468   ELECTROMIGRATION (437/957)
               RESIST ON SEMICONDUCTOR (437/    FOR   469   SHAPED JUNCTION FORMATION (437/
               928)                                            958)



                                                                                   January 2009
438 - 24           CLASS 438 SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS



FOR 470 USING NONSTANDARD DOPANT (437/         FOR 498 DIFFUSING DOPANTS IN COMPOUND
              959)                                        SEMICONDUCTOR (437/987)
FOR 471    WASHED EMITTER PROCESS (437/960)
FOR 472    EMITTER DIP PREVENTION (OR
              UTILIZATION) (437/961)
FOR 473    UTILIZING SPECIAL MASKS (CARBON,
              ETC.) (437/962)
FOR 474    LOCALIZED HEATING CONTROL DURING
              FLUID GROWTH (437/963)
FOR 475    FLUID GROWTH INVOLVING VAPOR-
              LIQUID-SOLID STAGES (437/964)
FOR 476    FLUID GROWTH OF COMPOUNDS
              COMPOSED OF GROUPS II, IV, OR
              VI ELEMENTS (437/965)
FOR 477    FORMING THIN SHEETS (437/966)
FOR 478    PRODUCING POLYCRYSTALLINE
              SEMICONDUCTOR MATERIAL (437/
              967)
FOR 479    SELECTIVE OXIDATION OF
              POLYCRYSTALLINE LAYER (437/
              968)
FOR 480    FORMING GRADED ENERGY GAP LAYERS
              (437/969)
FOR 481    DIFFERENTIAL CRYSTAL GROWTH (437/
              970)
FOR 482    FLUID GROWTH DOPING CONTROL (437/
              971)
FOR 483    UTILIZING MELT-BACK (437/972)
FOR 484    SOLID PHASE EPITAXIAL GROWTH
              (437/973)
FOR 485    THINNING OR REMOVAL OF SUBSTRATE
              (437/974)
FOR 486    DIFFUSION ALONG GRAIN BOUNDARIES
              (437/975)
FOR 487    CONTROLLING LATTICE STRAIN (437/
              976)
FOR 488    UTILIZING ROUGHENED SURFACE (437/
              977)
FOR 489    UTILIZING MULTIPLE DIELECTRIC
              LAYERS (437/978)
FOR 490    UTILIZING THICK-THIN OXIDE
              FORMATION (437/979)
FOR 491    FORMING POLYCRYSTALLINE
              SEMICONDUCTOR PASSIVATION
              (437/980)
FOR 492    PRODUCING TAPERED ETCHING (437/
              981)
FOR 493    REFLOW OF INSULATOR (437/982)
FOR 494    OXIDATION OF GATE OR GATE CONTACT
              LAYER (437/983)
FOR 495    SELF-ALIGNING FEATURE (437/984)
FOR 496    DIFFERENTIAL OXIDATION AND
              ETCHING (437/985)
FOR 497    DIFFUSING LATERALLY AND ETCHING
              (437/986)


January 2009