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Microcontroller Core - NXP Semic

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Microcontroller Core - NXP Semic Powered By Docstoc
					Industrial Reference Design Platform
Microcontroller Core




 Release 1.0
LPC2300/2400 series members


                                                                                                                 LPC2478
                                                                                                       LPC2470


                                                                                                      • 96K SRAM
                                                                                                      • 512KB Flash
                                                                     LPC2468
                                LPC2378                                                               • Ethernet (MII+RMII)
                          LPC2368                                                                     • USB FS Device
Functionality




                                                                     • 96K Internal SRAM              • USB Host/OTG
                    LPC2366                                          • 512KB Flash                    • LCD Controller
                LPC2364       • Ethernet (RMII)                      • Ethernet (MII+RMII)            • 2 x CAN
                              • USB FS Device                        • USB FS Device                  • External Memory
                              • 2 x CAN                              • USB Host/OTG                     Controller
                  Part No.    Flash   RAM     MiniBus   Package      • 2 x CAN
                 LPC2364     128 KB   32 KB     No    LQFP/BGA 100   • External Memory Controller
                 LPC2366     256 KB   56 KB     No      LQFP100
                 LPC2368     512 KB   56 KB     No    LQFP/BGA 100
                 LPC2378     512 KB   56 KB     Yes     LQFP144




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                                                                                TSC Americas – IRD Platform – Microcontroller Core
IRD LPC2468 Block Diagram




                                                                                                        RST
                                                                                                        Vdd
                  64 kB              512 kB




                                                  TRST




                                                                                                        Vss
                                                         TMS




                                                                           TDO




                                                                                                        X2
                                                                                                        X1
                                                               TCK
 GPIO
 FAST




                                                                     TDI
                  SRAM               FLASH

                                                                                                          System
                                                         Test/Debug              Trace       PLL
   FAST          SRAM            Memory                                                                  Functions
                                                                                                                                   CS 3:0
   GPIO         Controller      Accelerator                                                               Brownout
                                                               ARM 7TDMI-S                                               External A 23:0
                                                                                                           Detect
                                                                                         System Clock
                                                                                                          Power-On       Memory BLS 3:0
                      Local Bus                                                                                                    OE,WE
                                                                                                            Reset       Controller D 31:0

AMBA High-speed Bus (AHB2)                     AHB                                 AMBA High-speed Bus (AHB1)
                                                                       AHB
                                              Bridge                  Bridge
MII/RMII   Ethernet   16kB                                                                                    16 kB
            w/DMA     SRAM                                                                      VIC           SRAM           USB
                                              AHB to AHB Bridge                                                                         D+,D-
                                                                                                                             OTG/
 32 kHz
             Real Time       Watchdog                                                                                        OHCI
                                                                     AHB to APB Bridge
 Vbat          Clock          Timer                                                                                         w. PHY

                                                                                           Advanced Peripheral Bus (APB)



3x I2C     SPI, SSP   SSP      I2S       4x UART                 2x CAN           2x ADC      DAC       GPIO          4x Timer        PWM




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                                                                                            TSC Americas – IRD Platform – Microcontroller Core
ARM7TDMI-S

 •The ARM7TDMI-S Core
 • Arm/Thumb Modes
 • Register Map
 • Vectored Interrupt Controller
     • Handling peripheral interrupts

T - Thumb architecture extension
D - Debug extensions
M - Enhanced multiplier (32x8) with 64-bit result option
I - EmbeddedICE Macrocell TM
S - Fully synthesizeable (soft IP)




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                                                   TSC Americas – IRD Platform – Microcontroller Core
ARM7 Registers & Modes of Operation
User and System
       r0         • Seventeen 32-bit Registers
       r1         • Four special purpose registers
       r2             • Stack Pointer
       r3
                      • Link Register
       r4
                      • Program Counter
       r5
                      • Program Status Register
       r6
                  • Seven Modes of Operation
       r7
       r8
                      •Software selectable
       r9
                      •Each mode has its own set of banked registers
      r10         • Modes of Operation
      r11             User        Supervisor
      r12             System      Abort
    r13 (SP)
                      FIQ         Undefined
    r14 (LR)
    r15 (PC)          IRQ
     CPSR


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                                          TSC Americas – IRD Platform – Microcontroller Core
ARM7 Registers & Modes of Operation
User and System
       r0
       r1
       r2
       r3
       r4
       r5
                                      Banked registers
       r6
       r7            FIQ            IRQ         Supervisor           Abort          Undefined
       r8            r8_fiq
       r9            r9_fiq
      r10           r10_fiq
      r11           r11_fiq
      r12           r12_fiq
    r13 (SP)      r13_fiq (SP)   r13_irq (SP)   r13_svc (SP)      r13_abt (SP)       r13_und (SP)
    r14 (LR)      r14_fiq (LR)   r14_irq (LR)   r14_svc (LR)      r14_abt (LR)      r14_und (LR)
    r15 (PC)

     CPSR          SPSR_fiq       SPSR_irq       SPSR_svc          SPSR_abt           SPSR_und


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                                                   TSC Americas – IRD Platform – Microcontroller Core
Vectored Interrupt Controller (VIC)
 1
   Table of
              2    Assert
                  Interrupt
  interrupt        Service     3
  sources         Request
                              Load an ISR         4    Notify CPU that a
                                                         peripheral is
                               address into
                                                          requesting
                              VIC hardware                 attention
 Enable
 Register                                                               5
                                               Change core
                                              operating mode                 Load PC with
                                                                             ISR address

                                                                                           6
                                                                                    Perform ISR
                                                                                      Actions

                                                                                                          7
                                                                                         Return to prior
                                                                                        operating mode


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                                                               TSC Americas – IRD Platform – Microcontroller Core
LPC23xx/24xx
Interrupt Sources and Vector Assignments




                     VIC                  VIC                                       VIC
                   Channel              Channel                                   Channel
    Block             #        Block       #           Block                         #
WDT                  0       SSP1          11       USB                               22
-                    1       PLL           12       CAN                               23
ARM Core 0           2       RTC           13       SD/MMC                            24
ARM Core 1           3       EINT0         14       GPDMA                             25
TIMER0               4       EINT1         15       TIMER2                            26
TIMER1               5       EINT2         16       TIMER3                            27
UART0                6       EINT3         17       UART2                             28
UART1                7       ADC0          18       UART3                             29
PWM1                 8       I2C1          19       I2C2                              30
I2C0                 9       BOD           20       I2S                               31
SPI, SSP0            10      Ethernet      21



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                                           TSC Americas – IRD Platform – Microcontroller Core
LPC2468
Memory Map
                                               Ethernet w/DMA & USB (OTG, OHCI w PHY)
4.0 GB                           0xFFFF FFFF
            AHB Peripherals
                                 0xF000 0000
                                               Timers, PWM, I2C, SPI, I2S, UARTs, CAN,
            APB Peripherals
                                 0xE000 0000   SSP, DAC, ADC
                                 0xDFF FFFF




         External Static and
          Dynamic Memory                       • Memory mapped I/O
                                               • Flash sector sizes from 4 kB to 32 kB
                                 0x8000 0000
                                               • Flash = 100,000 write- erase cycles
2.0 GB         Boot Block                      • Boot Block supports
          Reserved for on-chip                      • In-Application Programming
            Static Ram and                          • In-System Programming
           Special Registers
                                 0x4000 0000


             Flash Memory
0.0 GB                           0x0000 0000




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                                                        TSC Americas – IRD Platform – Microcontroller Core
LPC2468
System Functions
• Internal Reference Clock (IRC)
• External Clock ( X1/X2)
• Real Time Clock (RTXC1/RTXC2)
• Phase-Locked Loop
• Peripheral & CPU Clock
• Power Control For Each Peripheral
• Power-On/Reset
• Brown-Out Detection




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                                      TSC Americas – IRD Platform – Microcontroller Core
LPC2468
Clock Subsystem
CCLK & PLLCLK
 System clock (PLLCLK) can be                                                                   USB
                                                                                               Clock
                                                                                                           usbclk
                                                                                                         (48 MHz)
                                                                                                                      USB Block
                                                                                               Divider

 derived from three sources              Main
                                        Oscillator
                                                                        PLL                     CPU

   – Main crystal (1MHz to 20MHz)
                                                                                      pllclk             cclk
                                                                                               Clock                ARM7TDMI-S
                                                                                               Divider



   – Internal RC oscillator (IRC)
                                                        system                   Bypass                                             25 or
                                                      clock select                                                                          External
                                                                                Synchro-                              Ethernet     50 MHz
                                                                                  nizer                                                     Ethernet
                                                                                                                       Block
                                         Internal                                                                                             PHY

       • Factory Trimmed to +/-1%          R/C
                                        Oscillator             wdclk    Watchdog                                     Other AHB


   – Real time clock (RTC)
                                                                         Timer                                       Peripherals
                                                                                       Perpipheral
                                                                                         Clock
                                                       watchdog                        Generator
                                                      clock select                             pclk                     APB

  CPU clock (CCLK) can be                                                 RTC
                                                                        Prescaler
                                                                                                                     Peripherals




  separate from the APB peripherals       RTC
                                                               rtcclk   Real Time
                                                                          Clock

   – CCLK can be higher or lower than   Oscillator
                                                       RTC clock
                                                        select

     the APB peripherals
  Independent peripheral clocks
  Watchdog Timer has a separate
  clock selector mux

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                                                     TSC Americas – IRD Platform – Microcontroller Core
Independent Peripheral Clocks (PCLK)


PCLKSELx allows
four individual clock
selections for each
peripheral




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                           TSC Americas – IRD Platform – Microcontroller Core
Watchdog Timer Clock Selection




Watchdog Timer has a
separate clock selector mux
   WDSEL = 00 Select Internal RC
             = 01 Select APB Clock
             = 10 Select RTC
             = 11 Reserved

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                                     TSC Americas – IRD Platform – Microcontroller Core
LPC2468
Power Control
 Idle Mode – clock to the core is stopped
   – Execution of instructions is suspended until an interrupt or reset occurs
 Sleep Mode – PLL is turned off
   – Processor state and registers, peripheral registers and RAM values are
     preserved
       • Flash is left in standby mode
       • LPC2468 resumes operation when certain types of interrupts not requiring a
         clock occur or a reset happens

 Power down Mode – All clocks except for the RTC* are turned off
   – Flash memory is turned off
       • Minimal power consumption
       • LPC2468 wakes up when certain types of interrupts not requiring clock occur
         or a reset

          * RTC clock pins and VBAT pin connected and RTC mode enabled




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                                                      TSC Americas – IRD Platform – Microcontroller Core
Power Control for each Peripheral

•The PCONP Register determines if a peripheral is switched on or off
   • 0 = Off
   • 1 = On




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                                               TSC Americas – IRD Platform – Microcontroller Core
Reset
 Reset source can be
  –   External power applied
  –   External Reset pin
  –   Watchdog Timer Reset
  –   Brown-Out Detected
        •   VDD(3V3) below 2.95V
  –   Ethernet MAC Wake up
  –   CAN Wake up
  –   USB need clock wake up
  –   Real Time Clock wake up
  –   External Interrupt wake up
  –   GPIO Port 0 wake up
  –   GPIO Port 2 wake up
 Brown-Out Detect
  – The LPC2468 includes a 2 stage monitoring of
    the voltage on VDD(3V3)




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                                                   TSC Americas – IRD Platform – Microcontroller Core
External Memory Controller (EMC)
Chip Selects


  Eight Independent Chip Selects
    – Static and Dynamic Memory
        supported
  Static memory (RAM, ROM & Flash)
  features
    – 8, 16 and 32-bit wide support
    – Asynchronous page mode
    – Programmable wait states
    – OE & WE programmable delays
  Dynamic memory support
    – Software controlled self-refresh
      mode
    – 2K, 4K & 8K row address (up to
      512MB)
    – Separate refresh domains for
      auto-refresh through a chip reset




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                                          TSC Americas – IRD Platform – Microcontroller Core
External Memory Controller
Static Memory Interfacing




    D[31:0]: Data lines
    A[23:0]: Address lines
    OE: Low-active Output Enable
    WE: Low-active Write Enable
    BLS[3:0]: Low-active Byte Lane Select

    CS[3:0]: Low-active Chip Select




                                            32-bit wide memory bank interfaced
                                            to 16-bit memory chips




                                                                                                18
                                                TSC Americas – IRD Platform – Microcontroller Core
External Memory Controller
Dynamic Memory Interfacing


     D[31:0]: Data lines
     A[14:0]: Address lines
     CAS: Column Address Strobe
     RAS: Row Address Strobe
     WE: Low-Active Write Enable

     DYCS[3:0]: Low-Active Chip Select
     CLKOUT [1:0]: SDRAM Clocks
     CKEOUT [3:0]: SDRAM Clock Enable
     DQMOUT [3:0]: SDRAM Data Mask




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                                         TSC Americas – IRD Platform – Microcontroller Core
I/O Pin Selection
Each I/O pin can be used for one of several functions




         Example:
               P0.2 = TXD0 (UART0 TXD)
               P0.3 = RXD0 (UART0 RXD)
               Other pin selects are GPIO
         PINSEL0 =0x00000050

                                                                                              20
                                              TSC Americas – IRD Platform – Microcontroller Core
Memory Accelerator Module (MAM)
A patented feature of the LPC2000 family
►   Near zero wait state performance from Flash
    memory
                                                                                         • NXP LPC2129
      ►   Independent verification via EEMBC
          benchmark                                                                      •Competitor A
      ►   Up to 40% faster than other ARM7 TDMI-S                                        •Competitor B
          competitors                                    1.8


      ►   Other ARM7 TDMI-S implementations require      1.6


          execution from RAM to get high performance     1.4



►   Pre-Fetch Buffer                                     1.2



      ►   Stores up to four ARM or eight Thumb            1                                                  MicroA
                                                                                                             MicroN

          instructions                                   0.8                                                 MicroC



►   Data Bypass Buffer                                   0.6


                                                         0.4
      ►   Stores Flash memory flagged as data
                                                         0.2
►   Branch Trail Buffer                                   0
      ►   Allows tight loop of up to four ARM or eight         autcor
                                                                 autcor
                                                                          conven
                                                                           conven
                                                                                      fbital
                                                                                       fbital
                                                                                                 viterbi
                                                                                                   viterbi


          Thumb instructions




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                                                                 TSC Americas – IRD Platform – Microcontroller Core
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TSC Americas – IRD Platform – Microcontroller Core

				
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