armasb-martijn-meng

							3.3.3Caches&WriteBuers


The ARM processor has a hardware cache and a write buer which can be separately

enabled by raising a _ag on the memory management unit. Turning on these hardware

features is an optimization, and not essential to the operation of ARM Asbestos.
However, principal Bootldr developer Jamey Hicks reported a twofold improvement

in performance after enabling ARM hardware caching. Mr. Hicks said that write

buer improvements were less noticeable, so the ARM Asbestos eorts have been
focused primarily on enabling the cache. Data caches and instruction caches can be

separately enabled on the ARM MMU. On PXA chips the data and instruction caches

are separate entities, but on other chips they may be shared. When caching is on and
buering is o, ARM caches act as write-through, meaning data writes immediately

pass to memory.

   Maintaining cache coherence is a new problem for Asbestos. The x86 features a

physically addressed cache: all data is remembered by its physical address. Because
all writes to random-access memory are re_ected in subsequent reads, it is impossible

to get inconsistent cache state on x86. The only caveat is memory-mapped IO, which

must always be marked uncacheable. ARM processors feature virtually addressed
caches, in which cache data is associated with virtual addresses and cache lookups

occur in parallel with virtual address translation. The major problem with caching

on ARM is that Asbestos maps all user pages doubly: one virtual address is used in
user space, the other is used in kernel space.

   Maintaining two cached virtual address lines for one physical memory location can

cause cache inconsistencies. One example is the kernel block cache. The block cache

ful_lls a user write request by copying data to a user page_s kernel space address.
When a user process (even the one that wrote to the block) performs a read on this

cached address, the cache will return stale data. Although the data at the physical

address of the block has changed via the kernel virtual address, the user cache line
remembers the old data values. In this example, the solution is to invalidate the cache

lines at the virtual addresses of the user data, ensuring that all user read requests

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