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A 1.4 GHz/2.7V Programmable Divider for DRRS µ Standard in 0.6µm CMOS process Hossein Zarei, Omid Shoaei and S. M. Fakhraie Electrical and Computer Depatrment of Tehran University Email : h-zarei@khorshid.ece.ut.ac.ir Abstract [3,4]. In this paper, a gating method for programmability is used. With improved A 1.4 GHz programmable divider, whose timing of the divider, the divider can operate modulus can be varied from 16 to 31 is in the 1.4 GHz frequency band with low power presented with improved timing of multi- consumption. Fig.1 shows the principle of its modulus divider structure and high-speed low- operation. The division value includes all the voltage embedded logic D-Flip Flop. integers between 2k and 2k+1 -1, where k is the Programmability is achieved by gating the number of the output bits of the sigma-delta feedback signal of the first latch of the divide- modulator. Four control bits are used to by-2 blocks. For high-speed operation, the first swallow cycles at progressively lower control stage, is implemented with a simple frequencies. The qualifying logic embedded pseudo-NMOS logic gate. The programmable within each divide-by-2/3 block is used to limit divider has been simulated in a 0.6µm digital each stage to skip over one cycle per period of CMOS technology with 13mW power the output signal (OUT4). Therefore in this consumption at 2.7V power supply and structure, the division value is equal to 32+D0 1.4GHz maximum frequency. .20+D1.21 +D2 .22 +D3 .23 +D4.24 . I. Introduction CK High Speed 2/3 OUT0 2/3 OUT1 2/3 OUT2 2/3 OUT3 D0* D1* D2* D3* Digital Radio Relay Systems (DRRS) [1], is a High Speed Control Control Quailfier Control Quailfier Control Quailfier wireless data networking standard that operates Quailfier 0 1 2 3 in 1.4 GHz frequency band. Depending on the D1 D2 D3 application, the standard channel spacing may D0 be varied from 25 KHz to 3.5 MHz, with three equipment classes, GMSK, 4-QAM or 16- Fig. 1. A 16 modulus divider architecture. QAM. For a sigma-delta fractional-N frequency synthesizer, designed with this The divide-by-2/3 blocks can be implemented standard, a 16-multi-modulus divider was by augmenting a divide-by-2 circuit with needed. In the following section, we discuss gating logic. Fig. 2 demonstrates an example of improved gating method, so that the divider the gating approach. The setting of D0* leads coulde operate at required frequency with low- to the swallowing of a pulse from the output power dissipation. In Section III, the detail of signal. Fig. 3 illustrates the timing diagram of a circuit design is described. Simulation result is multi-modulus divider with three divide-by-2/3 given in Section IV. stages, where the division value is equal to “9”. As illustrated, each control bits of the divide- II. Architecture by-2/3 block becomes asserted, only when the input bit is set and the outputs of this block and Conventionally, a programmable divider is the next blocks are all zero. Referring to Fig. 2 implemented using an extension of the dual- and Fig. 3, the following equation should be modulus divider in which the overall divide- satisfied. by-2 sections are replaced with divide-by-2/3 blocks [2]. In the presented design, the Tqf + Td + TFF < TCK (1) programmability is achieved by the phase switching technique in which a multipelxer where Tqf is the delay of the first qualifying selects the appropriate phase of the D-Flip control circuit, Td is the delay of an AND gate Flop. For glitch free operation, several and TFF is the time window in which D0* is techniques have been reported, however, with “high”. these techniqus, the chip area of the divider and its power dissipation would be increased QA_0 QB_0 maximum speed of the divider is increased so D Q OUT_0 D Q that this structure can operate up to 1.4 GHz in Q Q CK a 0.6µm CMOS process with 2.7V supply voltage. D0* first control circuit OUT_1 OUT_2 III. Circuit Design D0 OUT_3 Fig.2. The first stage of the divider using gating method Realization of a high-speed frequency divider in mixed environments, requires careful Therefore, the maximum operating frequency attention to certain aspects of the circuit design of this structure is less than the simple divide- to contribute low-noise to sensitive analog by-2 (or a T-Flip Flop), since the gating and circuit. Therefore, source coupled logic (SCL) control circuits increase the propagation delay was used to implement the divider, where from the output of the second D-Flip Flop (D- differential signals at both input and output FF) to the input of the first D-FF. reduce the coupling noise from supply and substrate lines. In the first stage, in order to Clk reduce the delay time of the logic (AND, OR Out0 gates), the logic is embedded within each succeeding flip-flops. Out1 For the first stage, a high-speed divide-by-2/3 Out2 and control circuit is needed. The D-Flip Flop D0 * proposed in [5], is used for the first stage divide-by-2/3. Since, an inverted output of this Fig.3. Conventional timing diagram D-FF does not exist, the first control circuit is designed with single-ended input and output. Clk Fig. 5 shows a Pseudo-NMOS logic gate used Out0 for high-speed control circuit of the first stage. Out1 Also, a new embedded AND gate is used in the D-FF of the first stage. Out2 D0 * D0 Fig.4. Improved timing diagram. D0 * For this reason, the designers have not Out0 Out1 Out2 Out3 previously used this technique for high-speed programmable dividers [3]. However, for the required frequency (at 1.4 GHz), we chose this Fig. 5. The first control qualifier circuit structure with improved timing and the low- delay circuits for logic and qualifying control Fig. 6 shows this new D-FF with single-ended blocks. The advantage of this method is the input and output of the first control circuit. simple and low-power qualifying control When D0* is “low”, the P1, that is a relatively circuit, which leads to lower power large PMOS transistor, becomes “on” and the consumption for the divider, compared to the drain voltage of P1 equal to Vdd, so that the phase switching technique. The flip-flop output of the first latch (QA_0) becomes “low”. proposed in [5,6], is a low-voltage high-speed Therefore, the input frequency is divided by flip-flop, however, since the 25% duty cycle of “2”. When D0* is asserted, P1 becomes “off” the output signals of this D-flip flop is and the division ratio of this block would be undesirable, this topology has not been used, equal to “3”. Other control circuits are for the phase switching technique. implemented with static logic gates for low However, if this topology is used for the first power consumption and with differentially stage divide-by-2/3 of the programmable inputs and outputs. Also the Pseudo-NMOS D- divider, the constraint (1) is relaxed. Fig. 4 FF in [4] enables high-speed operation while illustrates the improved timing, where only the producing a large output swing. An embedded first stage divide-by-2/3 is designed with this logic D-FF designed with this proposed flip flop with 25% duty cycle of the output topology, is used for other divide-by-2/3 signal. Then the time window in which D0* is blocks (Fig. 7). Static CMOS inverters are “high”, is increased to 3TCK /2. Also the TFF of used for interstage buffering in the divider of this flip-flop is very small. Therefore, the path. Power Process Operation Power IV. Simulation Results supply frequency consumption Perrott [3] 3V 0.6µm 900 MHz 22 mW The programmable divider was simulated in a Craninkx [7] 3V 0.7µm 1.75 GHz 24 mW Krishnapura [4] 2V 0.25µm 5.5 GHz 60 mW 0.6µm technology with HSPICE simulator. The This work 3V 0.6µm 1.4 GHz 13 mW sizing of the divider, especially for the first 2V 900 MHz 4.6 mW stage is very critical for high-speed low-power Tabel. 1. Recent divider designs operation. Therefore, the maximum operating frequency and the power consumption, at 2.7V power supply, were observed to 1.4 GHz and References 13 mW, respectively. Also at 2V power supply [1] “Low capacity point to point Digital Radio voltage, the maximum frequency will be equal Relay Systems (DRRS) operating in the 1.4 to 0.95 GHz with 4.6mW power dissipation. GHz frequency band”, ETS 300 630, March Fig. 8 shows the maximum speed and power 1997. consumption versus supply voltage. Fig. 9 [2] T. Kamoto, N. Adachi, and K. Yamashita, shows the outputs of the first control and the “High-speed multi-modulus prescaler IC, ” in divide-by-2/3 blocks at 1.4 GHz frequency. Fourth IEEE International Conference on Universal Personal Communication. Record 5. Conclusion Gateway to the 21st Century, pp. 325-328, 1995. A low power programmable divider for DRRS [3] M. H. Perrott, T. L. Tewskbury, and C. G. standard in 1.4 GHz frequency band has been Sodini, “A 27mW fractional-N presented. With 25% duty cycle of the output synthesizer/modulator IC, ” in Proc. IEEE of the first divide-by-2/3 blocks, the constraint Solid-State Circuits Conf., San Francisco, CA, for high-speed operation is relaxed. In order to pp. 366-367, Feb. 1997. reduce the delay time, a new embedded AND [4] N. Krishnapura, P. Kinget, “A 5.3 GHz gate in the D-FF, was also used in the first Programmable Divider for HiPerLAN in stage. Simulation results demonstrated the low- 0.25µm CMOS, ” IEEE 25th Europan Solid- power consumption at the target frequency. State Circuits Confrence, Duisburg, Germany, Table. 1 presents recent publications on high- pp. 142-145, Sep. 1999. speed frequency dividers, designed with the [5] B. Razavi, Kwing F. Lee, and Ran H. Yan, phase switching technique. In comparison to “Design of high-speed, low-power frequency [3,7], the power dissipation has been very dividers and phase-locked loops in deep decreased. In [4], the divider was designed in submicron CMOS, ” IEEE JSSC, Vol.30, 0.25µm process so that the maximum No.2, pp. 101-109, Feb. 1995. frequency was increased to 5.5 GHz, however [6] H. Wang, “A 1.8V 3mW 16.8GHz the power consumption at 2V power supply Frequency Divider in 0.25µm CMOS,” IEEE and 950MHz operation frequency is nearly two ISSCC, pp. 196-197, Feb. 2000. times more than the power consumption of this [7] J. Craninkx and M. S. J. Steyaert, “ A work. 1.75GHz/3V dual–modulus divide-by-128/129 prescaler in 0.7µm CMOS, ” IEEE JSSC, Vol.31, No.7, pp. 890-897, July. 1997. P1 D0* CK CK QA_0 QB_BAR_0 QB_BAR_0 QB_0 QB_0 QA_BAR_0 CK_BAR CK_BAR QA_BAR_0 QA_0 QB_BAR_0 QB_0 Fig. 6. The first divide-by-2/3 block with 25% duty cycle QB_1 QB_BAR_1 QB_1 D1*_BAR QA_1 QB_BAR_1 D1* QA_BAR_1 OUT_0_BAR OUT_0_BAR OUT_0 OUT_0 QA_BAR_1 QA_1 QB_BAR_1 QB_1 OUT_0 OUT_0 OUT_0_BAR OUT_0_BAR Fig. 7. Other divide-by-2/3 blocks with 50% duty cycle 1.9 45 1.8 40 Maximum Frequency (GHZ) 1.7 Power Dissapiation (mw) 35 1.6 30 1.5 25 1.4 20 1.3 15 1.2 1.1 10 1 5 0.9 0 2 2.5 3 3.5 4 2 2.5 3 3.5 4 Power Supply (v) Fig.8. Maximum frequency and power dissipation versus power supply 3V 0V V (c k ) 3V 0V V (Q B _ 0 ) 3V 0V V (O U T _ 1 ) 3V 0V V (O U T _ 3 ) 3V 0V 15ns 45ns V (D 0 * ) Fig.9. Waveforms of the divider at 1.4 GHz